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authorGraeme Russ <graeme.russ@gmail.com>2010-10-07 20:03:21 +1100
committerGraeme Russ <graeme.russ@gmail.com>2010-10-07 20:03:21 +1100
commit8ffb2e8f3365d9b80e8f7e5b7c0130b875e3b899 (patch)
treee30b526bd603e0b608ee3feadcf83e7d8049e2ab /arch/i386
parent59c6d0ef9af5fe0daf1b95992d061a10b33e23d4 (diff)
downloadu-boot-linaro-stable-8ffb2e8f3365d9b80e8f7e5b7c0130b875e3b899.tar.gz
x86: Coding Style Cleanup
Perform some basic code cleanups of the x86 files
Diffstat (limited to 'arch/i386')
-rw-r--r--arch/i386/cpu/sc520/sc520.c54
-rw-r--r--arch/i386/cpu/sc520/sc520_asm.S642
-rw-r--r--arch/i386/cpu/start.S30
-rw-r--r--arch/i386/cpu/start16.S9
4 files changed, 362 insertions, 373 deletions
diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c
index 519bfd8b0..7acd471d9 100644
--- a/arch/i386/cpu/sc520/sc520.c
+++ b/arch/i386/cpu/sc520/sc520.c
@@ -41,7 +41,8 @@ volatile sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)0xfffef000;
void init_sc520(void)
{
- /* Set the UARTxCTL register at it's slower,
+ /*
+ * Set the UARTxCTL register at it's slower,
* baud clock giving us a 1.8432 MHz reference
*/
writeb(0x07, &sc520_mmcr->uart1ctl);
@@ -50,25 +51,30 @@ void init_sc520(void)
/* first set the timer pin mapping */
writeb(0x72, &sc520_mmcr->clksel); /* no clock frequency selected, use 1.1892MHz */
- /* enable PCI bus arbitrer */
- writeb(0x02, &sc520_mmcr->sysarbctl); /* enable concurrent mode */
+ /* enable PCI bus arbiter (concurrent mode) */
+ writeb(0x02, &sc520_mmcr->sysarbctl);
- writeb(0x1f, &sc520_mmcr->sysarbmenb); /* enable external grants */
- writeb(0x04, &sc520_mmcr->hbctl); /* enable posted-writes */
+ /* enable external grants */
+ writeb(0x1f, &sc520_mmcr->sysarbmenb);
+
+ /* enable posted-writes */
+ writeb(0x04, &sc520_mmcr->hbctl);
if (CONFIG_SYS_SC520_HIGH_SPEED) {
- writeb(0x02, &sc520_mmcr->cpuctl); /* set it to 133 MHz and write back */
+ /* set it to 133 MHz and write back */
+ writeb(0x02, &sc520_mmcr->cpuctl);
gd->cpu_clk = 133000000;
printf("## CPU Speed set to 133MHz\n");
} else {
- writeb(0x01, &sc520_mmcr->cpuctl); /* set it to 100 MHz and write back */
+ /* set it to 100 MHz and write back */
+ writeb(0x01, &sc520_mmcr->cpuctl);
printf("## CPU Speed set to 100MHz\n");
gd->cpu_clk = 100000000;
}
/* wait at least one millisecond */
- asm("movl $0x2000,%%ecx\n"
+ asm("movl $0x2000, %%ecx\n"
"0: pushl %%ecx\n"
"popl %%ecx\n"
"loop 0b\n": : : "ecx");
@@ -107,15 +113,15 @@ unsigned long init_sc520_dram(void)
/* set SDRAM speed here */
- refresh_rate/=78;
- if (refresh_rate<=1) {
- val = 0; /* 7.8us */
- } else if (refresh_rate==2) {
- val = 1; /* 15.6us */
- } else if (refresh_rate==3 || refresh_rate==4) {
- val = 2; /* 31.2us */
+ refresh_rate /= 78;
+ if (refresh_rate <= 1) {
+ val = 0; /* 7.8us */
+ } else if (refresh_rate == 2) {
+ val = 1; /* 15.6us */
+ } else if (refresh_rate == 3 || refresh_rate == 4) {
+ val = 2; /* 31.2us */
} else {
- val = 3; /* 62.4us */
+ val = 3; /* 62.4us */
}
tmp = (readb(&sc520_mmcr->drcctl) & 0xcf) | (val<<4);
@@ -124,9 +130,9 @@ unsigned long init_sc520_dram(void)
val = readb(&sc520_mmcr->drctmctl) & 0xf0;
if (cas_precharge_delay==3) {
- val |= 0x04; /* 3T */
+ val |= 0x04; /* 3T */
} else if (cas_precharge_delay==4) {
- val |= 0x08; /* 4T */
+ val |= 0x08; /* 4T */
} else if (cas_precharge_delay>4) {
val |= 0x0c;
}
@@ -139,8 +145,10 @@ unsigned long init_sc520_dram(void)
writeb(val, &c520_mmcr->drctmctl);
#endif
- /* We read-back the configuration of the dram
- * controller that the assembly code wrote */
+ /*
+ * We read-back the configuration of the dram
+ * controller that the assembly code wrote
+ */
dram_ctrl = readl(&sc520_mmcr->drcbendadr);
bd->bi_dram[0].start = 0;
@@ -148,7 +156,6 @@ unsigned long init_sc520_dram(void)
/* bank 0 enabled */
dram_present = bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22;
bd->bi_dram[0].size = bd->bi_dram[1].start;
-
} else {
bd->bi_dram[0].size = 0;
bd->bi_dram[1].start = bd->bi_dram[0].start;
@@ -179,11 +186,6 @@ unsigned long init_sc520_dram(void)
} else {
bd->bi_dram[3].size = 0;
}
-
-
-#if 0
- printf("Configured %d bytes of dram\n", dram_present);
-#endif
gd->ram_size = dram_present;
return dram_present;
diff --git a/arch/i386/cpu/sc520/sc520_asm.S b/arch/i386/cpu/sc520/sc520_asm.S
index fff56c00b..7c2de3113 100644
--- a/arch/i386/cpu/sc520/sc520_asm.S
+++ b/arch/i386/cpu/sc520/sc520_asm.S
@@ -172,366 +172,349 @@
.equ ROW11_DATA, 0x07070707 /* 11 row data/also bank switch (MASK) */
.equ ROW10_DATA, 0xaaaaaaaa /* 10 row data/also bank switch (MASK) */
-
- /*
- * initialize dram controller registers
- */
.globl mem_init
mem_init:
- xorw %ax,%ax
- movl $DBCTL, %edi
- movb %al, (%edi) /* disable write buffer */
-
- movl $ECCCTL, %edi
- movb %al, (%edi) /* disable ECC */
-
- movl $DRCTMCTL, %edi
- movb $0x1E,%al /* Set SDRAM timing for slowest */
- movb %al, (%edi)
-
- /*
- * setup loop to do 4 external banks starting with bank 3
- */
- movl $0xff000000,%eax /* enable last bank and setup */
- movl $DRCBENDADR, %edi /* ending address register */
- movl %eax, (%edi)
-
- movl $DRCCFG, %edi /* setup */
- movw $0xbbbb,%ax /* dram config register for */
- movw %ax, (%edi)
-
- /*
- * issue a NOP to all DRAMs
- */
- movl $DRCCTL, %edi /* setup DRAM control register with */
- movb $0x1,%al /* Disable refresh,disable write buffer */
- movb %al, (%edi)
- movl $CACHELINESZ, %esi /* just a dummy address to write for */
- movw %ax, (%esi)
- /*
- * delay for 100 usec? 200?
- * ******this is a cludge for now *************
- */
- movw $100,%cx
+ /* initialize dram controller registers */
+ xorw %ax, %ax
+ movl $DBCTL, %edi
+ movb %al, (%edi) /* disable write buffer */
+
+ movl $ECCCTL, %edi
+ movb %al, (%edi) /* disable ECC */
+
+ movl $DRCTMCTL, %edi
+ movb $0x1e, %al /* Set SDRAM timing for slowest */
+ movb %al, (%edi)
+
+ /* setup loop to do 4 external banks starting with bank 3 */
+ movl $0xff000000, %eax /* enable last bank and setup */
+ movl $DRCBENDADR, %edi /* ending address register */
+ movl %eax, (%edi)
+
+ movl $DRCCFG, %edi /* setup */
+ movw $0xbbbb, %ax /* dram config register for */
+ movw %ax, (%edi)
+
+ /* issue a NOP to all DRAMs */
+ movl $DRCCTL, %edi /* setup DRAM control register with */
+ movb $0x01, %al /* Disable refresh,disable write buffer */
+ movb %al, (%edi)
+ movl $CACHELINESZ, %esi /* just a dummy address to write for */
+ movw %ax, (%esi)
+
+ /* delay for 100 usec? */
+ movw $100, %cx
sizdelay:
- loop sizdelay /* we need 100 usec here */
- /***********************************************/
+ loop sizdelay
- /*
- * issue all banks precharge
- */
- movb $0x2,%al /* All banks precharge */
- movb %al, (%edi)
- movw %ax, (%esi)
+ /* issue all banks precharge */
+ movb $0x02, %al
+ movb %al, (%edi)
+ movw %ax, (%esi)
- /*
- * issue 2 auto refreshes to all banks
- */
- movb $0x4,%al /* Auto refresh cmd */
- movb %al, (%edi)
- movw $2,%cx
+ /* issue 2 auto refreshes to all banks */
+ movb $0x04, %al /* Auto refresh cmd */
+ movb %al, (%edi)
+ movw $0x02, %cx
refresh1:
- movw %ax, (%esi)
- loop refresh1
-
- /*
- * issue LOAD MODE REGISTER command
- */
- movb $0x3,%al /* Load mode register cmd */
- movb %al, (%edi)
- movw %ax, (%esi)
-
- /*
- * issue 8 more auto refreshes to all banks
- */
- movb $0x4,%al /* Auto refresh cmd */
- movb %al, (%edi)
- movw $8,%cx
+ movw %ax, (%esi)
+ loop refresh1
+
+ /* issue LOAD MODE REGISTER command */
+ movb $0x03, %al /* Load mode register cmd */
+ movb %al, (%edi)
+ movw %ax, (%esi)
+
+ /* issue 8 more auto refreshes to all banks */
+ movb $0x04, %al /* Auto refresh cmd */
+ movb %al, (%edi)
+ movw $0x0008, %cx
refresh2:
- movw %ax, (%esi)
- loop refresh2
+ movw %ax, (%esi)
+ loop refresh2
- /*
- * set control register to NORMAL mode
- */
- movb $0x0,%al /* Normal mode value */
- movb %al, (%edi)
+ /* set control register to NORMAL mode */
+ movb $0x00, %al /* Normal mode value */
+ movb %al, (%edi)
- /*
- * size dram starting with external bank 3 moving to external bank 0
- */
- movl $0x3,%ecx /* start with external bank 3 */
+ /*
+ * size dram starting with external bank 3
+ * moving to external bank 0
+ */
+ movl $0x3, %ecx /* start with external bank 3 */
nextbank:
- /*
- * write col 11 wrap adr
- */
- movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */
- movl $COL11_DATA, %eax /* pattern for max supported columns(11) */
- movl %eax, (%esi) /* write max col pattern at max col adr */
- movl (%esi), %ebx /* optional read */
- cmpl %ebx,%eax /* to verify write */
- jnz bad_ram /* this ram is bad */
- /*
- * write col 10 wrap adr
- */
+ /* write col 11 wrap adr */
+ movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */
+ movl $COL11_DATA, %eax /* pattern for max supported columns(11) */
+ movl %eax, (%esi) /* write max col pattern at max col adr */
+ movl (%esi), %ebx /* optional read */
+ cmpl %ebx, %eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
+
+ /* write col 10 wrap adr */
+ movl $COL10_ADR, %esi /* set address to 10 col wrap address */
+ movl $COL10_DATA, %eax /* pattern for 10 col wrap */
+ movl %eax, (%esi) /* write 10 col pattern @ 10 col wrap adr */
+ movl (%esi), %ebx /* optional read */
+ cmpl %ebx, %eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
+
+ /* write col 9 wrap adr */
+ movl $COL09_ADR, %esi /* set address to 9 col wrap address */
+ movl $COL09_DATA, %eax /* pattern for 9 col wrap */
+ movl %eax, (%esi) /* write 9 col pattern @ 9 col wrap adr */
+ movl (%esi), %ebx /* optional read */
+ cmpl %ebx, %eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
+
+ /* write col 8 wrap adr */
+ movl $COL08_ADR, %esi /* set address to min(8) col wrap address */
+ movl $COL08_DATA, %eax /* pattern for min (8) col wrap */
+ movl %eax, (%esi) /* write min col pattern @ min col adr */
+ movl (%esi), %ebx /* optional read */
+ cmpl %ebx, %eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
+
+ /* write row 14 wrap adr */
+ movl $ROW14_ADR, %esi /* set address to max row (14) wrap addr */
+ movl $ROW14_DATA, %eax /* pattern for max supported rows(14) */
+ movl %eax, (%esi) /* write max row pattern at max row adr */
+ movl (%esi), %ebx /* optional read */
+ cmpl %ebx, %eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
+
+ /* write row 13 wrap adr */
+ movl $ROW13_ADR, %esi /* set address to 13 row wrap address */
+ movl $ROW13_DATA, %eax /* pattern for 13 row wrap */
+ movl %eax, (%esi) /* write 13 row pattern @ 13 row wrap adr */
+ movl (%esi), %ebx /* optional read */
+ cmpl %ebx, %eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
+
+ /* write row 12 wrap adr */
+ movl $ROW12_ADR, %esi /* set address to 12 row wrap address */
+ movl $ROW12_DATA, %eax /* pattern for 12 row wrap */
+ movl %eax, (%esi) /* write 12 row pattern @ 12 row wrap adr */
+ movl (%esi), %ebx /* optional read */
+ cmpl %ebx, %eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
+
+ /* write row 11 wrap adr */
+ movl $ROW11_ADR, %edi /* set address to 11 row wrap address */
+ movl $ROW11_DATA, %eax /* pattern for 11 row wrap */
+ movl %eax, (%edi) /* write 11 row pattern @ 11 row wrap adr */
+ movl (%edi), %ebx /* optional read */
+ cmpl %ebx, %eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
- movl $COL10_ADR, %esi /* set address to 10 col wrap address */
- movl $COL10_DATA, %eax /* pattern for 10 col wrap */
- movl %eax, (%esi) /* write 10 col pattern @ 10 col wrap adr */
- movl (%esi), %ebx /* optional read */
- cmpl %ebx,%eax /* to verify write */
- jnz bad_ram /* this ram is bad */
- /*
- * write col 9 wrap adr
- */
- movl $COL09_ADR, %esi /* set address to 9 col wrap address */
- movl $COL09_DATA, %eax /* pattern for 9 col wrap */
- movl %eax, (%esi) /* write 9 col pattern @ 9 col wrap adr */
- movl (%esi), %ebx /* optional read */
- cmpl %ebx,%eax /* to verify write */
- jnz bad_ram /* this ram is bad */
- /*
- * write col 8 wrap adr
- */
- movl $COL08_ADR, %esi /* set address to min(8) col wrap address */
- movl $COL08_DATA, %eax /* pattern for min (8) col wrap */
- movl %eax, (%esi) /* write min col pattern @ min col adr */
- movl (%esi), %ebx /* optional read */
- cmpl %ebx,%eax /* to verify write */
- jnz bad_ram /* this ram is bad */
- /*
- * write row 14 wrap adr
- */
- movl $ROW14_ADR, %esi /* set address to max row (14) wrap addr */
- movl $ROW14_DATA, %eax /* pattern for max supported rows(14) */
- movl %eax, (%esi) /* write max row pattern at max row adr */
- movl (%esi), %ebx /* optional read */
- cmpl %ebx,%eax /* to verify write */
- jnz bad_ram /* this ram is bad */
- /*
- * write row 13 wrap adr
- */
- movl $ROW13_ADR, %esi /* set address to 13 row wrap address */
- movl $ROW13_DATA, %eax /* pattern for 13 row wrap */
- movl %eax, (%esi) /* write 13 row pattern @ 13 row wrap adr */
- movl (%esi), %ebx /* optional read */
- cmpl %ebx,%eax /* to verify write */
- jnz bad_ram /* this ram is bad */
- /*
- * write row 12 wrap adr
- */
- movl $ROW12_ADR, %esi /* set address to 12 row wrap address */
- movl $ROW12_DATA, %eax /* pattern for 12 row wrap */
- movl %eax, (%esi) /* write 12 row pattern @ 12 row wrap adr */
- movl (%esi), %ebx /* optional read */
- cmpl %ebx,%eax /* to verify write */
- jnz bad_ram /* this ram is bad */
- /*
- * write row 11 wrap adr
- */
- movl $ROW11_ADR, %edi /* set address to 11 row wrap address */
- movl $ROW11_DATA, %eax /* pattern for 11 row wrap */
- movl %eax, (%edi) /* write 11 row pattern @ 11 row wrap adr */
- movl (%edi), %ebx /* optional read */
- cmpl %ebx,%eax /* to verify write */
- jnz bad_ram /* this ram is bad */
- /*
- * write row 10 wrap adr --- this write is really to determine number of banks
- */
- movl $ROW10_ADR, %edi /* set address to 10 row wrap address */
- movl $ROW10_DATA, %eax /* pattern for 10 row wrap (AA) */
- movl %eax, (%edi) /* write 10 row pattern @ 10 row wrap adr */
- movl (%edi), %ebx /* optional read */
- cmpl %ebx,%eax /* to verify write */
- jnz bad_ram /* this ram is bad */
- /*
- * read data @ row 12 wrap adr to determine * banks,
- * and read data @ row 14 wrap adr to determine * rows.
- * if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM.
- * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4
- * if data @ row 12 wrap == 11 or 12, we have 4 banks,
- */
- xorw %di,%di /* value for 2 banks in DI */
- movl (%esi), %ebx /* read from 12 row wrap to check banks
- * (esi is setup from the write to row 12 wrap) */
- cmpl %ebx,%eax /* check for AA pattern (eax holds the aa pattern) */
- jz only2 /* if pattern == AA, we only have 2 banks */
+ /*
+ * write row 10 wrap adr --- this write is really to determine
+ * number of banks
+ */
+ movl $ROW10_ADR, %edi /* set address to 10 row wrap address */
+ movl $ROW10_DATA, %eax /* pattern for 10 row wrap (AA) */
+ movl %eax, (%edi) /* write 10 row pattern @ 10 row wrap adr */
+ movl (%edi), %ebx /* optional read */
+ cmpl %ebx, %eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
+
+ /*
+ * read data @ row 12 wrap adr to determine * banks,
+ * and read data @ row 14 wrap adr to determine * rows.
+ * if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM.
+ * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4
+ * if data @ row 12 wrap == 11 or 12, we have 4 banks,
+ */
+ xorw %di, %di /* value for 2 banks in DI */
+ movl (%esi), %ebx /* read from 12 row wrap to check banks */
+ /* (esi is setup from the write to row 12 wrap) */
+ cmpl %ebx, %eax /* check for AA pattern (eax holds the aa pattern) */
+ jz only2 /* if pattern == AA, we only have 2 banks */
/* 4 banks */
- movw $8,%di /* value for 4 banks in DI (BNK_CNT bit) */
- cmpl $ROW11_DATA, %ebx /* only other legitimate values are 11 */
- jz only2
- cmpl $ROW12_DATA, %ebx /* and 12 */
- jnz bad_ram /* its bad if not 11 or 12! */
+ movw $0x008, %di /* value for 4 banks in DI (BNK_CNT bit) */
+ cmpl $ROW11_DATA, %ebx /* only other legitimate values are 11 */
+ jz only2
+ cmpl $ROW12_DATA, %ebx /* and 12 */
+ jnz bad_ram /* its bad if not 11 or 12! */
/* fall through */
only2:
/*
* validate row mask
*/
- movl $ROW14_ADR, %esi /* set address back to max row wrap addr */
- movl (%esi), %eax /* read actual number of rows @ row14 adr */
+ movl $ROW14_ADR, %esi /* set address back to max row wrap addr */
+ movl (%esi), %eax /* read actual number of rows @ row14 adr */
- cmpl $ROW11_DATA, %eax /* row must be greater than 11 pattern */
- jb bad_ram
+ cmpl $ROW11_DATA, %eax /* row must be greater than 11 pattern */
+ jb bad_ram
- cmpl $ROW14_DATA, %eax /* and row must be less than 14 pattern */
- ja bad_ram
+ cmpl $ROW14_DATA, %eax /* and row must be less than 14 pattern */
+ ja bad_ram
+
+ cmpb %ah, %al /* verify all 4 bytes of dword same */
+ jnz bad_ram
+ movl %eax, %ebx
+ shrl $16, %ebx
+ cmpw %bx, %ax
+ jnz bad_ram
+
+ /*
+ * read col 11 wrap adr for real column data value
+ */
+ movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */
+ movl (%esi), %eax /* read real col number at max col adr */
+
+ /*
+ * validate column data
+ */
+ cmpl $COL08_DATA, %eax /* col must be greater than 8 pattern */
+ jb bad_ram
+
+ cmpl $COL11_DATA, %eax /* and row must be less than 11 pattern */
+ ja bad_ram
+
+ subl $COL08_DATA, %eax /* normalize column data to zero */
+ jc bad_ram
+ cmpb %ah, %al /* verify all 4 bytes of dword equal */
+ jnz bad_ram
+ movl %eax, %edx
+ shrl $16, %edx
+ cmpw %dx, %ax
+ jnz bad_ram
+
+ /*
+ * merge bank and col data together
+ */
+ addw %di, %dx /* merge of bank and col info in dl */
+
+ /*
+ * fix ending addr mask based upon col info
+ */
+ movb $0x03, %al
+ subb %dh, %al /* dh contains the overflow from the bank/col merge */
+ movb %bl, %dh /* bl contains the row mask (aa, 07, 0f, 1f or 3f) */
+ xchgw %cx, %ax /* cx = ax = 3 or 2 depending on 2 or 4 bank device */
+ shrb %cl, %dh
+ incb %dh /* ending addr is 1 greater than real end */
+ xchgw %cx, %ax /* cx is bank number again */
- cmpb %ah,%al /* verify all 4 bytes of dword same */
- jnz bad_ram
- movl %eax,%ebx
- shrl $16,%ebx
- cmpw %bx,%ax
- jnz bad_ram
- /*
- * read col 11 wrap adr for real column data value
- */
- movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */
- movl (%esi), %eax /* read real col number at max col adr */
- /*
- * validate column data
- */
- cmpl $COL08_DATA, %eax /* col must be greater than 8 pattern */
- jb bad_ram
-
- cmpl $COL11_DATA, %eax /* and row must be less than 11 pattern */
- ja bad_ram
-
- subl $COL08_DATA, %eax /* normalize column data to zero */
- jc bad_ram
- cmpb %ah,%al /* verify all 4 bytes of dword equal */
- jnz bad_ram
- movl %eax,%edx
- shrl $16,%edx
- cmpw %dx,%ax
- jnz bad_ram
- /*
- * merge bank and col data together
- */
- addw %di,%dx /* merge of bank and col info in dl */
- /*
- * fix ending addr mask based upon col info
- */
- movb $3,%al
- subb %dh,%al /* dh contains the overflow from the bank/col merge */
- movb %bl,%dh /* bl contains the row mask (aa, 07, 0f, 1f or 3f) */
- xchgw %cx,%ax /* cx = ax = 3 or 2 depending on 2 or 4 bank device */
- shrb %cl,%dh /* */
- incb %dh /* ending addr is 1 greater than real end */
- xchgw %cx,%ax /* cx is bank number again */
- /*
- * issue all banks precharge
- */
bad_reint:
- movl $DRCCTL, %esi /* setup DRAM control register with */
- movb $0x2,%al /* All banks precharge */
- movb %al, (%esi)
- movl $CACHELINESZ, %esi /* address to init read buffer */
- movw %ax, (%esi)
+ /*
+ * issue all banks precharge
+ */
+ movl $DRCCTL, %esi /* setup DRAM control register with */
+ movb $0x02, %al /* All banks precharge */
+ movb %al, (%esi)
+ movl $CACHELINESZ, %esi /* address to init read buffer */
+ movw %ax, (%esi)
- /*
- * update ENDING ADDRESS REGISTER
- */
- movl $DRCBENDADR, %edi /* DRAM ending address register */
- movl %ecx,%ebx
+ /*
+ * update ENDING ADDRESS REGISTER
+ */
+ movl $DRCBENDADR, %edi /* DRAM ending address register */
+ movl %ecx, %ebx
addl %ebx, %edi
- movb %dh, (%edi)
- /*
- * update CONFIG REGISTER
- */
- xorb %dh,%dh
- movw $0x00f,%bx
- movw %cx,%ax
- shlw $2,%ax
- xchgw %cx,%ax
- shlw %cl,%dx
- shlw %cl,%bx
- notw %bx
- xchgw %cx,%ax
- movl $DRCCFG, %edi
- mov (%edi), %ax
- andw %bx,%ax
- orw %dx,%ax
- movw %ax, (%edi)
- jcxz cleanup
-
- decw %cx
- movl %ecx,%ebx
- movl $DRCBENDADR, %edi /* DRAM ending address register */
- movb $0xff,%al
+ movb %dh, (%edi)
+
+ /*
+ * update CONFIG REGISTER
+ */
+ xorb %dh, %dh
+ movw $0x000f, %bx
+ movw %cx, %ax
+ shlw $2, %ax
+ xchgw %cx, %ax
+ shlw %cl, %dx
+ shlw %cl, %bx
+ notw %bx
+ xchgw %cx, %ax
+ movl $DRCCFG, %edi
+ movw (%edi), %ax
+ andw %bx, %ax
+ orw %dx, %ax
+ movw %ax, (%edi)
+ jcxz cleanup
+
+ decw %cx
+ movl %ecx, %ebx
+ movl $DRCBENDADR, %edi /* DRAM ending address register */
+ movb $0xff, %al
addl %ebx, %edi
- movb %al, (%edi)
- /*
- * set control register to NORMAL mode
- */
- movl $DRCCTL, %esi /* setup DRAM control register with */
- movb $0x0,%al /* Normal mode value */
- movb %al, (%esi)
- movl $CACHELINESZ, %esi /* address to init read buffer */
- movw %ax, (%esi)
- jmp nextbank
+ movb %al, (%edi)
+
+ /*
+ * set control register to NORMAL mode
+ */
+ movl $DRCCTL, %esi /* setup DRAM control register with */
+ movb $0x00, %al /* Normal mode value */
+ movb %al, (%esi)
+ movl $CACHELINESZ, %esi /* address to init read buffer */
+ movw %ax, (%esi)
+ jmp nextbank
cleanup:
- movl $DRCBENDADR, %edi /* DRAM ending address register */
- movw $4,%cx
- xorw %ax,%ax
+ movl $DRCBENDADR, %edi /* DRAM ending address register */
+ movw $0x04, %cx
+ xorw %ax, %ax
cleanuplp:
- movb (%edi), %al
- orb %al,%al
- jz emptybank
+ movb (%edi), %al
+ orb %al, %al
+ jz emptybank
- addb %ah,%al
- jns nottoomuch
+ addb %ah, %al
+ jns nottoomuch
- movb $0x7f,%al
+ movb $0x7f, %al
nottoomuch:
- movb %al,%ah
- orb $0x80,%al
- movb %al, (%edi)
+ movb %al, %ah
+ orb $0x80, %al
+ movb %al, (%edi)
emptybank:
- incl %edi
- loop cleanuplp
+ incl %edi
+ loop cleanuplp
#if defined CONFIG_SYS_SDRAM_DRCTMCTL
/* just have your hardware desinger _GIVE_ you what you need here! */
- movl $DRCTMCTL, %edi
- movb $CONFIG_SYS_SDRAM_DRCTMCTL,%al
- movb %al, (%edi)
+ movl $DRCTMCTL, %edi
+ movb $CONFIG_SYS_SDRAM_DRCTMCTL, %al
+ movb %al, (%edi)
#else
#if defined(CONFIG_SYS_SDRAM_CAS_LATENCY_2T) || defined(CONFIG_SYS_SDRAM_CAS_LATENCY_3T)
- /* set the CAS latency now since it is hard to do
- * when we run from the RAM */
- movl $DRCTMCTL, %edi /* DRAM timing register */
- movb (%edi), %al
+ /*
+ * Set the CAS latency now since it is hard to do
+ * when we run from the RAM
+ */
+ movl $DRCTMCTL, %edi /* DRAM timing register */
+ movb (%edi), %al
#ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
- andb $0xef, %al
+ andb $0xef, %al
#endif
#ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
- orb $0x10, %al
+ orb $0x10, %al
#endif
- movb %al, (%edi)
+ movb %al, (%edi)
#endif
#endif
- movl $DRCCTL, %edi /* DRAM Control register */
- movb $0x3,%al /* Load mode register cmd */
- movb %al, (%edi)
- movw %ax, (%esi)
+ movl $DRCCTL, %edi /* DRAM Control register */
+ movb $0x03, %al /* Load mode register cmd */
+ movb %al, (%edi)
+ movw %ax, (%esi)
- movl $DRCCTL, %edi /* DRAM Control register */
- movb $0x18,%al /* Enable refresh and NORMAL mode */
- movb %al, (%edi)
+ movl $DRCCTL, %edi /* DRAM Control register */
+ movb $0x18, %al /* Enable refresh and NORMAL mode */
+ movb %al, (%edi)
- jmp dram_done
+ jmp dram_done
bad_ram:
- xorl %edx,%edx
- xorl %edi,%edi
- jmp bad_reint
+ xorl %edx, %edx
+ xorl %edi, %edi
+ jmp bad_reint
dram_done:
@@ -551,17 +534,17 @@ init_ecc:
movl %ebx, %ebp
/* A nominal memory test: just a byte at each address line */
- movl %eax, %ecx
- shrl $0x1, %ecx
+ movl %eax, %ecx
+ shrl $0x1, %ecx
movl $0x1, %edi
memtest0:
movb $0xa5, (%edi)
- cmpb $0xa5, (%edi)
+ cmpb $0xa5, (%edi)
jne out
- shrl $1, %ecx
- andl %ecx,%ecx
+ shrl $0x1, %ecx
+ andl %ecx, %ecx
jz set_ecc
- shll $1, %edi
+ shll $0x1, %edi
jmp memtest0
set_ecc:
@@ -570,21 +553,24 @@ set_ecc:
xorl %esi, %esi
xorl %edi, %edi
xorl %eax, %eax
- shrl $2, %ecx
+ shrl $0x2, %ecx
cld
rep stosl
- /* enable read, write buffers */
- movb $0x11, %al
- movl $DBCTL, %edi
- movb %al, (%edi)
- /* enable NMI mapping for ECC */
- movl $ECCINT, %edi
- mov $0x10, %al
- movb %al, (%edi)
- /* Turn on ECC */
- movl $ECCCTL, %edi
- mov $0x05, %al
- movb %al, (%edi)
+
+ /* enable read, write buffers */
+ movb $0x11, %al
+ movl $DBCTL, %edi
+ movb %al, (%edi)
+
+ /* enable NMI mapping for ECC */
+ movl $ECCINT, %edi
+ movb $0x10, %al
+ movb %al, (%edi)
+
+ /* Turn on ECC */
+ movl $ECCCTL, %edi
+ movb $0x05, %al
+ movb %al,(%edi)
#endif
out:
@@ -596,7 +582,7 @@ out:
*/
.globl get_mem_size
get_mem_size:
- movl $DRCBENDADR, %edi /* DRAM ending address register */
+ movl $DRCBENDADR, %edi /* DRAM ending address register */
bank0: movl (%edi), %eax
movl %eax, %ecx
diff --git a/arch/i386/cpu/start.S b/arch/i386/cpu/start.S
index 3cea04b4c..f67a1b7a6 100644
--- a/arch/i386/cpu/start.S
+++ b/arch/i386/cpu/start.S
@@ -45,7 +45,7 @@ _i386boot_start:
/* Turn of cache (this might require a 486-class CPU) */
movl %cr0, %eax
- orl $0x60000000,%eax
+ orl $0x60000000, %eax
movl %eax, %cr0
wbinvd
@@ -54,13 +54,13 @@ _i386boot_start:
_start:
/* This is the 32-bit cold-reset entry point */
- movl $0x18,%eax /* Load our segement registes, the
+ movl $0x18, %eax /* Load our segement registes, the
* gdt have already been loaded by start16.S */
- movw %ax,%fs
- movw %ax,%ds
- movw %ax,%gs
- movw %ax,%es
- movw %ax,%ss
+ movw %ax, %fs
+ movw %ax, %ds
+ movw %ax, %gs
+ movw %ax, %es
+ movw %ax, %ss
/* Clear the interupt vectors */
lidt blank_idt_ptr
@@ -79,7 +79,7 @@ _start:
* to store the return address */
/* Early platform init (setup gpio, etc ) */
- mov $early_board_init_ret, %ebp
+ mov $early_board_init_ret, %ebp
jmp early_board_init
early_board_init_ret:
@@ -92,12 +92,12 @@ early_board_init_ret:
/* size memory */
mov $mem_init_ret, %ebp
- jmp mem_init
+ jmp mem_init
mem_init_ret:
/* fetch memory size (into %eax) */
mov $get_mem_size_ret, %ebp
- jmp get_mem_size
+ jmp get_mem_size
get_mem_size_ret:
/* Check we have enough memory for stack */
@@ -113,7 +113,7 @@ get_mem_size_ret:
jmp die
mem_ok:
/* Set stack pointer to upper memory limit*/
- movl %eax, %esp
+ movl %eax, %esp
/* indicate progress */
movw $0x02, %ax
@@ -150,12 +150,12 @@ stack_ok:
wbinvd
/* Get upper memory limit */
- movl %esp, %ecx
- subl $CONFIG_SYS_STACK_SIZE, %ecx
+ movl %esp, %ecx
+ subl $CONFIG_SYS_STACK_SIZE, %ecx
/* Create a Stack Frame */
- pushl %ebp
- movl %esp, %ebp
+ pushl %ebp
+ movl %esp, %ebp
/* stack_limit parameter */
pushl %ecx
diff --git a/arch/i386/cpu/start16.S b/arch/i386/cpu/start16.S
index ebe583584..2a5cca9d6 100644
--- a/arch/i386/cpu/start16.S
+++ b/arch/i386/cpu/start16.S
@@ -31,7 +31,8 @@
.code16
.globl start16
start16:
- /* First we let the BSP do some early initialization
+ /*
+ * First we let the BSP do some early initialization
* this code have to map the flash to its final position
*/
mov $board_init16_ret, %bp
@@ -40,7 +41,7 @@ board_init16_ret:
/* Turn of cache (this might require a 486-class CPU) */
movl %cr0, %eax
- orl $0x60000000,%eax
+ orl $0x60000000, %eax
movl %eax, %cr0
wbinvd
@@ -50,7 +51,7 @@ o32 cs lgdt gdt_ptr
/* Now, we enter protected mode */
movl %cr0, %eax
- orl $1,%eax
+ orl $1, %eax
movl %eax, %cr0
/* Flush the prefetch queue */
@@ -61,7 +62,7 @@ ff:
/* Finally jump to the 32bit initialization code */
movw $code32start, %ax
- movw %ax,%bp
+ movw %ax, %bp
o32 cs ljmp *(%bp)
/* 48-bit far pointer */