Move architecture-specific includes to arch/$ARCH/include/asm

This helps to clean up the include/ directory so that it only contains
non-architecture-specific headers and also matches Linux's directory
layout which many U-Boot developers are already familiar with.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>

139 files changed, 64793 insertions, 0 deletions

diff --git a/arch/blackfin/include/asm/bfin_logo_230x230.h b/arch/blackfin/include/asm/bfin_logo_230x230.h
new file mode 100644
index 000000000..3a79631fc
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_logo_230x230.h
@@ -0,0 +1,2377 @@
+/*
+ * Generated by EasyLogo, (C) 2000 by Paolo Scaffardi
+ *
+ * To use this, include it and call: easylogo_plot(screen,&bfin_logo, width,x,y)
+ *
+ * Where:	'screen'	is the pointer to the frame buffer
+ *		'width'	is the screen width
+ *		'x'		is the horizontal position
+ *		'y'		is the vertical position
+ */
+
+#define EASYLOGO_ENABLE_GZIP 37470
+
+static unsigned char EASYLOGO_DECOMP_BUFFER[158700];
+
+#include <video_easylogo.h>
+
+#define	DEF_BFIN_LOGO_WIDTH		230
+#define	DEF_BFIN_LOGO_HEIGHT		230
+#define	DEF_BFIN_LOGO_PIXELS		52900
+#define	DEF_BFIN_LOGO_BPP		24
+#define	DEF_BFIN_LOGO_PIXEL_SIZE	3
+#define	DEF_BFIN_LOGO_SIZE		158700
+
+unsigned char DEF_BFIN_LOGO_DATA[] = {
+ 0x1f, 0x8b, 0x08, 0x00, 0x58, 0x7e, 0x68, 0x47, 0x00, 0x03, 0xec, 0x9d, 0x07, 0x5c, 0x53, 0xe7,
+ 0xfe, 0xc6, 0x55, 0xb6, 0x04, 0x42, 0x80, 0x40, 0x26, 0x59, 0x24, 0x04, 0x02, 0x01, 0xc2, 0x86,
+ 0x00, 0x61, 0x84, 0xbd, 0xf7, 0x5e, 0x22, 0x22, 0x88, 0xb6, 0x55, 0x71, 0xd4, 0x75, 0x6b, 0x7b,
+ 0xfd, 0x54, 0x6b, 0xeb, 0xac, 0xb7, 0xe3, 0x52, 0xad, 0x5e, 0x57, 0xd5, 0xf6, 0xfe, 0x6b, 0x5b,
+ 0xab, 0xd6, 0xd6, 0xb6, 0xee, 0x81, 0x5a, 0x95, 0xdb, 0xd6, 0x5d, 0x17, 0x52, 0x07, 0x60, 0xbc,
+ 0xc5, 0xf5, 0xbf, 0x4f, 0x38, 0x35, 0x0d, 0x43, 0x2a, 0xdc, 0xaa, 0xb7, 0xf1, 0x3c, 0x9f, 0xa8,
+ 0x90, 0x9c, 0x93, 0xf7, 0x3d, 0x9e, 0xef, 0x79, 0xde, 0xe7, 0xf7, 0xe6, 0x9c, 0x93, 0x41, 0x83,
+ 0x48, 0xfd, 0x31, 0x1a, 0xdc, 0x9b, 0x9e, 0x76, 0xa7, 0x48, 0x91, 0xd2, 0x8a, 0xa0, 0x71, 0x48,
+ 0xa7, 0x8c, 0x8d, 0x8d, 0x4d, 0x3a, 0x65, 0xd6, 0x43, 0xa6, 0xa6, 0xa6, 0x78, 0xde, 0xb8, 0x53,
+ 0x46, 0x46, 0x46, 0x24, 0xc3, 0xa4, 0x9e, 0xa4, 0x74, 0x94, 0x82, 0x3d, 0xa0, 0x68, 0x6e, 0x6e,
+ 0x6e, 0x61, 0x61, 0x61, 0x69, 0x69, 0x69, 0x6d, 0x6d, 0x6d, 0x63, 0x63, 0x63, 0x6b, 0x6b, 0x67,
+ 0x6f, 0x4f, 0x77, 0xe8, 0x2a, 0x7b, 0x7b, 0x7b, 0x5b, 0x5b, 0x5b, 0xbc, 0x6a, 0x65, 0x65, 0x85,
+ 0x25, 0xb1, 0x0a, 0x56, 0x24, 0xe8, 0xc5, 0xfb, 0x90, 0xf4, 0x92, 0x7a, 0x4c, 0x22, 0x40, 0x05,
+ 0x69, 0xb0, 0xcd, 0xa1, 0x43, 0x87, 0x5a, 0x59, 0x59, 0x83, 0x43, 0x00, 0xc9, 0x62, 0xb1, 0x79,
+ 0x3c, 0x9e, 0x48, 0x24, 0x92, 0x4a, 0xa5, 0xee, 0xee, 0xee, 0x5e, 0x5e, 0x5e, 0xde, 0xde, 0x0a,
+ 0x85, 0xc2, 0x87, 0x78, 0x78, 0x7b, 0x7b, 0xcb, 0xe5, 0x9e, 0x32, 0x99, 0xcc, 0xc5, 0xc5, 0x45,
+ 0x28, 0x14, 0x72, 0x38, 0x1c, 0x47, 0x47, 0x47, 0x80, 0x0d, 0xc2, 0x09, 0x7a, 0x61, 0xbf, 0x84,
+ 0xf1, 0x3e, 0xed, 0xed, 0x23, 0x65, 0x38, 0x02, 0x4e, 0x80, 0x0a, 0x68, 0xc1, 0x4e, 0x41, 0x9a,
+ 0x9d, 0x9d, 0x1d, 0x8b, 0xc5, 0x12, 0x08, 0x84, 0x6e, 0x6e, 0x6e, 0x00, 0x32, 0x30, 0x30, 0x30,
+ 0x3c, 0x5c, 0x15, 0x13, 0x13, 0x9b, 0x9c, 0x9c, 0x9c, 0x99, 0x99, 0x99, 0x97, 0x97, 0x57, 0x58,
+ 0x58, 0x58, 0xf4, 0x40, 0x05, 0x05, 0x05, 0xb9, 0xb9, 0xb9, 0x19, 0x19, 0x19, 0x89, 0x89, 0x89,
+ 0x51, 0x51, 0xd1, 0x21, 0x21, 0x4a, 0x1f, 0x1f, 0x1f, 0x00, 0x0c, 0xc2, 0xd9, 0x6c, 0x36, 0x9d,
+ 0x4e, 0xa7, 0x52, 0xa9, 0xe0, 0x1f, 0xae, 0x4b, 0x72, 0x4b, 0xea, 0xbf, 0x97, 0xce, 0x54, 0xe1,
+ 0x87, 0x18, 0xd6, 0x99, 0x4c, 0x96, 0x50, 0x28, 0xf2, 0xf0, 0xf0, 0x08, 0x0c, 0x0c, 0x8a, 0x8e,
+ 0x8e, 0x4e, 0x4d, 0x4d, 0xcd, 0xcf, 0xcf, 0x2f, 0x2f, 0x2f, 0xaf, 0xae, 0xae, 0xae, 0xa9, 0xa9,
+ 0xc1, 0x0f, 0x59, 0x59, 0x59, 0x49, 0x49, 0xc9, 0xb1, 0xb1, 0xb1, 0x11, 0x11, 0x11, 0xa1, 0xa1,
+ 0xa1, 0x51, 0x51, 0x51, 0x09, 0x09, 0x89, 0x19, 0x19, 0x99, 0xc5, 0xc5, 0x25, 0x58, 0xa6, 0xb6,
+ 0xb6, 0x76, 0xd8, 0xb0, 0xca, 0x82, 0x82, 0xc2, 0xf4, 0xf4, 0x0c, 0x2c, 0x13, 0x12, 0x12, 0xe2,
+ 0xe9, 0xe9, 0x29, 0x12, 0x39, 0x83, 0x7f, 0xd8, 0x35, 0x85, 0x42, 0x41, 0x43, 0x64, 0xd0, 0x25,
+ 0x35, 0x30, 0x11, 0xac, 0x62, 0xd4, 0x46, 0xf8, 0xa4, 0xd3, 0x1d, 0x9c, 0x9c, 0x78, 0x6e, 0x6e,
+ 0x32, 0x80, 0x0a, 0xd2, 0xb2, 0xb3, 0x73, 0x4a, 0x4a, 0x4a, 0x2b, 0x2a, 0x86, 0x95, 0x95, 0x95,
+ 0xc5, 0xc7, 0x27, 0x20, 0x06, 0xc0, 0x2a, 0x41, 0xda, 0xef, 0xbe, 0x27, 0x98, 0x94, 0x48, 0x24,
+ 0x6a, 0x75, 0x0c, 0xbc, 0xb7, 0xbc, 0xbc, 0xa2, 0xb4, 0xb4, 0x14, 0xc0, 0x27, 0x24, 0x24, 0x04,
+ 0x07, 0x07, 0x23, 0x4e, 0xf0, 0xf9, 0x7c, 0x64, 0x0c, 0x78, 0xb8, 0x8e, 0xdb, 0x27, 0xb0, 0x99,
+ 0xa4, 0x0c, 0x40, 0x44, 0x06, 0x00, 0x36, 0x60, 0x15, 0x08, 0x01, 0x24, 0xb9, 0x5c, 0x0e, 0xc3,
+ 0x4c, 0x4e, 0x4e, 0x01, 0xa8, 0x70, 0xcb, 0xac, 0xac, 0x6c, 0x95, 0x4a, 0xe5, 0xec, 0xec, 0x8c,
+ 0x9c, 0x30, 0xb0, 0x26, 0x70, 0x2c, 0x30, 0x99, 0xcc, 0x80, 0x80, 0x80, 0xf4, 0xf4, 0xf4, 0xa2,
+ 0xa2, 0xe2, 0x92, 0x92, 0x92, 0xb4, 0xb4, 0xb4, 0xb0, 0xb0, 0x30, 0x34, 0x84, 0xe6, 0x50, 0xa9,
+ 0xc1, 0xd2, 0x91, 0x13, 0xc8, 0xba, 0x8c, 0xd4, 0xef, 0x8a, 0xb0, 0x56, 0x04, 0x4b, 0x0c, 0xd3,
+ 0xa8, 0xa7, 0x80, 0x50, 0x78, 0x78, 0x38, 0x06, 0x71, 0x8c, 0xe6, 0x30, 0xc6, 0xc8, 0xc8, 0x48,
+ 0x57, 0x57, 0x57, 0x90, 0xfc, 0x47, 0x81, 0x04, 0x0f, 0x07, 0xf9, 0x88, 0x10, 0x88, 0xbe, 0x08,
+ 0x15, 0x00, 0x58, 0xa9, 0x0c, 0x45, 0x13, 0xa8, 0xe6, 0x10, 0x42, 0x10, 0x9b, 0xd1, 0x19, 0x12,
+ 0x5a, 0x52, 0x0f, 0x13, 0x70, 0x85, 0xb3, 0x61, 0xec, 0x86, 0xb5, 0x8a, 0xc5, 0x62, 0x0c, 0xd6,
+ 0x48, 0xaa, 0x95, 0x95, 0x95, 0xa5, 0xa5, 0x65, 0xf0, 0x58, 0x00, 0x3c, 0x60, 0x53, 0xed, 0x5b,
+ 0x78, 0x5b, 0x2e, 0x97, 0xab, 0x54, 0x2a, 0xcb, 0xca, 0x80, 0x6d, 0x39, 0x92, 0x86, 0xaf, 0xaf,
+ 0x2f, 0x4a, 0x33, 0x74, 0x03, 0x9d, 0x21, 0xcc, 0xf6, 0x71, 0xb4, 0x4b, 0xea, 0x4f, 0x2d, 0x02,
+ 0x57, 0xc4, 0x48, 0xd4, 0x41, 0xa8, 0xe5, 0x61, 0xa7, 0x18, 0xac, 0x47, 0x8d, 0x1a, 0x15, 0x1b,
+ 0x1b, 0x87, 0x67, 0xf0, 0xd2, 0xe3, 0xee, 0x00, 0x9a, 0x60, 0x30, 0x18, 0x28, 0xe8, 0xd0, 0x68,
+ 0x6e, 0x6e, 0x2e, 0x82, 0x07, 0xba, 0xc1, 0x66, 0xb3, 0xa9, 0x54, 0x2a, 0x99, 0x6c, 0x49, 0x75,
+ 0x13, 0x81, 0x2b, 0xd8, 0x70, 0x72, 0x72, 0x52, 0x28, 0x14, 0x89, 0x89, 0x89, 0x55, 0x55, 0x55,
+ 0x70, 0x3c, 0x81, 0x40, 0xf0, 0x18, 0xc7, 0xe5, 0xde, 0xde, 0x16, 0xcd, 0xc1, 0xcc, 0x8b, 0x8b,
+ 0x8b, 0x87, 0x0d, 0x1b, 0x96, 0x9c, 0x9c, 0xec, 0xe7, 0xe7, 0x2f, 0x14, 0x0a, 0x11, 0x51, 0xc8,
+ 0x84, 0x40, 0x4a, 0x27, 0xe0, 0x8a, 0x71, 0x19, 0xb8, 0x02, 0x15, 0x3f, 0x3f, 0x3f, 0x84, 0x49,
+ 0xe0, 0x9a, 0x91, 0x91, 0x01, 0x67, 0x7b, 0x5c, 0x4d, 0xa2, 0xb8, 0x33, 0x33, 0xb3, 0xa0, 0x52,
+ 0xcd, 0x29, 0x14, 0x23, 0x53, 0xd3, 0x9e, 0x1c, 0x22, 0x48, 0x87, 0x85, 0x85, 0x03, 0xda, 0xbc,
+ 0xbc, 0x7c, 0x04, 0x69, 0x89, 0x44, 0x82, 0x84, 0x80, 0x72, 0x0c, 0xfd, 0x24, 0xa1, 0x7d, 0xc6,
+ 0x05, 0x00, 0xe0, 0x5d, 0x88, 0x8b, 0x18, 0x7f, 0x7d, 0x7c, 0x7c, 0x80, 0x2b, 0x92, 0x24, 0xca,
+ 0x76, 0xd4, 0x44, 0x8f, 0xaf, 0x51, 0x54, 0x77, 0x34, 0x16, 0x53, 0x22, 0x97, 0x4b, 0xbd, 0xbd,
+ 0xb8, 0x62, 0x89, 0xb5, 0x9d, 0x9d, 0x09, 0x8e, 0x8e, 0xae, 0x28, 0xc2, 0xf3, 0x51, 0xf7, 0xa1,
+ 0x22, 0x2b, 0x2d, 0x2d, 0x45, 0x69, 0x86, 0x72, 0xcc, 0xd1, 0xd1, 0x11, 0xd0, 0x92, 0xf1, 0xe0,
+ 0x19, 0x17, 0x00, 0x80, 0xa1, 0xc1, 0xc1, 0x3c, 0x3c, 0x3c, 0x30, 0x0a, 0x23, 0x09, 0x04, 0x05,
+ 0x05, 0x61, 0x08, 0x7e, 0xac, 0x8d, 0x9a, 0x98, 0x9b, 0xf3, 0xa4, 0xd2, 0xb0, 0x98, 0x98, 0xf8,
+ 0xf4, 0xf4, 0xa8, 0xc4, 0x44, 0x45, 0x70, 0x30, 0x57, 0x2c, 0xa6, 0xd0, 0x68, 0x20, 0x59, 0x7f,
+ 0x31, 0x90, 0x89, 0x94, 0x92, 0x9d, 0x9d, 0x53, 0x51, 0x51, 0x81, 0x5c, 0xed, 0xe2, 0x22, 0xb5,
+ 0xb7, 0xa7, 0xa3, 0x6f, 0x8f, 0x32, 0xf7, 0x4b, 0xca, 0x20, 0x45, 0xc4, 0x57, 0xa4, 0x44, 0xb1,
+ 0x58, 0xac, 0x56, 0xab, 0x4b, 0x4b, 0xcb, 0x30, 0x04, 0x03, 0xe0, 0xc7, 0xdd, 0x2e, 0xc2, 0x80,
+ 0x1b, 0xfc, 0x3c, 0x37, 0xaf, 0xaa, 0xa6, 0x66, 0x04, 0xea, 0xac, 0x92, 0x92, 0xc8, 0x84, 0x04,
+ 0x99, 0x8f, 0x8f, 0x1d, 0x8b, 0x65, 0xd4, 0xa3, 0xc4, 0x03, 0xa5, 0x28, 0xc4, 0xca, 0xca, 0xb4,
+ 0x7d, 0x73, 0x76, 0x16, 0xa3, 0xb7, 0x88, 0x2b, 0xe4, 0xec, 0xc1, 0x33, 0x28, 0x22, 0x0f, 0x58,
+ 0x59, 0x59, 0x71, 0xb9, 0xdc, 0xc0, 0xc0, 0xc0, 0xa2, 0xa2, 0xe2, 0xcc, 0xcc, 0xcc, 0x27, 0x80,
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+ 0x9d, 0x3d, 0xe1, 0xc5, 0x29, 0xc3, 0x46, 0x8c, 0x48, 0xcc, 0xc8, 0x80, 0xd9, 0x32, 0xf8, 0x3c,
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+ 0x5a, 0x65, 0x65, 0xa5, 0x9d, 0x9d, 0xdd, 0x93, 0x68, 0x78, 0xf0, 0x60, 0xaa, 0x83, 0x03, 0x22,
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+ 0xf2, 0xe4, 0x8a, 0xea, 0xea, 0xc4, 0x8c, 0x4c, 0xdf, 0x90, 0x10, 0x06, 0x9f, 0x6f, 0xd4, 0x35,
+ 0x45, 0x03, 0x4e, 0x0e, 0x87, 0x53, 0x5c, 0x5c, 0x92, 0x93, 0x93, 0xe3, 0xef, 0xef, 0xcf, 0x66,
+ 0x73, 0x10, 0x68, 0xc9, 0xa9, 0x83, 0x67, 0x4d, 0xd8, 0xe3, 0x30, 0x2b, 0x91, 0x48, 0x14, 0x11,
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+ 0x6b, 0xd6, 0xd8, 0x09, 0x13, 0x2b, 0x47, 0x8e, 0xcc, 0x2a, 0x28, 0x50, 0xc5, 0xc6, 0xba, 0x29,
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+ 0x4a, 0x0a, 0x22, 0x37, 0x9d, 0x4e, 0x47, 0x6d, 0x48, 0x66, 0x83, 0x67, 0x47, 0xd8, 0xd7, 0xd8,
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+ 0xa0, 0x52, 0x49, 0xbd, 0xbd, 0xe9, 0x3c, 0x27, 0xe3, 0x1e, 0xf9, 0x04, 0x1d, 0x8e, 0x8a, 0x8a,
+ 0x2a, 0x2f, 0xd7, 0x56, 0x61, 0x42, 0xa1, 0xd0, 0xc6, 0xc6, 0xc6, 0xb4, 0xb7, 0x99, 0x31, 0x52,
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+ 0x97, 0x44, 0x4c, 0x63, 0xb3, 0xcc, 0xa9, 0xd4, 0xc1, 0x5d, 0xe7, 0x0d, 0x08, 0xc1, 0x5a, 0x8b,
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+ 0xb6, 0x58, 0xe5, 0x66, 0xa5, 0x7f, 0xc0, 0x40, 0x1f, 0xec, 0xbd, 0x60, 0xc1, 0x02, 0xe4, 0x15,
+ 0x15, 0x28, 0x51, 0xa3, 0xe2, 0xc9, 0x95, 0x1e, 0xc7, 0x81, 0xde, 0x11, 0x76, 0x9d, 0x3c, 0x79,
+ 0x2a, 0x3a, 0x26, 0x36, 0x2e, 0x2e, 0x7e, 0xcc, 0x45, 0xc6, 0x60, 0xd1, 0xd1, 0xd1, 0x00, 0x2a,
+ 0xa8, 0x15, 0x09, 0xb8, 0xad, 0xaa, 0x62, 0x48, 0x4f, 0xc1, 0xfe, 0xcb, 0xde, 0xc6, 0xe0, 0x61,
+ 0xc1, 0x4b, 0x0f, 0x1f, 0x3e, 0x2c, 0x2c, 0x2a, 0x86, 0x9f, 0x42, 0xce, 0x23, 0x0a, 0xa3, 0xd1,
+ 0xe9, 0xd0, 0x06, 0xff, 0xb6, 0x34, 0x2b, 0x6d, 0x62, 0xe8, 0x7e, 0x42, 0x3a, 0x0e, 0x54, 0x37,
+ 0x04, 0x6b, 0xd0, 0xba, 0x40, 0x05, 0x34, 0xe7, 0xaa, 0x55, 0xab, 0xb4, 0xb4, 0xb4, 0x0e, 0xec,
+ 0x37, 0x70, 0xb0, 0x30, 0x76, 0xb3, 0x36, 0xf4, 0xb1, 0xdf, 0xf5, 0xd4, 0x7a, 0x5d, 0xa4, 0xb9,
+ 0x4a, 0x8c, 0x19, 0xd1, 0xb8, 0x1a, 0x6f, 0x29, 0x4e, 0xd0, 0x00, 0xe0, 0x55, 0x5a, 0xb4, 0x29,
+ 0x3d, 0xd4, 0x6c, 0xb1, 0x97, 0x95, 0xf6, 0x09, 0x73, 0x83, 0xdd, 0x3b, 0x77, 0x2c, 0x5f, 0xbe,
+ 0x7c, 0xde, 0xbc, 0x79, 0x5f, 0x7f, 0xfd, 0xf5, 0x3f, 0xfe, 0xf1, 0x4f, 0xf1, 0x80, 0xb7, 0x91,
+ 0x79, 0x19, 0x5f, 0xc9, 0xc9, 0x13, 0x9b, 0xf3, 0x9e, 0x3b, 0xe7, 0x9c, 0xf0, 0xfc, 0xf9, 0xed,
+ 0x3b, 0x77, 0xc6, 0xec, 0x0e, 0x00, 0x2d, 0xe7, 0xe4, 0xe6, 0xf6, 0x0f, 0x0c, 0x40, 0xc4, 0x22,
+ 0xf8, 0x1a, 0x20, 0x86, 0xfa, 0x7b, 0xfe, 0xd5, 0x71, 0xf0, 0xde, 0x86, 0x22, 0x06, 0x1d, 0x3d,
+ 0x09, 0x0e, 0x4e, 0x4d, 0x4d, 0xbb, 0x79, 0xeb, 0x96, 0x91, 0x91, 0xd1, 0xf7, 0xdf, 0x2f, 0x9d,
+ 0x3e, 0x7d, 0xfa, 0x47, 0x59, 0xb0, 0xeb, 0x77, 0x36, 0xf1, 0x60, 0x06, 0x71, 0xff, 0x1a, 0xd4,
+ 0xc2, 0xac, 0x59, 0xb3, 0xe4, 0xe5, 0xe5, 0xd5, 0xd5, 0xd5, 0xd7, 0xad, 0x5b, 0xa7, 0xbb, 0x5d,
+ 0xf7, 0xe0, 0x81, 0xfd, 0x76, 0x16, 0x07, 0xcf, 0xda, 0x98, 0x5c, 0xb3, 0x3b, 0xe0, 0x6b, 0xb7,
+ 0xeb, 0xb1, 0xcd, 0xe6, 0x10, 0x8b, 0x15, 0xa1, 0x16, 0x1a, 0xa1, 0x16, 0xcb, 0x42, 0x8e, 0xac,
+ 0x0e, 0xb0, 0xd9, 0x7a, 0xcb, 0x4e, 0xdf, 0xe9, 0x88, 0x91, 0xf1, 0x7e, 0xfd, 0x2d, 0x5b, 0xb6,
+ 0xa8, 0xaa, 0xaa, 0xc1, 0xef, 0x83, 0xba, 0x25, 0xb4, 0xbd, 0x78, 0x26, 0x91, 0xac, 0xac, 0x2c,
+ 0xb9, 0x25, 0xc4, 0xa9, 0xe0, 0xa7, 0x21, 0xe6, 0xe6, 0xe6, 0xe3, 0xc7, 0x8f, 0x97, 0x9e, 0xe9,
+ 0x86, 0xe8, 0x20, 0x27, 0x37, 0xaf, 0xb1, 0xa9, 0xa9, 0xba, 0xa6, 0xb6, 0xa6, 0xb6, 0xae, 0xbe,
+ 0xbe, 0x01, 0x92, 0x00, 0x75, 0xea, 0x2d, 0x26, 0xc9, 0xbd, 0xd6, 0x50, 0x2b, 0x3f, 0xd6, 0x90,
+ 0xd4, 0x3f, 0xa3, 0xa1, 0x70, 0x21, 0xc6, 0x1e, 0x3f, 0x0e, 0xba, 0x7f, 0xff, 0x81, 0xc5, 0xe1,
+ 0xc3, 0x2b, 0x57, 0xae, 0x9a, 0x3d, 0x7b, 0x36, 0x25, 0x0c, 0xfe, 0x58, 0x04, 0xbe, 0xb7, 0x89,
+ 0x1b, 0xca, 0x00, 0x5d, 0x54, 0x3d, 0x4a, 0xe8, 0x02, 0xba, 0xa4, 0xd0, 0x55, 0x83, 0xef, 0x26,
+ 0x7a, 0xd6, 0xb4, 0x75, 0xf4, 0xf6, 0xec, 0x3e, 0x60, 0xb8, 0xdf, 0xe4, 0xa0, 0xb1, 0xb9, 0xe9,
+ 0x21, 0x73, 0x93, 0x43, 0x26, 0x07, 0x8d, 0x0c, 0x0d, 0xf6, 0xed, 0xd0, 0xd5, 0x85, 0x9e, 0x5f,
+ 0xbc, 0x78, 0x31, 0x94, 0x00, 0x34, 0x06, 0xf2, 0x81, 0xea, 0x10, 0x94, 0xd0, 0x48, 0xd4, 0x62,
+ 0x8f, 0x73, 0xe7, 0xcd, 0xfb, 0xe1, 0x87, 0x35, 0x87, 0x8f, 0x1c, 0xb9, 0x77, 0xcf, 0x3b, 0x2e,
+ 0x3e, 0x3e, 0x2b, 0x2b, 0x3b, 0xbf, 0xa0, 0xb0, 0xb0, 0xa8, 0x08, 0x3e, 0x8b, 0x48, 0x85, 0x45,
+ 0x05, 0x05, 0x85, 0x79, 0x79, 0xf9, 0x59, 0xd9, 0x39, 0xf1, 0x09, 0xcf, 0xa3, 0xa0, 0xbd, 0x62,
+ 0x62, 0x93, 0x93, 0x53, 0x10, 0xa3, 0xe1, 0x4b, 0x1c, 0x7d, 0x71, 0xda, 0xfb, 0xa4, 0x22, 0xc8,
+ 0x66, 0x89, 0x84, 0x2f, 0x8b, 0x8a, 0x8a, 0x8b, 0x8a, 0x4b, 0x88, 0xcd, 0xf3, 0xca, 0xca, 0xc9,
+ 0x7e, 0x0c, 0x08, 0x90, 0xea, 0xea, 0xea, 0x1a, 0xd4, 0x14, 0xd4, 0x95, 0xba, 0xfa, 0x06, 0xa4,
+ 0xfa, 0x86, 0x17, 0x89, 0xf8, 0x58, 0x57, 0x5f, 0x43, 0xae, 0x96, 0x80, 0xb3, 0xaa, 0x18, 0x8c,
+ 0x8a, 0xca, 0xca, 0xb2, 0xf2, 0x8a, 0xd2, 0xd2, 0xb2, 0xe2, 0x92, 0x52, 0xdc, 0xa7, 0xe8, 0x35,
+ 0x3f, 0xf4, 0x1e, 0x09, 0x5e, 0x26, 0x35, 0x2d, 0x8d, 0x1a, 0x43, 0xf8, 0xa1, 0x29, 0x25, 0x35,
+ 0x31, 0x31, 0x09, 0x1a, 0x2c, 0x3c, 0x22, 0xe2, 0x86, 0xa7, 0xe7, 0xc1, 0x43, 0x87, 0x96, 0x2d,
+ 0x5b, 0x8e, 0x28, 0xe6, 0xf3, 0xcf, 0x3f, 0xff, 0xd3, 0x71, 0xac, 0x84, 0x8d, 0x16, 0xba, 0x20,
+ 0x49, 0xbc, 0x11, 0xfc, 0x38, 0xa0, 0x0b, 0x0f, 0x02, 0x47, 0x0f, 0xe2, 0x5d, 0xb8, 0x70, 0x21,
+ 0x00, 0x8c, 0x60, 0x7f, 0xe9, 0x52, 0x0d, 0x38, 0x1a, 0xfc, 0xa1, 0xa2, 0xa2, 0x02, 0x4a, 0x84,
+ 0x12, 0x46, 0x90, 0x05, 0x2a, 0x43, 0x5d, 0xa6, 0xd6, 0x27, 0x91, 0x96, 0xf4, 0xd4, 0x82, 0xba,
+ 0x38, 0x0d, 0xc2, 0x43, 0x5b, 0x5b, 0xdb, 0xf6, 0xe8, 0x51, 0x77, 0x77, 0x8f, 0xdb, 0xb7, 0x6f,
+ 0x7b, 0xfb, 0xf8, 0xf8, 0xfa, 0xfa, 0x51, 0xe6, 0xeb, 0xeb, 0x8b, 0x4f, 0x77, 0xef, 0x7a, 0x5d,
+ 0xbf, 0x71, 0x03, 0x61, 0xc2, 0x79, 0x17, 0x57, 0xd7, 0x0b, 0x6e, 0x97, 0x2e, 0x5f, 0xf6, 0xf4,
+ 0xbc, 0x79, 0xd7, 0xcb, 0x0b, 0xe7, 0x8d, 0x9c, 0xf8, 0xf1, 0xec, 0x3e, 0x58, 0xe7, 0xc1, 0x03,
+ 0x7f, 0xff, 0x87, 0x8f, 0x1e, 0x05, 0x04, 0x06, 0x3e, 0x46, 0x40, 0x18, 0x1c, 0x1c, 0xf2, 0xec,
+ 0x59, 0x58, 0x58, 0x18, 0xca, 0x37, 0x22, 0x32, 0x32, 0x32, 0x8a, 0xa8, 0x37, 0x54, 0xc2, 0x47,
+ 0x7c, 0x19, 0x16, 0x1e, 0x8e, 0x13, 0x82, 0x9f, 0x3e, 0x85, 0x2c, 0xa4, 0x36, 0x32, 0xf3, 0x7f,
+ 0xf8, 0x10, 0x37, 0xc1, 0xad, 0x3e, 0xfa, 0xd3, 0x7d, 0x14, 0x43, 0xae, 0x79, 0x7b, 0x7b, 0x43,
+ 0x0f, 0x20, 0x33, 0xad, 0x6d, 0x6c, 0x7e, 0xd4, 0xd4, 0x54, 0x5a, 0xb8, 0x90, 0x6a, 0x98, 0xfd,
+ 0xb3, 0xe8, 0xd8, 0x37, 0x1b, 0xd5, 0x3d, 0x41, 0x75, 0xae, 0x7d, 0x32, 0xd2, 0xb3, 0x46, 0x36,
+ 0xed, 0x7e, 0x05, 0xd7, 0x3c, 0x71, 0x22, 0x31, 0x89, 0x60, 0x2a, 0x69, 0x93, 0x27, 0x4f, 0x01,
+ 0x9e, 0xc9, 0xb1, 0xca, 0x5f, 0x50, 0x23, 0x00, 0xdf, 0xd0, 0xca, 0x47, 0x8d, 0xd7, 0x42, 0x15,
+ 0x80, 0x3f, 0x02, 0xec, 0x37, 0x6f, 0xd9, 0xb2, 0x67, 0x8f, 0x9e, 0x91, 0x91, 0xb1, 0x89, 0x89,
+ 0xa9, 0xa9, 0xa9, 0x99, 0xa9, 0x19, 0x99, 0x4c, 0xcd, 0xf0, 0xd1, 0xc8, 0xd8, 0xd8, 0xc0, 0x60,
+ 0xff, 0x1e, 0x3d, 0xbd, 0x9d, 0xbb, 0x76, 0xed, 0xda, 0xbd, 0x5b, 0x6f, 0xef, 0xde, 0xfd, 0x86,
+ 0x86, 0x07, 0x0f, 0x1e, 0x7a, 0x79, 0xda, 0xc7, 0x4b, 0x66, 0x66, 0xc4, 0x06, 0x6a, 0xe6, 0x16,
+ 0xb0, 0xc3, 0x87, 0x41, 0xfd, 0x96, 0x96, 0xd6, 0xd6, 0x36, 0xb6, 0xb6, 0xc4, 0xdc, 0x5e, 0x7b,
+ 0x87, 0x63, 0xc7, 0x8e, 0x39, 0x3a, 0x3a, 0x1e, 0x3f, 0x7e, 0xfc, 0x04, 0x12, 0xfe, 0x8f, 0x4f,
+ 0xf8, 0x0e, 0x07, 0x50, 0xdd, 0x50, 0xf4, 0x96, 0x56, 0x56, 0x38, 0x1f, 0xd7, 0xe1, 0x62, 0xdc,
+ 0x02, 0xb7, 0xfa, 0xe8, 0x8f, 0xf7, 0x71, 0x12, 0x95, 0xab, 0x46, 0x46, 0x7b, 0xf6, 0xec, 0xd9,
+ 0xbc, 0x79, 0xb3, 0xaa, 0x9a, 0x1a, 0x8a, 0x00, 0x6e, 0xf4, 0xf7, 0x19, 0x66, 0xf0, 0x7b, 0x9a,
+ 0x44, 0xcf, 0x1a, 0xd5, 0xb4, 0x4b, 0x2d, 0x88, 0xfa, 0x0f, 0xd2, 0xf0, 0x07, 0x25, 0x0e, 0x71,
+ 0x14, 0xe7, 0x8c, 0x49, 0xad, 0xa3, 0xef, 0x06, 0x3c, 0xe3, 0xaa, 0xaf, 0xc6, 0x8f, 0x9f, 0x3e,
+ 0x7d, 0x06, 0xf4, 0x06, 0xc8, 0x56, 0x5d, 0x7d, 0x09, 0xa2, 0x00, 0x98, 0x86, 0x86, 0x06, 0xc5,
+ 0xdb, 0xf8, 0xa8, 0xbe, 0x64, 0x89, 0xaa, 0xaa, 0xaa, 0xb2, 0xb2, 0xb2, 0xa2, 0x12, 0x61, 0xca,
+ 0x8b, 0x16, 0x8d, 0x10, 0x3b, 0x75, 0xe2, 0x6f, 0x67, 0xcb, 0x60, 0xcb, 0x97, 0xaf, 0xa0, 0xa6,
+ 0xe3, 0xad, 0x26, 0xec, 0x07, 0x68, 0x18, 0xca, 0xf0, 0x07, 0x3e, 0xe0, 0x2b, 0x44, 0xa6, 0x38,
+ 0x8c, 0x93, 0x70, 0x2e, 0xce, 0xc7, 0x55, 0xbf, 0xe9, 0x33, 0x7d, 0xb8, 0xbd, 0xc8, 0x55, 0xf5,
+ 0x25, 0xc8, 0x70, 0x64, 0x3b, 0x32, 0xff, 0xab, 0xaf, 0xc6, 0x7f, 0xac, 0x45, 0x11, 0xff, 0x9d,
+ 0x4d, 0x0c, 0x60, 0xf1, 0x94, 0x0a, 0xea, 0x6f, 0xea, 0xfb, 0xb7, 0xbc, 0x83, 0x78, 0xaa, 0xc5,
+ 0xf8, 0xf1, 0x5f, 0x4f, 0x98, 0x30, 0x11, 0xbe, 0x09, 0x84, 0x3d, 0xc2, 0xd9, 0x53, 0xa9, 0xbf,
+ 0xf1, 0x25, 0x98, 0xfc, 0xdb, 0x09, 0x13, 0xbe, 0x21, 0x6d, 0x02, 0xce, 0x23, 0x89, 0x7d, 0xf4,
+ 0x99, 0xbf, 0xa9, 0x4d, 0x23, 0x6d, 0xfa, 0x88, 0x8d, 0xcc, 0xce, 0x9b, 0x41, 0x7d, 0x9c, 0x36,
+ 0x62, 0xbf, 0xc7, 0xa3, 0x7c, 0x0c, 0x13, 0xe7, 0x2a, 0x32, 0x12, 0xd9, 0x8e, 0xcc, 0x47, 0x11,
+ 0xfc, 0xfb, 0x37, 0xc6, 0xfe, 0x9b, 0x18, 0xa5, 0x37, 0xa8, 0x0e, 0x05, 0x8a, 0xae, 0xc7, 0x34,
+ 0x1c, 0xfa, 0x9f, 0x51, 0xf6, 0x86, 0x33, 0x7f, 0x07, 0x13, 0x3b, 0x94, 0x3f, 0xbb, 0x8d, 0x76,
+ 0x88, 0xa3, 0xe1, 0xfa, 0xff, 0x01, 0x00, 0x07, 0xdb, 0x50, 0xec, 0x6b, 0x02, 0x00
+};
+
+fastimage_t bfin_logo = {
+		DEF_BFIN_LOGO_DATA,
+		DEF_BFIN_LOGO_WIDTH,
+		DEF_BFIN_LOGO_HEIGHT,
+		DEF_BFIN_LOGO_BPP,
+		DEF_BFIN_LOGO_PIXEL_SIZE,
+		DEF_BFIN_LOGO_SIZE
+};
diff --git a/arch/blackfin/include/asm/bfin_logo_rgb565_230x230.h b/arch/blackfin/include/asm/bfin_logo_rgb565_230x230.h
new file mode 100644
index 000000000..c5b0be96f
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_logo_rgb565_230x230.h
@@ -0,0 +1,1242 @@
+/*
+ * Generated by EasyLogo, (C) 2000 by Paolo Scaffardi
+ *
+ * To use this, include it and call: easylogo_plot(screen,&bfin_logo, width,x,y)
+ *
+ * Where:	'screen'	is the pointer to the frame buffer
+ *		'width'	is the screen width
+ *		'x'		is the horizontal position
+ *		'y'		is the vertical position
+ */
+
+#define EASYLOGO_ENABLE_GZIP 19303
+
+static unsigned char EASYLOGO_DECOMP_BUFFER[105800];
+
+#include <video_easylogo.h>
+
+#define	DEF_BFIN_LOGO_WIDTH		230
+#define	DEF_BFIN_LOGO_HEIGHT		230
+#define	DEF_BFIN_LOGO_PIXELS		52900
+#define	DEF_BFIN_LOGO_BPP		16
+#define	DEF_BFIN_LOGO_PIXEL_SIZE	2
+#define	DEF_BFIN_LOGO_SIZE		105800
+
+unsigned char DEF_BFIN_LOGO_DATA[] = {
+ 0x1f, 0x8b, 0x08, 0x00, 0x9d, 0x56, 0x26, 0x4b, 0x00, 0x03, 0xec, 0x5d, 0x7f, 0x4c, 0x1b, 0x77,
+ 0x96, 0xb7, 0x2e, 0xe8, 0x3a, 0x52, 0xb8, 0xd3, 0x64, 0xc3, 0x36, 0xd3, 0x14, 0xac, 0xf1, 0xc6,
+ 0xa6, 0x36, 0x0c, 0xbd, 0x3a, 0xb8, 0x5a, 0x66, 0x01, 0x29, 0xb6, 0x82, 0x14, 0x5c, 0xb8, 0xdb,
+ 0xb8, 0xa1, 0x5b, 0x9c, 0x3a, 0x77, 0xc4, 0x41, 0x2a, 0x72, 0xd1, 0x2a, 0x75, 0x68, 0xeb, 0x38,
+ 0x20, 0x85, 0x23, 0x48, 0x45, 0x24, 0x77, 0x65, 0x09, 0x55, 0x59, 0x97, 0x53, 0x2d, 0x99, 0x53,
+ 0x39, 0x99, 0x3f, 0xd2, 0x42, 0x6e, 0x49, 0xcc, 0x4a, 0x41, 0x35, 0x52, 0x90, 0x1c, 0xa9, 0xd9,
+ 0x9a, 0xdb, 0x90, 0x18, 0xa9, 0xd6, 0xc5, 0x52, 0xb9, 0x3b, 0x77, 0xc5, 0xea, 0x9c, 0x86, 0xe6,
+ 0x72, 0xdf, 0x37, 0x5f, 0x0f, 0xe3, 0xdf, 0x36, 0xb6, 0x93, 0xb4, 0x61, 0x3e, 0x5f, 0x85, 0xc4,
+ 0x63, 0x67, 0xfc, 0xb5, 0x3f, 0xbc, 0xf7, 0x7d, 0xdf, 0xf7, 0xde, 0xf7, 0x3d, 0x89, 0x44, 0x84,
+ 0x88, 0x1f, 0x32, 0xe8, 0x34, 0x43, 0xc4, 0x8f, 0x05, 0x98, 0x2f, 0x2d, 0xa1, 0x25, 0x3a, 0x88,
+ 0x7e, 0xb2, 0x9f, 0x74, 0xc6, 0x0c, 0x78, 0xdc, 0x81, 0xae, 0xc3, 0xb3, 0x22, 0xab, 0x3f, 0x64,
+ 0x60, 0x0e, 0x81, 0x41, 0x27, 0xb9, 0x40, 0x05, 0xa9, 0x12, 0x99, 0x5c, 0xd6, 0xa4, 0xea, 0x54,
+ 0x0f, 0x6e, 0x8e, 0x4e, 0x55, 0x93, 0x4a, 0x2e, 0x2b, 0x91, 0x05, 0x29, 0x27, 0xc7, 0x2a, 0xe6,
+ 0x54, 0xc4, 0x0f, 0x0b, 0x3c, 0x8b, 0x0b, 0x88, 0xc1, 0x26, 0xd5, 0xa0, 0x7a, 0x91, 0x0d, 0xb1,
+ 0x4a, 0x5d, 0x97, 0x7e, 0xc8, 0xb0, 0x64, 0x14, 0xc6, 0x94, 0x61, 0xc8, 0xd0, 0xac, 0x27, 0x74,
+ 0x8b, 0xec, 0xa0, 0xba, 0x49, 0x85, 0x39, 0xed, 0x10, 0xf9, 0xfc, 0xc1, 0x00, 0x4b, 0x23, 0x66,
+ 0xb1, 0x53, 0x35, 0xc9, 0x12, 0x88, 0xc1, 0x25, 0x63, 0xa9, 0xb9, 0xd5, 0xd2, 0x6a, 0x29, 0x35,
+ 0x4f, 0x19, 0xba, 0xf4, 0xc0, 0x1e, 0xcf, 0xec, 0x9a, 0xb1, 0xd5, 0xd2, 0x6d, 0x61, 0xcc, 0x4b,
+ 0xc6, 0x21, 0x83, 0x12, 0x71, 0xda, 0x89, 0x18, 0x5d, 0xa0, 0xfa, 0x49, 0x51, 0xe7, 0x3e, 0x69,
+ 0x60, 0x69, 0x74, 0x92, 0x41, 0xaa, 0x49, 0xb5, 0x88, 0xd8, 0x9a, 0x42, 0x5c, 0x95, 0x9a, 0x4b,
+ 0xcd, 0xcd, 0xfa, 0x41, 0xb5, 0x93, 0x4c, 0xf7, 0xbf, 0x3a, 0x08, 0xb9, 0x4c, 0xa9, 0x83, 0x57,
+ 0xae, 0x21, 0x59, 0x6d, 0xd6, 0x2f, 0xb2, 0x20, 0xa3, 0x58, 0x42, 0x1f, 0xe7, 0xec, 0x45, 0x08,
+ 0xa0, 0x25, 0xc0, 0x23, 0x48, 0x63, 0x88, 0xed, 0xd2, 0xaf, 0x19, 0xd7, 0x90, 0x0e, 0x25, 0x74,
+ 0x72, 0x19, 0x9d, 0xe3, 0xff, 0x5e, 0xa0, 0x16, 0x59, 0x90, 0xd4, 0x35, 0x63, 0x97, 0x3e, 0x84,
+ 0x24, 0x34, 0x18, 0x95, 0x4f, 0x11, 0x8f, 0x17, 0x58, 0xaf, 0x06, 0x29, 0xe0, 0x71, 0xc8, 0x00,
+ 0x12, 0xa6, 0xd4, 0x35, 0xa9, 0x3a, 0xb6, 0x2c, 0x57, 0x5a, 0x24, 0xa3, 0x84, 0x0e, 0x74, 0xf2,
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+ 0xbc, 0x77, 0x36, 0x2a, 0x18, 0xe8, 0x88, 0xf0, 0xc6, 0x46, 0x17, 0xed, 0x7d, 0xbd, 0x7d, 0xe5,
+ 0xfe, 0x94, 0x3f, 0x85, 0xbb, 0xc4, 0xfd, 0xf4, 0x93, 0xd9, 0xae, 0xcc, 0x27, 0x19, 0xd8, 0x5d,
+ 0x23, 0xb9, 0x92, 0x9a, 0x96, 0x6b, 0x9b, 0x6d, 0x47, 0xa6, 0x6c, 0x2b, 0x39, 0x95, 0xba, 0x8b,
+ 0x2a, 0xf2, 0xe5, 0xec, 0x54, 0xf4, 0x6b, 0x83, 0x1e, 0x8a, 0x8e, 0x0c, 0x46, 0x8b, 0xb6, 0xa3,
+ 0x5d, 0x99, 0xc5, 0x28, 0x8c, 0x22, 0x6e, 0x25, 0x8b, 0x2c, 0x64, 0x26, 0x7d, 0xce, 0xb8, 0xa7,
+ 0x5e, 0x6b, 0x67, 0x1e, 0x51, 0xfd, 0x78, 0x60, 0x64, 0x22, 0x0e, 0x01, 0xed, 0x8d, 0x70, 0xc2,
+ 0xee, 0x11, 0xf3, 0x05, 0xfa, 0x0e, 0xc6, 0x08, 0xd8, 0x5f, 0xe9, 0xb8, 0x19, 0xc8, 0x25, 0xd0,
+ 0x41, 0x9c, 0xe4, 0xfe, 0x2e, 0x54, 0x82, 0x72, 0x93, 0x6d, 0x66, 0xca, 0xa9, 0xca, 0x65, 0xd8,
+ 0x46, 0x6b, 0xa2, 0x34, 0xeb, 0x0e, 0x68, 0x43, 0xee, 0x10, 0x57, 0x1b, 0x3e, 0x1a, 0x7e, 0x14,
+ 0x76, 0x6a, 0x01, 0x3d, 0x2e, 0x32, 0xe2, 0x1d, 0x2f, 0x31, 0x89, 0x4c, 0xb9, 0xed, 0x3a, 0x7c,
+ 0xbe, 0xcb, 0xd8, 0xe5, 0xa9, 0x04, 0xbb, 0x89, 0xeb, 0x14, 0xad, 0xcf, 0x7d, 0x4d, 0xab, 0xb5,
+ 0x76, 0x06, 0x54, 0xa7, 0xc8, 0xa7, 0x54, 0xa6, 0xca, 0xdf, 0x27, 0x1d, 0x9f, 0x0b, 0x37, 0x22,
+ 0x49, 0x43, 0xdf, 0x47, 0xe9, 0xa8, 0x1d, 0xed, 0x50, 0x8c, 0xc2, 0x97, 0x96, 0x5c, 0x85, 0x6a,
+ 0x76, 0x7b, 0xcd, 0x5a, 0x6b, 0x03, 0xc7, 0x45, 0x89, 0x5a, 0x39, 0xeb, 0x2e, 0x71, 0xb4, 0x6b,
+ 0x62, 0x89, 0x8e, 0xc1, 0x4b, 0x7a, 0xab, 0x83, 0x22, 0x5d, 0x89, 0xc7, 0xdc, 0x4d, 0x1c, 0xea,
+ 0xb0, 0x67, 0xd3, 0xee, 0x5a, 0x41, 0xaf, 0xa4, 0xec, 0x08, 0x4a, 0x2e, 0xfe, 0x4d, 0xf9, 0xe8,
+ 0xb4, 0x01, 0xf9, 0x09, 0xd6, 0x0f, 0x9a, 0x63, 0xe7, 0x7b, 0xe1, 0x35, 0x8f, 0x46, 0xe3, 0x6d,
+ 0x2f, 0x46, 0x65, 0x74, 0x24, 0xeb, 0x47, 0x51, 0x9a, 0x73, 0x3b, 0x88, 0xd1, 0x05, 0xcf, 0x70,
+ 0xad, 0x8f, 0x78, 0x43, 0xb4, 0xab, 0xd0, 0x45, 0x3e, 0xd2, 0xe7, 0x1c, 0x72, 0x77, 0x08, 0xe8,
+ 0xa6, 0x5b, 0xf5, 0xce, 0xf0, 0x4e, 0xb2, 0x7f, 0xb0, 0xac, 0x17, 0xde, 0xc3, 0x5e, 0x09, 0xe8,
+ 0x29, 0x68, 0x99, 0x83, 0xb7, 0xf4, 0xaf, 0x8f, 0xa5, 0xe2, 0xa1, 0xd3, 0x5d, 0x25, 0xd8, 0x9d,
+ 0x4d, 0x74, 0xd0, 0x17, 0xce, 0xcc, 0x47, 0x8e, 0xcb, 0x32, 0xad, 0x8c, 0xda, 0xe7, 0x5c, 0xac,
+ 0x3c, 0x96, 0x52, 0x5c, 0xf4, 0x56, 0x9b, 0x17, 0x53, 0x64, 0xa5, 0xde, 0x6a, 0x9f, 0xd3, 0xe7,
+ 0x1c, 0xae, 0x9e, 0x72, 0xc7, 0xc5, 0x0b, 0xb2, 0xc8, 0xf6, 0x9a, 0xd9, 0x2a, 0x3b, 0x93, 0x79,
+ 0x79, 0x6a, 0x87, 0x05, 0x44, 0x3e, 0x0f, 0x35, 0x7b, 0x6f, 0x52, 0x5f, 0x39, 0xd6, 0xb8, 0xd0,
+ 0x0d, 0x84, 0x1e, 0xde, 0xbd, 0x3a, 0x98, 0x76, 0xa2, 0x67, 0x1f, 0xeb, 0x1e, 0x27, 0x03, 0xb8,
+ 0xc3, 0x10, 0xfb, 0x81, 0x61, 0x3f, 0xb1, 0xa3, 0x53, 0x45, 0xdd, 0x7b, 0xa4, 0x33, 0xaa, 0x6a,
+ 0x47, 0x0e, 0x51, 0x2f, 0x50, 0x05, 0xa8, 0x27, 0x16, 0xa1, 0x77, 0x0e, 0xdd, 0x5b, 0xe9, 0x25,
+ 0xed, 0xaf, 0x66, 0x7f, 0x79, 0xbb, 0x5f, 0xdf, 0x88, 0x7c, 0x9f, 0xc6, 0x5a, 0x88, 0x09, 0xca,
+ 0x35, 0x79, 0x05, 0xfa, 0xfd, 0x34, 0xd6, 0xbb, 0x5a, 0xe6, 0xba, 0xb3, 0x07, 0xf7, 0xda, 0xa3,
+ 0xa6, 0x9b, 0xe4, 0x6b, 0x03, 0x57, 0x87, 0xc2, 0xb2, 0x81, 0x1f, 0x5c, 0xf3, 0xc5, 0xf3, 0xa0,
+ 0x17, 0x94, 0xf9, 0x67, 0x58, 0x15, 0x55, 0xf6, 0x8b, 0x14, 0xef, 0x4b, 0x8a, 0xfe, 0xf6, 0xb3,
+ 0x87, 0xae, 0x0a, 0xb6, 0xdf, 0x51, 0x6c, 0x63, 0x14, 0xd9, 0xcb, 0x78, 0xf9, 0x6c, 0xd5, 0xaa,
+ 0x01, 0x28, 0x52, 0x23, 0xfb, 0xe8, 0x29, 0xd8, 0xf9, 0xd7, 0x2a, 0x05, 0xdc, 0x68, 0xd3, 0x84,
+ 0xde, 0x19, 0x58, 0x88, 0x6c, 0xbc, 0xc2, 0x1e, 0x1c, 0x00, 0xee, 0x4e, 0x87, 0xb6, 0xd8, 0xdd,
+ 0x40, 0x63, 0x20, 0x18, 0x42, 0x4f, 0xd0, 0xc5, 0xd7, 0x97, 0xb2, 0x46, 0x25, 0xe1, 0x5e, 0xac,
+ 0x99, 0xfb, 0x89, 0xc2, 0x09, 0x74, 0x0e, 0x99, 0xc0, 0xe3, 0xe1, 0x84, 0x97, 0xce, 0x36, 0xc7,
+ 0x2a, 0xf9, 0x99, 0xd9, 0x7f, 0x4e, 0x66, 0xd8, 0x88, 0xcc, 0x47, 0x1a, 0x03, 0x66, 0xcd, 0xe0,
+ 0x38, 0xb8, 0xdb, 0x7d, 0x98, 0x8c, 0xbe, 0x34, 0xaa, 0x47, 0x12, 0x52, 0x11, 0x56, 0x56, 0x00,
+ 0x76, 0x0e, 0xb9, 0xd2, 0x35, 0xcb, 0x31, 0x94, 0x83, 0x2d, 0x19, 0xbb, 0x10, 0xc9, 0xba, 0x1e,
+ 0xea, 0x09, 0x52, 0xe7, 0xda, 0x21, 0xea, 0x34, 0x75, 0x2e, 0x5b, 0x3c, 0xd7, 0xfb, 0x75, 0x6b,
+ 0x27, 0xd4, 0x3a, 0x03, 0xbf, 0xcd, 0x3d, 0x9e, 0xe0, 0x73, 0xfd, 0xfa, 0x41, 0xde, 0x3f, 0x53,
+ 0xc8, 0xef, 0xb8, 0xd6, 0x2a, 0x7d, 0x4f, 0xee, 0x2a, 0xb3, 0xb9, 0x1c, 0x92, 0x53, 0x3b, 0x8a,
+ 0xff, 0xf0, 0x6c, 0x17, 0xaf, 0xc1, 0xd9, 0x6d, 0x59, 0x62, 0x96, 0x6d, 0x1a, 0xfa, 0xf3, 0xe9,
+ 0x67, 0xb2, 0x82, 0xcb, 0xd2, 0xff, 0x94, 0x06, 0x79, 0x7c, 0xd5, 0x95, 0x83, 0x4f, 0xc9, 0x08,
+ 0xf8, 0x86, 0xe8, 0x13, 0xb4, 0x47, 0x11, 0xa7, 0x77, 0xa8, 0x98, 0xd8, 0xb4, 0x64, 0xd3, 0xa2,
+ 0x61, 0xd3, 0x38, 0xb3, 0xf3, 0xdc, 0x41, 0x90, 0xde, 0x0b, 0x95, 0xcb, 0xf7, 0xce, 0x14, 0xf8,
+ 0x86, 0x4f, 0xff, 0x11, 0x26, 0xe5, 0xd8, 0xcd, 0x96, 0xff, 0x17, 0xd8, 0x7d, 0xcf, 0x6f, 0x5c,
+ 0xec, 0xa7, 0xa1, 0x48, 0x9d, 0x01, 0x00
+};
+
+fastimage_t bfin_logo = {
+		DEF_BFIN_LOGO_DATA,
+		DEF_BFIN_LOGO_WIDTH,
+		DEF_BFIN_LOGO_HEIGHT,
+		DEF_BFIN_LOGO_BPP,
+		DEF_BFIN_LOGO_PIXEL_SIZE,
+		DEF_BFIN_LOGO_SIZE
+};
diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h
new file mode 100644
index 000000000..ab1fea55c
--- /dev/null
+++ b/arch/blackfin/include/asm/bitops.h
@@ -0,0 +1,371 @@
+/*
+ * U-boot - bitops.h Routines for bit operations
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _BLACKFIN_BITOPS_H
+#define _BLACKFIN_BITOPS_H
+
+/*
+ * Copyright 1992, Linus Torvalds.
+ */
+
+#include <linux/config.h>
+#include <asm/byteorder.h>
+#include <asm/system.h>
+
+#ifdef __KERNEL__
+/*
+ * Function prototypes to keep gcc -Wall happy
+ */
+
+/*
+ * The __ functions are not atomic
+ */
+
+/*
+ * ffz = Find First Zero in word. Undefined if no zero exists,
+ * so code should check against ~0UL first..
+ */
+static __inline__ unsigned long ffz(unsigned long word)
+{
+	unsigned long result = 0;
+
+	while (word & 1) {
+		result++;
+		word >>= 1;
+	}
+	return result;
+}
+
+static __inline__ void set_bit(int nr, volatile void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	*a |= mask;
+	local_irq_restore(flags);
+}
+
+static __inline__ void __set_bit(int nr, volatile void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	*a |= mask;
+}
+#define PLATFORM__SET_BIT
+
+/*
+ * clear_bit() doesn't provide any barrier for the compiler.
+ */
+#define smp_mb__before_clear_bit()	barrier()
+#define smp_mb__after_clear_bit()	barrier()
+
+static __inline__ void clear_bit(int nr, volatile void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	*a &= ~mask;
+	local_irq_restore(flags);
+}
+
+static __inline__ void change_bit(int nr, volatile void *addr)
+{
+	int mask, flags;
+	unsigned long *ADDR = (unsigned long *)addr;
+
+	ADDR += nr >> 5;
+	mask = 1 << (nr & 31);
+	local_irq_save(flags);
+	*ADDR ^= mask;
+	local_irq_restore(flags);
+}
+
+static __inline__ void __change_bit(int nr, volatile void *addr)
+{
+	int mask;
+	unsigned long *ADDR = (unsigned long *)addr;
+
+	ADDR += nr >> 5;
+	mask = 1 << (nr & 31);
+	*ADDR ^= mask;
+}
+
+static __inline__ int test_and_set_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	retval = (mask & *a) != 0;
+	*a |= mask;
+	local_irq_restore(flags);
+
+	return retval;
+}
+
+static __inline__ int __test_and_set_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a |= mask;
+	return retval;
+}
+
+static __inline__ int test_and_clear_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	retval = (mask & *a) != 0;
+	*a &= ~mask;
+	local_irq_restore(flags);
+
+	return retval;
+}
+
+static __inline__ int __test_and_clear_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a &= ~mask;
+	return retval;
+}
+
+static __inline__ int test_and_change_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	retval = (mask & *a) != 0;
+	*a ^= mask;
+	local_irq_restore(flags);
+
+	return retval;
+}
+
+static __inline__ int __test_and_change_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a ^= mask;
+	return retval;
+}
+
+/*
+ * This routine doesn't need to be atomic.
+ */
+static __inline__ int __constant_test_bit(int nr, const volatile void *addr)
+{
+	return ((1UL << (nr & 31)) &
+		(((const volatile unsigned int *)addr)[nr >> 5])) != 0;
+}
+
+static __inline__ int __test_bit(int nr, volatile void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	return ((mask & *a) != 0);
+}
+
+#define	test_bit(nr,addr) \
+(__builtin_constant_p(nr) ? \
+ __constant_test_bit((nr),(addr)) : \
+ __test_bit((nr),(addr)))
+
+#define	find_first_zero_bit(addr, size) \
+	find_next_zero_bit((addr), (size), 0)
+
+static __inline__ int find_next_zero_bit(void *addr, int size, int offset)
+{
+	unsigned long *p = ((unsigned long *)addr) + (offset >> 5);
+	unsigned long result = offset & ~31UL;
+	unsigned long tmp;
+
+	if (offset >= size)
+		return size;
+	size -= result;
+	offset &= 31UL;
+	if (offset) {
+		tmp = *(p++);
+		tmp |= ~0UL >> (32 - offset);
+		if (size < 32)
+			goto found_first;
+		if (~tmp)
+			goto found_middle;
+		size -= 32;
+		result += 32;
+	}
+	while (size & ~31UL) {
+		if (~(tmp = *(p++)))
+			goto found_middle;
+		result += 32;
+		size -= 32;
+	}
+	if (!size)
+		return result;
+	tmp = *p;
+
+      found_first:
+	tmp |= ~0UL >> size;
+      found_middle:
+	return result + ffz(tmp);
+}
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x)	generic_hweight32(x)
+#define hweight16(x)	generic_hweight16(x)
+#define hweight8(x)	generic_hweight8(x)
+
+static __inline__ int ext2_set_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	unsigned long flags;
+	volatile unsigned char *ADDR = (unsigned char *)addr;
+
+	ADDR += nr >> 3;
+	mask = 1 << (nr & 0x07);
+	local_irq_save(flags);
+	retval = (mask & *ADDR) != 0;
+	*ADDR |= mask;
+	local_irq_restore(flags);
+	return retval;
+}
+
+static __inline__ int ext2_clear_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	unsigned long flags;
+	volatile unsigned char *ADDR = (unsigned char *)addr;
+
+	ADDR += nr >> 3;
+	mask = 1 << (nr & 0x07);
+	local_irq_save(flags);
+	retval = (mask & *ADDR) != 0;
+	*ADDR &= ~mask;
+	local_irq_restore(flags);
+	return retval;
+}
+
+static __inline__ int ext2_test_bit(int nr, const volatile void *addr)
+{
+	int mask;
+	const volatile unsigned char *ADDR = (const unsigned char *)addr;
+
+	ADDR += nr >> 3;
+	mask = 1 << (nr & 0x07);
+	return ((mask & *ADDR) != 0);
+}
+
+#define ext2_find_first_zero_bit(addr, size) \
+	ext2_find_next_zero_bit((addr), (size), 0)
+
+static __inline__ unsigned long ext2_find_next_zero_bit(void *addr,
+							unsigned long size,
+							unsigned long offset)
+{
+	unsigned long *p = ((unsigned long *)addr) + (offset >> 5);
+	unsigned long result = offset & ~31UL;
+	unsigned long tmp;
+
+	if (offset >= size)
+		return size;
+	size -= result;
+	offset &= 31UL;
+	if (offset) {
+		tmp = *(p++);
+		tmp |= ~0UL >> (32 - offset);
+		if (size < 32)
+			goto found_first;
+		if (~tmp)
+			goto found_middle;
+		size -= 32;
+		result += 32;
+	}
+	while (size & ~31UL) {
+		if (~(tmp = *(p++)))
+			goto found_middle;
+		result += 32;
+		size -= 32;
+	}
+	if (!size)
+		return result;
+	tmp = *p;
+
+      found_first:
+	tmp |= ~0UL >> size;
+      found_middle:
+	return result + ffz(tmp);
+}
+
+/* Bitmap functions for the minix filesystem. */
+#define minix_test_and_set_bit(nr,addr)		test_and_set_bit(nr,addr)
+#define minix_set_bit(nr,addr)			set_bit(nr,addr)
+#define minix_test_and_clear_bit(nr,addr)	test_and_clear_bit(nr,addr)
+#define minix_test_bit(nr,addr)			test_bit(nr,addr)
+#define minix_find_first_zero_bit(addr,size)	find_first_zero_bit(addr,size)
+
+#endif
+
+#endif
diff --git a/arch/blackfin/include/asm/blackfin.h b/arch/blackfin/include/asm/blackfin.h
new file mode 100644
index 000000000..204d02b5f
--- /dev/null
+++ b/arch/blackfin/include/asm/blackfin.h
@@ -0,0 +1,15 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by toolchain/trunk/proc-defs/sh/create-arch-headers.sh
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __MACH_GLOB_BLACKFIN__
+#define __MACH_GLOB_BLACKFIN__
+
+#include "blackfin_def.h"
+#ifndef __ASSEMBLY__
+#include "blackfin_cdef.h"
+#endif
+#include "blackfin_local.h"
+
+#endif /* __MACH_GLOB_BLACKFIN__ */
diff --git a/arch/blackfin/include/asm/blackfin_cdef.h b/arch/blackfin/include/asm/blackfin_cdef.h
new file mode 100644
index 000000000..aa03f2ce4
--- /dev/null
+++ b/arch/blackfin/include/asm/blackfin_cdef.h
@@ -0,0 +1,67 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by toolchain/trunk/proc-defs/sh/create-arch-headers.sh
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __MACH_CDEF_BLACKFIN__
+#define __MACH_CDEF_BLACKFIN__
+
+#ifdef __ADSPBF522__
+# include "mach-bf527/BF522_cdef.h"
+#endif
+#ifdef __ADSPBF523__
+# include "mach-bf527/BF523_cdef.h"
+#endif
+#ifdef __ADSPBF524__
+# include "mach-bf527/BF524_cdef.h"
+#endif
+#ifdef __ADSPBF525__
+# include "mach-bf527/BF525_cdef.h"
+#endif
+#ifdef __ADSPBF526__
+# include "mach-bf527/BF526_cdef.h"
+#endif
+#ifdef __ADSPBF527__
+# include "mach-bf527/BF527_cdef.h"
+#endif
+#ifdef __ADSPBF531__
+# include "mach-bf533/BF531_cdef.h"
+#endif
+#ifdef __ADSPBF532__
+# include "mach-bf533/BF532_cdef.h"
+#endif
+#ifdef __ADSPBF533__
+# include "mach-bf533/BF533_cdef.h"
+#endif
+#ifdef __ADSPBF534__
+# include "mach-bf537/BF534_cdef.h"
+#endif
+#ifdef __ADSPBF536__
+# include "mach-bf537/BF536_cdef.h"
+#endif
+#ifdef __ADSPBF537__
+# include "mach-bf537/BF537_cdef.h"
+#endif
+#ifdef __ADSPBF541__
+# include "mach-bf548/BF541_cdef.h"
+#endif
+#ifdef __ADSPBF542__
+# include "mach-bf548/BF542_cdef.h"
+#endif
+#ifdef __ADSPBF544__
+# include "mach-bf548/BF544_cdef.h"
+#endif
+#ifdef __ADSPBF547__
+# include "mach-bf548/BF547_cdef.h"
+#endif
+#ifdef __ADSPBF548__
+# include "mach-bf548/BF548_cdef.h"
+#endif
+#ifdef __ADSPBF549__
+# include "mach-bf548/BF549_cdef.h"
+#endif
+#ifdef __ADSPBF561__
+# include "mach-bf561/BF561_cdef.h"
+#endif
+
+#endif /* __MACH_CDEF_BLACKFIN__ */
diff --git a/arch/blackfin/include/asm/blackfin_def.h b/arch/blackfin/include/asm/blackfin_def.h
new file mode 100644
index 000000000..18372f6a8
--- /dev/null
+++ b/arch/blackfin/include/asm/blackfin_def.h
@@ -0,0 +1,105 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by toolchain/trunk/proc-defs/sh/create-arch-headers.sh
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __MACH_DEF_BLACKFIN__
+#define __MACH_DEF_BLACKFIN__
+
+#ifdef __ADSPBF522__
+# include "mach-bf527/BF522_def.h"
+# include "mach-bf527/anomaly.h"
+# include "mach-bf527/def_local.h"
+#endif
+#ifdef __ADSPBF523__
+# include "mach-bf527/BF523_def.h"
+# include "mach-bf527/anomaly.h"
+# include "mach-bf527/def_local.h"
+#endif
+#ifdef __ADSPBF524__
+# include "mach-bf527/BF524_def.h"
+# include "mach-bf527/anomaly.h"
+# include "mach-bf527/def_local.h"
+#endif
+#ifdef __ADSPBF525__
+# include "mach-bf527/BF525_def.h"
+# include "mach-bf527/anomaly.h"
+# include "mach-bf527/def_local.h"
+#endif
+#ifdef __ADSPBF526__
+# include "mach-bf527/BF526_def.h"
+# include "mach-bf527/anomaly.h"
+# include "mach-bf527/def_local.h"
+#endif
+#ifdef __ADSPBF527__
+# include "mach-bf527/BF527_def.h"
+# include "mach-bf527/anomaly.h"
+# include "mach-bf527/def_local.h"
+#endif
+#ifdef __ADSPBF531__
+# include "mach-bf533/BF531_def.h"
+# include "mach-bf533/anomaly.h"
+# include "mach-bf533/def_local.h"
+#endif
+#ifdef __ADSPBF532__
+# include "mach-bf533/BF532_def.h"
+# include "mach-bf533/anomaly.h"
+# include "mach-bf533/def_local.h"
+#endif
+#ifdef __ADSPBF533__
+# include "mach-bf533/BF533_def.h"
+# include "mach-bf533/anomaly.h"
+# include "mach-bf533/def_local.h"
+#endif
+#ifdef __ADSPBF534__
+# include "mach-bf537/BF534_def.h"
+# include "mach-bf537/anomaly.h"
+# include "mach-bf537/def_local.h"
+#endif
+#ifdef __ADSPBF536__
+# include "mach-bf537/BF536_def.h"
+# include "mach-bf537/anomaly.h"
+# include "mach-bf537/def_local.h"
+#endif
+#ifdef __ADSPBF537__
+# include "mach-bf537/BF537_def.h"
+# include "mach-bf537/anomaly.h"
+# include "mach-bf537/def_local.h"
+#endif
+#ifdef __ADSPBF541__
+# include "mach-bf548/BF541_def.h"
+# include "mach-bf548/anomaly.h"
+# include "mach-bf548/def_local.h"
+#endif
+#ifdef __ADSPBF542__
+# include "mach-bf548/BF542_def.h"
+# include "mach-bf548/anomaly.h"
+# include "mach-bf548/def_local.h"
+#endif
+#ifdef __ADSPBF544__
+# include "mach-bf548/BF544_def.h"
+# include "mach-bf548/anomaly.h"
+# include "mach-bf548/def_local.h"
+#endif
+#ifdef __ADSPBF547__
+# include "mach-bf548/BF547_def.h"
+# include "mach-bf548/anomaly.h"
+# include "mach-bf548/def_local.h"
+#endif
+#ifdef __ADSPBF548__
+# include "mach-bf548/BF548_def.h"
+# include "mach-bf548/anomaly.h"
+# include "mach-bf548/def_local.h"
+#endif
+#ifdef __ADSPBF549__
+# include "mach-bf548/BF549_def.h"
+# include "mach-bf548/anomaly.h"
+# include "mach-bf548/def_local.h"
+#endif
+#ifdef __ADSPBF561__
+# include "mach-bf561/BF561_def.h"
+# include "mach-bf561/anomaly.h"
+# include "mach-bf561/def_local.h"
+#endif
+
+#endif /* __MACH_DEF_BLACKFIN__ */
diff --git a/arch/blackfin/include/asm/blackfin_local.h b/arch/blackfin/include/asm/blackfin_local.h
new file mode 100644
index 000000000..3fd34b33f
--- /dev/null
+++ b/arch/blackfin/include/asm/blackfin_local.h
@@ -0,0 +1,220 @@
+/*
+ * U-boot - blackfin_local.h
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __BLACKFIN_LOCAL_H__
+#define __BLACKFIN_LOCAL_H__
+
+#include <asm/mem_map.h>
+
+#define LO(con32) ((con32) & 0xFFFF)
+#define lo(con32) ((con32) & 0xFFFF)
+#define HI(con32) (((con32) >> 16) & 0xFFFF)
+#define hi(con32) (((con32) >> 16) & 0xFFFF)
+
+#define OFFSET_(x) (x & 0x0000FFFF)
+#define MK_BMSK_(x) (1 << x)
+
+/* Ideally this should be USEC not MSEC, but the USEC multiplication
+ * likes to overflow 32bit quantities which is all our assembler
+ * currently supports ;(
+ */
+#define USEC_PER_MSEC 1000
+#define MSEC_PER_SEC 1000
+#define BFIN_SCLK (100000000)
+#define SCLK_TO_MSEC(sclk) ((MSEC_PER_SEC * ((sclk) / USEC_PER_MSEC)) / (BFIN_SCLK / USEC_PER_MSEC))
+#define MSEC_TO_SCLK(msec) ((((BFIN_SCLK / USEC_PER_MSEC) * (msec)) / MSEC_PER_SEC) * USEC_PER_MSEC)
+
+#define L1_CACHE_SHIFT 5
+#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
+
+#include <asm/linkage.h>
+
+#ifndef __ASSEMBLY__
+# ifdef SHARED_RESOURCES
+#  include <asm/shared_resources.h>
+# endif
+
+# include <linux/types.h>
+
+extern u_long get_vco(void);
+extern u_long get_cclk(void);
+extern u_long get_sclk(void);
+
+# define bfin_revid() (bfin_read_CHIPID() >> 28)
+
+extern bool bfin_os_log_check(void);
+extern void bfin_os_log_dump(void);
+
+extern void blackfin_icache_flush_range(const void *, const void *);
+extern void blackfin_dcache_flush_range(const void *, const void *);
+extern void blackfin_icache_dcache_flush_range(const void *, const void *);
+extern void blackfin_dcache_flush_invalidate_range(const void *, const void *);
+
+/* Use DMA to move data from on chip to external memory.  The L1 instruction
+ * regions can only be accessed via DMA, so if the address in question is in
+ * that region, make sure we attempt to DMA indirectly.
+ */
+# define addr_bfin_on_chip_mem(addr) (((unsigned long)(addr) & 0xFFF00000) == 0xFFA00000)
+
+# include <asm/system.h>
+
+#if ANOMALY_05000198
+# define NOP_PAD_ANOMALY_05000198 "nop;"
+#else
+# define NOP_PAD_ANOMALY_05000198
+#endif
+
+#define bfin_read8(addr) ({ \
+	uint8_t __v; \
+	__asm__ __volatile__( \
+		NOP_PAD_ANOMALY_05000198 \
+		"%0 = b[%1] (z);" \
+		: "=d" (__v) \
+		: "a" (addr) \
+	); \
+	__v; })
+
+#define bfin_read16(addr) ({ \
+	uint16_t __v; \
+	__asm__ __volatile__( \
+		NOP_PAD_ANOMALY_05000198 \
+		"%0 = w[%1] (z);" \
+		: "=d" (__v) \
+		: "a" (addr) \
+	); \
+	__v; })
+
+#define bfin_read32(addr) ({ \
+	uint32_t __v; \
+	__asm__ __volatile__( \
+		NOP_PAD_ANOMALY_05000198 \
+		"%0 = [%1];" \
+		: "=d" (__v) \
+		: "a" (addr) \
+	); \
+	__v; })
+
+#define bfin_readPTR(addr) bfin_read32(addr)
+
+#define bfin_write8(addr, val) \
+	__asm__ __volatile__( \
+		NOP_PAD_ANOMALY_05000198 \
+		"b[%0] = %1;" \
+		: \
+		: "a" (addr), "d" (val) \
+		: "memory" \
+	)
+
+#define bfin_write16(addr, val) \
+	__asm__ __volatile__( \
+		NOP_PAD_ANOMALY_05000198 \
+		"w[%0] = %1;" \
+		: \
+		: "a" (addr), "d" (val) \
+		: "memory" \
+	)
+
+#define bfin_write32(addr, val) \
+	__asm__ __volatile__( \
+		NOP_PAD_ANOMALY_05000198 \
+		"[%0] = %1;" \
+		: \
+		: "a" (addr), "d" (val) \
+		: "memory" \
+	)
+
+#define bfin_writePTR(addr, val) bfin_write32(addr, val)
+
+/* SSYNC implementation for C file */
+static inline void SSYNC(void)
+{
+	int _tmp;
+	if (ANOMALY_05000312)
+		__asm__ __volatile__(
+			"cli %0;"
+			"nop;"
+			"nop;"
+			"ssync;"
+			"sti %0;"
+			: "=d" (_tmp)
+		);
+	else if (ANOMALY_05000244)
+		__asm__ __volatile__(
+			"nop;"
+			"nop;"
+			"nop;"
+			"ssync;"
+		);
+	else
+		__asm__ __volatile__("ssync;");
+}
+
+/* CSYNC implementation for C file */
+static inline void CSYNC(void)
+{
+	int _tmp;
+	if (ANOMALY_05000312)
+		__asm__ __volatile__(
+			"cli %0;"
+			"nop;"
+			"nop;"
+			"csync;"
+			"sti %0;"
+			: "=d" (_tmp)
+		);
+	else if (ANOMALY_05000244)
+		__asm__ __volatile__(
+			"nop;"
+			"nop;"
+			"nop;"
+			"csync;"
+		);
+	else
+		__asm__ __volatile__("csync;");
+}
+
+#else  /* __ASSEMBLY__ */
+
+/* SSYNC & CSYNC implementations for assembly files */
+
+#define ssync(x) SSYNC(x)
+#define csync(x) CSYNC(x)
+
+#if ANOMALY_05000312
+#define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch;
+#define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch;
+
+#elif ANOMALY_05000244
+#define SSYNC(scratch) nop; nop; nop; SSYNC;
+#define CSYNC(scratch) nop; nop; nop; CSYNC;
+
+#else
+#define SSYNC(scratch) SSYNC;
+#define CSYNC(scratch) CSYNC;
+
+#endif /* ANOMALY_05000312 & ANOMALY_05000244 handling */
+
+#endif /* __ASSEMBLY__ */
+
+#endif
diff --git a/arch/blackfin/include/asm/byteorder.h b/arch/blackfin/include/asm/byteorder.h
new file mode 100644
index 000000000..a1a52a5c1
--- /dev/null
+++ b/arch/blackfin/include/asm/byteorder.h
@@ -0,0 +1,40 @@
+/*
+ * U-boot -  byteorder.h
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _BLACKFIN_BYTEORDER_H
+#define _BLACKFIN_BYTEORDER_H
+
+#include <asm/types.h>
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#include <linux/byteorder/little_endian.h>
+
+#endif
diff --git a/arch/blackfin/include/asm/config-pre.h b/arch/blackfin/include/asm/config-pre.h
new file mode 100644
index 000000000..4531519d9
--- /dev/null
+++ b/arch/blackfin/include/asm/config-pre.h
@@ -0,0 +1,80 @@
+/*
+ * config-pre.h - common defines for Blackfin boards in config.h
+ *
+ * Copyright (c) 2007-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __ASM_BLACKFIN_CONFIG_PRE_H__
+#define __ASM_BLACKFIN_CONFIG_PRE_H__
+
+/* Misc helper functions */
+#define XMK_STR(x) #x
+#define MK_STR(x) XMK_STR(x)
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+/* Bootmode defines -- your config needs to select this via CONFIG_BFIN_BOOT_MODE.
+ * Depending on your cpu, some of these may not be valid, check your HRM.
+ * The actual values here are meaningless as long as they're unique.
+ */
+#define BFIN_BOOT_BYPASS      1       /* bypass bootrom */
+#define BFIN_BOOT_PARA        2       /* boot ldr out of parallel flash */
+#define BFIN_BOOT_SPI_MASTER  3       /* boot ldr out of serial flash */
+#define BFIN_BOOT_SPI_SLAVE   4       /* boot ldr as spi slave */
+#define BFIN_BOOT_TWI_MASTER  5       /* boot ldr over twi device */
+#define BFIN_BOOT_TWI_SLAVE   6       /* boot ldr over twi slave */
+#define BFIN_BOOT_UART        7       /* boot ldr over uart */
+#define BFIN_BOOT_IDLE        8       /* do nothing, just idle */
+#define BFIN_BOOT_FIFO        9       /* boot ldr out of FIFO */
+#define BFIN_BOOT_MEM         10      /* boot ldr out of memory (warmboot) */
+#define BFIN_BOOT_16HOST_DMA  11      /* boot ldr from 16-bit host dma */
+#define BFIN_BOOT_8HOST_DMA   12      /* boot ldr from 8-bit host dma */
+#define BFIN_BOOT_NAND        13      /* boot ldr from nand flash */
+
+#ifndef __ASSEMBLY__
+static inline const char *get_bfin_boot_mode(int bfin_boot)
+{
+	switch (bfin_boot) {
+	case BFIN_BOOT_BYPASS:     return "bypass";
+	case BFIN_BOOT_PARA:       return "parallel flash";
+	case BFIN_BOOT_SPI_MASTER: return "spi flash";
+	case BFIN_BOOT_SPI_SLAVE:  return "spi slave";
+	case BFIN_BOOT_TWI_MASTER: return "i2c flash";
+	case BFIN_BOOT_TWI_SLAVE:  return "i2c slave";
+	case BFIN_BOOT_UART:       return "uart";
+	case BFIN_BOOT_IDLE:       return "idle";
+	case BFIN_BOOT_FIFO:       return "fifo";
+	case BFIN_BOOT_MEM:        return "memory";
+	case BFIN_BOOT_16HOST_DMA: return "16bit dma";
+	case BFIN_BOOT_8HOST_DMA:  return "8bit dma";
+	case BFIN_BOOT_NAND:       return "nand flash";
+	default:                   return "INVALID";
+	}
+}
+#endif
+
+/* Most bootroms allow for EVT1 redirection */
+#if ((defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__)) \
+     && __SILICON_REVISION__ < 3) || defined(__ADSPBF561__)
+# undef CONFIG_BFIN_BOOTROM_USES_EVT1
+#else
+# define CONFIG_BFIN_BOOTROM_USES_EVT1
+#endif
+
+/* Define the default SPI CS used when booting out of SPI */
+#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \
+    defined(__ADSPBF538__) || defined(__ADSPBF539__) || defined(__ADSPBF561__) || \
+    defined(__ADSPBF51x__)
+# define BFIN_BOOT_SPI_SSEL 2
+#else
+# define BFIN_BOOT_SPI_SSEL 1
+#endif
+
+/* There is no Blackfin/NetBSD port */
+#undef CONFIG_BOOTM_NETBSD
+
+/* We rarely use interrupts, so favor throughput over latency */
+#define CONFIG_BFIN_INS_LOWOVERHEAD
+
+#endif
diff --git a/arch/blackfin/include/asm/config.h b/arch/blackfin/include/asm/config.h
new file mode 100644
index 000000000..745568505
--- /dev/null
+++ b/arch/blackfin/include/asm/config.h
@@ -0,0 +1,169 @@
+/*
+ * config.h - setup common defines for Blackfin boards based on config.h
+ *
+ * Copyright (c) 2007-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __ASM_BLACKFIN_CONFIG_POST_H__
+#define __ASM_BLACKFIN_CONFIG_POST_H__
+
+/* Sanity check CONFIG_BFIN_CPU */
+#ifndef CONFIG_BFIN_CPU
+# error CONFIG_BFIN_CPU: your board config needs to define this
+#endif
+
+#ifndef CONFIG_BFIN_SCRATCH_REG
+# define CONFIG_BFIN_SCRATCH_REG retn
+#endif
+
+/* Relocation to SDRAM works on all Blackfin boards */
+#define CONFIG_RELOC_FIXUP_WORKS
+
+/* Make sure the structure is properly aligned */
+#if ((CONFIG_SYS_GBL_DATA_ADDR & -4) != CONFIG_SYS_GBL_DATA_ADDR)
+# error CONFIG_SYS_GBL_DATA_ADDR: must be 4 byte aligned
+#endif
+
+/* Set default CONFIG_VCO_HZ if need be */
+#if !defined(CONFIG_VCO_HZ)
+# if (CONFIG_CLKIN_HALF == 0)
+#  define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
+# else
+#  define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / 2)
+# endif
+#endif
+
+/* Set default CONFIG_CCLK_HZ if need be */
+#if !defined(CONFIG_CCLK_HZ)
+# if (CONFIG_PLL_BYPASS == 0)
+#  define CONFIG_CCLK_HZ (CONFIG_VCO_HZ / CONFIG_CCLK_DIV)
+# else
+#  define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
+# endif
+#endif
+
+/* Set default CONFIG_SCLK_HZ if need be */
+#if !defined(CONFIG_SCLK_HZ)
+# if (CONFIG_PLL_BYPASS == 0)
+#  define CONFIG_SCLK_HZ (CONFIG_VCO_HZ / CONFIG_SCLK_DIV)
+# else
+#  define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
+# endif
+#endif
+
+/* Since we use these to program PLL registers directly,
+ * make sure the values are sane and won't screw us up.
+ */
+#if (CONFIG_VCO_MULT & 0x3F) != CONFIG_VCO_MULT
+# error CONFIG_VCO_MULT: Invalid value: must fit in 6 bits (0 - 63)
+#endif
+#if (CONFIG_CLKIN_HALF & 0x1) != CONFIG_CLKIN_HALF
+# error CONFIG_CLKIN_HALF: Invalid value: must be 0 or 1
+#endif
+#if (CONFIG_PLL_BYPASS & 0x1) != CONFIG_PLL_BYPASS
+# error CONFIG_PLL_BYPASS: Invalid value: must be 0 or 1
+#endif
+
+/* If we are using KGDB, make sure we defer exceptions */
+#ifdef CONFIG_CMD_KGDB
+# define CONFIG_EXCEPTION_DEFER	1
+#endif
+
+/* Using L1 scratch pad makes sense for everyone by default. */
+#ifndef CONFIG_LINUX_CMDLINE_ADDR
+# define CONFIG_LINUX_CMDLINE_ADDR L1_SRAM_SCRATCH
+#endif
+#ifndef CONFIG_LINUX_CMDLINE_SIZE
+# define CONFIG_LINUX_CMDLINE_SIZE L1_SRAM_SCRATCH_SIZE
+#endif
+
+/* Set default SPI flash CS to the one we boot from */
+#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_SPI_CS)
+# define CONFIG_ENV_SPI_CS BFIN_BOOT_SPI_SSEL
+#endif
+
+/* We need envcrc to embed the env into LDRs */
+#ifdef CONFIG_ENV_IS_EMBEDDED_IN_LDR
+# define CONFIG_BUILD_ENVCRC
+#endif
+
+/* Default/common Blackfin memory layout */
+#ifndef CONFIG_SYS_SDRAM_BASE
+# define CONFIG_SYS_SDRAM_BASE 0
+#endif
+#ifndef CONFIG_SYS_MAX_RAM_SIZE
+# define CONFIG_SYS_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 * 1024)
+#endif
+#ifndef CONFIG_SYS_MONITOR_BASE
+# if CONFIG_SYS_MAX_RAM_SIZE
+#  define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN)
+# else
+#  define CONFIG_SYS_MONITOR_BASE 0
+# endif
+#endif
+#ifndef CONFIG_SYS_MALLOC_BASE
+# define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
+#endif
+#ifndef CONFIG_SYS_GBL_DATA_SIZE
+# define CONFIG_SYS_GBL_DATA_SIZE (128)
+#endif
+#ifndef CONFIG_SYS_GBL_DATA_ADDR
+# define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
+#endif
+#ifndef CONFIG_STACKBASE
+# define CONFIG_STACKBASE (CONFIG_SYS_GBL_DATA_ADDR - 4)
+#endif
+#ifndef CONFIG_SYS_MEMTEST_START
+# define CONFIG_SYS_MEMTEST_START 0
+#endif
+#ifndef CONFIG_SYS_MEMTEST_END
+# define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 8192 + 4)
+#endif
+
+/* Check to make sure everything fits in external RAM */
+#if CONFIG_SYS_MAX_RAM_SIZE && \
+    ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) > CONFIG_SYS_MAX_RAM_SIZE)
+# error Memory Map does not fit into configuration
+#endif
+
+/* Default/common Blackfin environment settings */
+#ifndef CONFIG_LOADADDR
+# define CONFIG_LOADADDR 0x1000000
+#endif
+#ifndef CONFIG_SYS_LOAD_ADDR
+# define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#endif
+#ifndef CONFIG_SYS_BOOTM_LEN
+# define CONFIG_SYS_BOOTM_LEN 0x4000000
+#endif
+#ifndef CONFIG_SYS_PROMPT
+# define CONFIG_SYS_PROMPT "bfin> "
+#endif
+#ifndef CONFIG_SYS_CBSIZE
+# define CONFIG_SYS_CBSIZE 1024
+#elif defined(CONFIG_CMD_KGDB) && CONFIG_SYS_CBSIZE < 1024
+# error "kgdb needs cbsize to be >= 1024"
+#endif
+#ifndef CONFIG_SYS_BARGSIZE
+# define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#endif
+#ifndef CONFIG_SYS_PBSIZE
+# define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#endif
+#ifndef CONFIG_SYS_MAXARGS
+# define CONFIG_SYS_MAXARGS 16
+#endif
+#if defined(CONFIG_SYS_HZ)
+# if (CONFIG_SYS_HZ != 1000)
+#  warning "CONFIG_SYS_HZ must always be 1000"
+# endif
+# undef CONFIG_SYS_HZ
+#endif
+#define CONFIG_SYS_HZ 1000
+#ifndef CONFIG_SYS_BAUDRATE_TABLE
+# define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#endif
+
+#endif
diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h
new file mode 100644
index 000000000..cc21e93a1
--- /dev/null
+++ b/arch/blackfin/include/asm/cplb.h
@@ -0,0 +1,76 @@
+/*
+ * cplb.h - defines for managing CPLB tables
+ *
+ * Copyright (c) 2002-2007 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __ASM_BLACKFIN_CPLB_H__
+#define __ASM_BLACKFIN_CPLB_H__
+
+#include <asm/mach-common/bits/mpu.h>
+
+#define CPLB_ENABLE_ICACHE_P	0
+#define CPLB_ENABLE_DCACHE_P	1
+#define CPLB_ENABLE_DCACHE2_P	2
+#define CPLB_ENABLE_CPLBS_P	3	/* Deprecated! */
+#define CPLB_ENABLE_ICPLBS_P	4
+#define CPLB_ENABLE_DCPLBS_P	5
+
+#define CPLB_ENABLE_ICACHE	(1<<CPLB_ENABLE_ICACHE_P)
+#define CPLB_ENABLE_DCACHE	(1<<CPLB_ENABLE_DCACHE_P)
+#define CPLB_ENABLE_DCACHE2	(1<<CPLB_ENABLE_DCACHE2_P)
+#define CPLB_ENABLE_CPLBS	(1<<CPLB_ENABLE_CPLBS_P)
+#define CPLB_ENABLE_ICPLBS	(1<<CPLB_ENABLE_ICPLBS_P)
+#define CPLB_ENABLE_DCPLBS	(1<<CPLB_ENABLE_DCPLBS_P)
+#define CPLB_ENABLE_ANY_CPLBS	CPLB_ENABLE_CPLBS | \
+				CPLB_ENABLE_ICPLBS | \
+				CPLB_ENABLE_DCPLBS
+
+#define CPLB_RELOADED		0x0000
+#define CPLB_NO_UNLOCKED	0x0001
+#define CPLB_NO_ADDR_MATCH	0x0002
+#define CPLB_PROT_VIOL		0x0003
+
+#define CPLB_DEF_CACHE		CPLB_L1_CHBL | CPLB_WT
+#define CPLB_CACHE_ENABLED	CPLB_L1_CHBL | CPLB_DIRTY
+
+#define CPLB_ALL_ACCESS	CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
+
+#define CPLB_I_PAGE_MGMT	CPLB_LOCK | CPLB_VALID
+#define CPLB_D_PAGE_MGMT	CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
+#define CPLB_DNOCACHE		CPLB_ALL_ACCESS | CPLB_VALID
+#define CPLB_DDOCACHE		CPLB_DNOCACHE | CPLB_DEF_CACHE
+#define CPLB_INOCACHE		CPLB_USER_RD | CPLB_VALID
+#define CPLB_IDOCACHE		CPLB_INOCACHE | CPLB_L1_CHBL
+
+/* Data Attibutes*/
+
+#define SDRAM_IGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
+#define SDRAM_IKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define L1_IMEMORY              (PAGE_SIZE_1MB | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define SDRAM_INON_CHBL         (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
+
+#if ANOMALY_05000158
+# define ANOMALY_05000158_WORKAROUND 0x200
+#else
+# define ANOMALY_05000158_WORKAROUND 0
+#endif
+
+#ifdef CONFIG_DCACHE_WB		/*Write Back Policy */
+#define SDRAM_DGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#define SDRAM_DKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND)
+#define L1_DMEMORY              (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#define SDRAM_EBIU              (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+
+#else				/*Write Through */
+#define SDRAM_DGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#define SDRAM_DKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND)
+#define L1_DMEMORY              (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#define SDRAM_EBIU              (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#endif
+
+#endif				/* _CPLB_H */
diff --git a/arch/blackfin/include/asm/deferred.h b/arch/blackfin/include/asm/deferred.h
new file mode 100644
index 000000000..82ceda3e4
--- /dev/null
+++ b/arch/blackfin/include/asm/deferred.h
@@ -0,0 +1,20 @@
+/*
+ * U-boot - deferred register layout
+ *
+ * Copyright 2004-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _BLACKFIN_DEFER_H
+#define _BLACKFIN_DEFER_H
+
+#define deferred_regs_DCPLB_FAULT_ADDR	0
+#define deferred_regs_ICPLB_FAULT_ADDR	1
+#define deferred_regs_retx		2
+#define deferred_regs_SEQSTAT		3
+#define deferred_regs_SYSCFG		4
+#define deferred_regs_IMASK		5
+#define deferred_regs_last		6
+
+#endif /* _BLACKFIN_DEFER_H */
diff --git a/arch/blackfin/include/asm/delay.h b/arch/blackfin/include/asm/delay.h
new file mode 100644
index 000000000..3af6ad3e7
--- /dev/null
+++ b/arch/blackfin/include/asm/delay.h
@@ -0,0 +1,55 @@
+/*
+ * U-boot - delay.h Routines for introducing delays
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _BLACKFIN_DELAY_H
+#define _BLACKFIN_DELAY_H
+
+/*
+ * Changes made by akbar.hussain@Lineo.com, for BLACKFIN
+ * Copyright (C) 1994 Hamish Macdonald
+ *
+ * Delay routines, using a pre-computed "loops_per_second" value.
+ */
+
+extern __inline__ void __delay(unsigned long loops)
+{
+	__asm__ __volatile__("1:\t%0 += -1;\n\t"
+			     "cc = %0 == 0;\n\t"
+			     "if ! cc jump 1b;\n":"=d"(loops)
+			     :"0"(loops));
+}
+
+/*
+ * Use only for very small delays ( < 1 msec).  Should probably use a
+ * lookup table, really, as the multiplications take much too long with
+ * short delays.  This is a "reasonable" implementation, though (and the
+ * first constant multiplications gets optimized away if the delay is
+ * a constant)
+ */
+extern __inline__ void __udelay(unsigned long usecs)
+{
+	__delay(usecs);
+}
+
+#endif
diff --git a/arch/blackfin/include/asm/entry.h b/arch/blackfin/include/asm/entry.h
new file mode 100644
index 000000000..404144f4f
--- /dev/null
+++ b/arch/blackfin/include/asm/entry.h
@@ -0,0 +1,259 @@
+/*
+ * entry.h - routines for context saving and restoring (for interrupts/exceptions)
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __BLACKFIN_ENTRY_H
+#define __BLACKFIN_ENTRY_H
+#ifdef __ASSEMBLY__
+
+#define SAVE_ALL_INT		save_context_no_interrupts
+#define SAVE_ALL_SYS		save_context_no_interrupts
+#define SAVE_CONTEXT		save_context_with_interrupts
+
+#define RESTORE_ALL		restore_context_no_interrupts
+#define RESTORE_ALL_SYS		restore_context_no_interrupts
+#define RESTORE_CONTEXT		restore_context_with_interrupts
+
+/*
+ * Code to save processor context.
+ * We even save the register which are preserved by a function call
+ * - r4, r5, r6, r7, p3, p4, p5
+ */
+.macro save_context_with_interrupts
+	[--sp] = R0;
+	[--sp] = ( R7:0, P5:0 );
+	[--sp] = fp;
+	[--sp] = usp;
+
+	[--sp] = i0;
+	[--sp] = i1;
+	[--sp] = i2;
+	[--sp] = i3;
+
+	[--sp] = m0;
+	[--sp] = m1;
+	[--sp] = m2;
+	[--sp] = m3;
+
+	[--sp] = l0;
+	[--sp] = l1;
+	[--sp] = l2;
+	[--sp] = l3;
+
+	[--sp] = b0;
+	[--sp] = b1;
+	[--sp] = b2;
+	[--sp] = b3;
+	[--sp] = a0.x;
+	[--sp] = a0.w;
+	[--sp] = a1.x;
+	[--sp] = a1.w;
+
+	[--sp] = LC0;
+	[--sp] = LC1;
+	[--sp] = LT0;
+	[--sp] = LT1;
+	[--sp] = LB0;
+	[--sp] = LB1;
+
+	[--sp] = ASTAT;
+
+	[--sp] = r0;	/* Skip reserved */
+	[--sp] = RETS;
+	[--sp] = RETI;
+	[--sp] = RETX;
+	[--sp] = RETN;
+	[--sp] = RETE;
+	[--sp] = SEQSTAT;
+	[--sp] = SYSCFG;
+#ifdef CONFIG_CMD_KGDB
+	p0.l = lo(IPEND)
+	p0.h = hi(IPEND)
+	r0 = [p0];
+#endif
+	[--sp] = r0;	/* Skip IPEND as well. */
+.endm
+
+.macro save_context_no_interrupts
+	[--sp] = R0;
+	[--sp] = ( R7:0, P5:0 );
+	[--sp] = fp;
+	[--sp] = usp;
+
+	[--sp] = i0;
+	[--sp] = i1;
+	[--sp] = i2;
+	[--sp] = i3;
+
+	[--sp] = m0;
+	[--sp] = m1;
+	[--sp] = m2;
+	[--sp] = m3;
+
+	[--sp] = l0;
+	[--sp] = l1;
+	[--sp] = l2;
+	[--sp] = l3;
+
+	[--sp] = b0;
+	[--sp] = b1;
+	[--sp] = b2;
+	[--sp] = b3;
+	[--sp] = a0.x;
+	[--sp] = a0.w;
+	[--sp] = a1.x;
+	[--sp] = a1.w;
+
+	[--sp] = LC0;
+	[--sp] = LC1;
+	[--sp] = LT0;
+	[--sp] = LT1;
+	[--sp] = LB0;
+	[--sp] = LB1;
+
+	[--sp] = ASTAT;
+
+	[--sp] = r0;	/* Skip reserved */
+	[--sp] = RETS;
+	r0 = RETI;
+	[--sp] = r0;
+	[--sp] = RETX;
+	[--sp] = RETN;
+	[--sp] = RETE;
+	[--sp] = SEQSTAT;
+	[--sp] = SYSCFG;
+#ifdef CONFIG_CMD_KGDB
+	p0.l = lo(IPEND)
+	p0.h = hi(IPEND)
+	r0 = [p0];
+#endif
+	[--sp] = r0;	/* Skip IPEND as well. */
+.endm
+
+.macro restore_context_no_interrupts
+	sp += 4;
+	SYSCFG = [sp++];
+	SEQSTAT = [sp++];
+	RETE = [sp++];
+	RETN = [sp++];
+	RETX = [sp++];
+	r0 = [sp++];
+	RETI = r0;
+	RETS = [sp++];
+
+	sp += 4;
+
+	ASTAT = [sp++];
+
+	LB1 = [sp++];
+	LB0 = [sp++];
+	LT1 = [sp++];
+	LT0 = [sp++];
+	LC1 = [sp++];
+	LC0 = [sp++];
+
+	a1.w = [sp++];
+	a1.x = [sp++];
+	a0.w = [sp++];
+	a0.x = [sp++];
+	b3 = [sp++];
+	b2 = [sp++];
+	b1 = [sp++];
+	b0 = [sp++];
+
+	l3 = [sp++];
+	l2 = [sp++];
+	l1 = [sp++];
+	l0 = [sp++];
+
+	m3 = [sp++];
+	m2 = [sp++];
+	m1 = [sp++];
+	m0 = [sp++];
+
+	i3 = [sp++];
+	i2 = [sp++];
+	i1 = [sp++];
+	i0 = [sp++];
+
+	sp += 4;
+	fp = [sp++];
+
+	( R7 : 0, P5 : 0) = [ SP ++ ];
+	sp += 4;
+.endm
+
+.macro restore_context_with_interrupts
+	sp += 4;
+	SYSCFG = [sp++];
+	SEQSTAT = [sp++];
+	RETE = [sp++];
+	RETN = [sp++];
+	RETX = [sp++];
+	RETI = [sp++];
+	RETS = [sp++];
+
+	sp += 4;
+
+	ASTAT = [sp++];
+
+	LB1 = [sp++];
+	LB0 = [sp++];
+	LT1 = [sp++];
+	LT0 = [sp++];
+	LC1 = [sp++];
+	LC0 = [sp++];
+
+	a1.w = [sp++];
+	a1.x = [sp++];
+	a0.w = [sp++];
+	a0.x = [sp++];
+	b3 = [sp++];
+	b2 = [sp++];
+	b1 = [sp++];
+	b0 = [sp++];
+
+	l3 = [sp++];
+	l2 = [sp++];
+	l1 = [sp++];
+	l0 = [sp++];
+
+	m3 = [sp++];
+	m2 = [sp++];
+	m1 = [sp++];
+	m0 = [sp++];
+
+	i3 = [sp++];
+	i2 = [sp++];
+	i1 = [sp++];
+	i0 = [sp++];
+
+	sp += 4;
+	fp = [sp++];
+
+	( R7 : 0, P5 : 0) = [ SP ++ ];
+	sp += 4;
+.endm
+
+#endif
+#endif
diff --git a/arch/blackfin/include/asm/errno.h b/arch/blackfin/include/asm/errno.h
new file mode 100644
index 000000000..4c82b503d
--- /dev/null
+++ b/arch/blackfin/include/asm/errno.h
@@ -0,0 +1 @@
+#include <asm-generic/errno.h>
diff --git a/arch/blackfin/include/asm/global_data.h b/arch/blackfin/include/asm/global_data.h
new file mode 100644
index 000000000..c7099e6da
--- /dev/null
+++ b/arch/blackfin/include/asm/global_data.h
@@ -0,0 +1,72 @@
+/*
+ * U-boot - global_data.h Declarations for global data of u-boot
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef	__ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+
+#include <asm/u-boot.h>
+
+/*
+ * The following data structure is placed in some memory wich is
+ * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
+ * some locked parts of the data cache) to allow for a minimum set of
+ * global variables during system initialization (until we have set
+ * up the memory controller so that we can use RAM).
+ *
+ * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
+ */
+typedef struct global_data {
+	bd_t *bd;
+	unsigned long flags;
+	unsigned long board_type;
+	unsigned long baudrate;
+	unsigned long have_console;	/* serial_init() was called */
+	phys_size_t ram_size;		/* RAM size */
+	unsigned long env_addr;	/* Address  of Environment struct */
+	unsigned long env_valid;	/* Checksum of Environment valid? */
+#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
+	unsigned long post_log_word;	/* Record POST activities */
+	unsigned long post_init_f_time;	/* When post_init_f started */
+#endif
+
+	void **jt;		/* jump table */
+} gd_t;
+
+/*
+ * Global Data Flags
+ */
+#define	GD_FLG_RELOC	0x00001	/* Code was relocated to RAM     */
+#define	GD_FLG_DEVINIT	0x00002	/* Devices have been initialized */
+#define	GD_FLG_SILENT	0x00004	/* Silent mode                   */
+#define	GD_FLG_POSTFAIL	0x00008	/* Critical POST test failed     */
+#define	GD_FLG_POSTSTOP	0x00010	/* POST seqeunce aborted	 */
+#define	GD_FLG_LOGINIT	0x00020	/* Log Buf has been initialized	 */
+#define GD_FLG_DISABLE_CONSOLE	0x00040		/* Disable console (in & out)	 */
+
+#define DECLARE_GLOBAL_DATA_PTR     register gd_t * volatile gd asm ("P3")
+
+#endif
diff --git a/arch/blackfin/include/asm/io.h b/arch/blackfin/include/asm/io.h
new file mode 100644
index 000000000..75244a073
--- /dev/null
+++ b/arch/blackfin/include/asm/io.h
@@ -0,0 +1,227 @@
+/*
+ * U-boot - io.h IO routines
+ *
+ * Copyright 2004-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _BLACKFIN_IO_H
+#define _BLACKFIN_IO_H
+
+#ifdef __KERNEL__
+
+#include <asm/blackfin.h>
+
+#define __iomem
+
+static inline void sync(void)
+{
+	SSYNC();
+}
+
+/*
+ * Given a physical address and a length, return a virtual address
+ * that can be used to access the memory range with the caching
+ * properties specified by "flags".
+ */
+#define MAP_NOCACHE	(0)
+#define MAP_WRCOMBINE	(0)
+#define MAP_WRBACK	(0)
+#define MAP_WRTHROUGH	(0)
+
+static inline void *
+map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+{
+	return (void *)paddr;
+}
+
+/*
+ * Take down a mapping set up by map_physmem().
+ */
+static inline void unmap_physmem(void *vaddr, unsigned long flags)
+{
+
+}
+
+static inline phys_addr_t virt_to_phys(void * vaddr)
+{
+	return (phys_addr_t)(vaddr);
+}
+
+/*
+ * These are for ISA/PCI shared memory _only_ and should never be used
+ * on any other type of memory, including Zorro memory. They are meant to
+ * access the bus in the bus byte order which is little-endian!.
+ *
+ * readX/writeX() are used to access memory mapped devices. On some
+ * architectures the memory mapped IO stuff needs to be accessed
+ * differently. On the bfin architecture, we just read/write the
+ * memory location directly.
+ */
+#ifndef __ASSEMBLY__
+
+static inline unsigned char readb(const volatile void __iomem *addr)
+{
+	unsigned int val;
+	int tmp;
+
+	__asm__ __volatile__ (
+		"cli %1;"
+		"NOP; NOP; SSYNC;"
+		"%0 = b [%2] (z);"
+		"sti %1;"
+		: "=d"(val), "=d"(tmp)
+		: "a"(addr)
+	);
+
+	return (unsigned char) val;
+}
+
+static inline unsigned short readw(const volatile void __iomem *addr)
+{
+	unsigned int val;
+	int tmp;
+
+	__asm__ __volatile__ (
+		"cli %1;"
+		"NOP; NOP; SSYNC;"
+		"%0 = w [%2] (z);"
+		"sti %1;"
+		: "=d"(val), "=d"(tmp)
+		: "a"(addr)
+	);
+
+	return (unsigned short) val;
+}
+
+static inline unsigned int readl(const volatile void __iomem *addr)
+{
+	unsigned int val;
+	int tmp;
+
+	__asm__ __volatile__ (
+		"cli %1;"
+		"NOP; NOP; SSYNC;"
+		"%0 = [%2];"
+		"sti %1;"
+		: "=d"(val), "=d"(tmp)
+		: "a"(addr)
+	);
+
+	return val;
+}
+
+#endif /*  __ASSEMBLY__ */
+
+#define writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b))
+#define writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b))
+#define writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b))
+
+#define __raw_readb readb
+#define __raw_readw readw
+#define __raw_readl readl
+#define __raw_writeb writeb
+#define __raw_writew writew
+#define __raw_writel writel
+#define memset_io(a, b, c)	memset((void *)(a), (b), (c))
+#define memcpy_fromio(a, b, c)	memcpy((a), (void *)(b), (c))
+#define memcpy_toio(a, b, c)	memcpy((void *)(a), (b), (c))
+
+/* Convert "I/O port addresses" to actual addresses.  i.e. ugly casts. */
+#define __io(port) ((void *)(unsigned long)(port))
+
+#define inb(port)    readb(__io(port))
+#define inw(port)    readw(__io(port))
+#define inl(port)    readl(__io(port))
+#define outb(x, port) writeb(x, __io(port))
+#define outw(x, port) writew(x, __io(port))
+#define outl(x, port) writel(x, __io(port))
+
+#define inb_p(port)    inb(__io(port))
+#define inw_p(port)    inw(__io(port))
+#define inl_p(port)    inl(__io(port))
+#define outb_p(x, port) outb(x, __io(port))
+#define outw_p(x, port) outw(x, __io(port))
+#define outl_p(x, port) outl(x, __io(port))
+
+#define ioread8_rep(a, d, c)	readsb(a, d, c)
+#define ioread16_rep(a, d, c)	readsw(a, d, c)
+#define ioread32_rep(a, d, c)	readsl(a, d, c)
+#define iowrite8_rep(a, s, c)	writesb(a, s, c)
+#define iowrite16_rep(a, s, c)	writesw(a, s, c)
+#define iowrite32_rep(a, s, c)	writesl(a, s, c)
+
+#define ioread8(x)			readb(x)
+#define ioread16(x)			readw(x)
+#define ioread32(x)			readl(x)
+#define iowrite8(val, x)		writeb(val, x)
+#define iowrite16(val, x)		writew(val, x)
+#define iowrite32(val, x)		writel(val, x)
+
+#define mmiowb() wmb()
+
+#ifndef __ASSEMBLY__
+
+extern void outsb(unsigned long port, const void *addr, unsigned long count);
+extern void outsw(unsigned long port, const void *addr, unsigned long count);
+extern void outsw_8(unsigned long port, const void *addr, unsigned long count);
+extern void outsl(unsigned long port, const void *addr, unsigned long count);
+
+extern void insb(unsigned long port, void *addr, unsigned long count);
+extern void insw(unsigned long port, void *addr, unsigned long count);
+extern void insw_8(unsigned long port, void *addr, unsigned long count);
+extern void insl(unsigned long port, void *addr, unsigned long count);
+extern void insl_16(unsigned long port, void *addr, unsigned long count);
+
+static inline void readsl(const void __iomem *addr, void *buf, int len)
+{
+	insl((unsigned long)addr, buf, len);
+}
+
+static inline void readsw(const void __iomem *addr, void *buf, int len)
+{
+	insw((unsigned long)addr, buf, len);
+}
+
+static inline void readsb(const void __iomem *addr, void *buf, int len)
+{
+	insb((unsigned long)addr, buf, len);
+}
+
+static inline void writesl(const void __iomem *addr, const void *buf, int len)
+{
+	outsl((unsigned long)addr, buf, len);
+}
+
+static inline void writesw(const void __iomem *addr, const void *buf, int len)
+{
+	outsw((unsigned long)addr, buf, len);
+}
+
+static inline void writesb(const void __iomem *addr, const void *buf, int len)
+{
+	outsb((unsigned long)addr, buf, len);
+}
+
+#if defined(CONFIG_STAMP_CF) || defined(CONFIG_BFIN_IDE)
+/* This hack for CF/IDE needs to be addressed at some point */
+extern void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words);
+extern void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words);
+extern unsigned char cf_inb(volatile unsigned char *addr);
+extern void cf_outb(unsigned char val, volatile unsigned char *addr);
+#undef inb
+#undef outb
+#undef insw
+#undef outsw
+#define inb(addr) cf_inb((void *)(addr))
+#define outb(x, addr) cf_outb((unsigned char)(x), (void *)(addr))
+#define insw(port, addr, cnt) cf_insw((void *)(addr), (void *)(port), cnt)
+#define outsw(port, addr, cnt) cf_outsw((void *)(port), (void *)(addr), cnt)
+#endif
+
+#endif
+
+#endif				/* __KERNEL__ */
+
+#endif
diff --git a/arch/blackfin/include/asm/linkage.h b/arch/blackfin/include/asm/linkage.h
new file mode 100644
index 000000000..fbb497c7b
--- /dev/null
+++ b/arch/blackfin/include/asm/linkage.h
@@ -0,0 +1,74 @@
+/*
+ * U-boot - linkage.h
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _LINUX_LINKAGE_H
+#define _LINUX_LINKAGE_H
+
+#include <linux/config.h>
+
+#ifdef __cplusplus
+#define CPP_ASMLINKAGE		extern "C"
+#else
+#define CPP_ASMLINKAGE
+#endif
+
+#define asmlinkage CPP_ASMLINKAGE
+
+#define SYMBOL_NAME_STR(X)	#X
+#define SYMBOL_NAME(X)		X
+#ifdef __STDC__
+#define SYMBOL_NAME_LABEL(X)	X##:
+#else
+#define SYMBOL_NAME_LABEL(X)	X:
+#endif
+
+#define __ALIGN .align		4
+#define __ALIGN_STR		".align 4"
+
+#ifdef __ASSEMBLY__
+
+#define ALIGN			__ALIGN
+#define ALIGN_STR		__ALIGN_STR
+
+#define LENTRY(name) \
+	ALIGN; \
+	SYMBOL_NAME_LABEL(name)
+
+#define ENTRY(name) \
+	.globl SYMBOL_NAME(name); \
+	LENTRY(name)
+#endif
+
+#ifndef END
+#define END(name) \
+	.size name, .-name
+#endif
+
+#ifndef ENDPROC
+#define ENDPROC(name) \
+	.type name, @function; \
+	END(name)
+#endif
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h b/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h
new file mode 100644
index 000000000..f65b439c1
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h
@@ -0,0 +1,1505 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_EDN_BF52x_extended__
+#define __BFIN_CDEF_ADSP_EDN_BF52x_extended__
+
+#define pSIC_RVECT                     ((uint16_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */
+#define bfin_read_SIC_RVECT()          bfin_read16(SIC_RVECT)
+#define bfin_write_SIC_RVECT(val)      bfin_write16(SIC_RVECT, val)
+#define pSIC_IMASK0                    ((uint32_t volatile *)SIC_IMASK0) /* Interrupt Mask Register */
+#define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)
+#define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)
+#define pSIC_IAR0                      ((uint32_t volatile *)SIC_IAR0) /* Interrupt Assignment Register 0 */
+#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
+#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
+#define pSIC_IAR1                      ((uint32_t volatile *)SIC_IAR1) /* Interrupt Assignment Register 1 */
+#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
+#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
+#define pSIC_IAR2                      ((uint32_t volatile *)SIC_IAR2) /* Interrupt Assignment Register 2 */
+#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
+#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
+#define pSIC_IAR3                      ((uint32_t volatile *)SIC_IAR3) /* Interrupt Assignment Register 3 */
+#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
+#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
+#define pSIC_ISR0                      ((uint32_t volatile *)SIC_ISR0) /* Interrupt Status Register */
+#define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)
+#define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)
+#define pSIC_IWR0                      ((uint32_t volatile *)SIC_IWR0) /* Interrupt Wakeup Register */
+#define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)
+#define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)
+#define pSIC_IMASK1                    ((uint32_t volatile *)SIC_IMASK1) /* Interrupt Mask register of SIC2 */
+#define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)
+#define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)
+#define pSIC_IAR4                      ((uint32_t volatile *)SIC_IAR4) /* Interrupt Assignment register4 */
+#define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)
+#define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)
+#define pSIC_IAR5                      ((uint32_t volatile *)SIC_IAR5) /* Interrupt Assignment register5 */
+#define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)
+#define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)
+#define pSIC_IAR6                      ((uint32_t volatile *)SIC_IAR6) /* Interrupt Assignment register6 */
+#define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)
+#define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)
+#define pSIC_IAR7                      ((uint32_t volatile *)SIC_IAR7) /* Interrupt Assignment register7 */
+#define bfin_read_SIC_IAR7()           bfin_read32(SIC_IAR7)
+#define bfin_write_SIC_IAR7(val)       bfin_write32(SIC_IAR7, val)
+#define pSIC_ISR1                      ((uint32_t volatile *)SIC_ISR1) /* Interrupt Status register */
+#define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)
+#define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)
+#define pSIC_IWR1                      ((uint32_t volatile *)SIC_IWR1) /* Interrupt Wakeup register */
+#define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)
+#define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)
+#define pWDOG_CTL                      ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
+#define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
+#define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
+#define pWDOG_CNT                      ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
+#define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
+#define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
+#define pWDOG_STAT                     ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
+#define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
+#define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
+#define pRTC_STAT                      ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */
+#define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
+#define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
+#define pRTC_ICTL                      ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */
+#define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
+#define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
+#define pRTC_ISTAT                     ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */
+#define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
+#define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
+#define pRTC_SWCNT                     ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */
+#define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
+#define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
+#define pRTC_ALARM                     ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Time Register */
+#define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
+#define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
+#define pRTC_PREN                      ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */
+#define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
+#define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
+#define pUART0_THR                     ((uint16_t volatile *)UART0_THR) /* Transmit Holding register */
+#define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
+#define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
+#define pUART0_RBR                     ((uint16_t volatile *)UART0_RBR) /* Receive Buffer register */
+#define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
+#define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
+#define pUART0_DLL                     ((uint16_t volatile *)UART0_DLL) /* Divisor Latch (Low-Byte) */
+#define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
+#define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
+#define pUART0_IER                     ((uint16_t volatile *)UART0_IER) /* Interrupt Enable Register */
+#define bfin_read_UART0_IER()          bfin_read16(UART0_IER)
+#define bfin_write_UART0_IER(val)      bfin_write16(UART0_IER, val)
+#define pUART0_DLH                     ((uint16_t volatile *)UART0_DLH) /* Divisor Latch (High-Byte) */
+#define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
+#define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
+#define pUART0_IIR                     ((uint16_t volatile *)UART0_IIR) /* Interrupt Identification Register */
+#define bfin_read_UART0_IIR()          bfin_read16(UART0_IIR)
+#define bfin_write_UART0_IIR(val)      bfin_write16(UART0_IIR, val)
+#define pUART0_LCR                     ((uint16_t volatile *)UART0_LCR) /* Line Control Register */
+#define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
+#define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
+#define pUART0_MCR                     ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */
+#define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
+#define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
+#define pUART0_LSR                     ((uint16_t volatile *)UART0_LSR) /* Line Status Register */
+#define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
+#define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
+#define pUART0_MSR                     ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */
+#define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
+#define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
+#define pUART0_SCR                     ((uint16_t volatile *)UART0_SCR) /* SCR Scratch Register */
+#define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
+#define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
+#define pUART0_GCTL                    ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */
+#define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
+#define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
+#define pSPI_CTL                       ((uint16_t volatile *)SPI_CTL) /* SPI Control Register */
+#define bfin_read_SPI_CTL()            bfin_read16(SPI_CTL)
+#define bfin_write_SPI_CTL(val)        bfin_write16(SPI_CTL, val)
+#define pSPI_FLG                       ((uint16_t volatile *)SPI_FLG) /* SPI Flag register */
+#define bfin_read_SPI_FLG()            bfin_read16(SPI_FLG)
+#define bfin_write_SPI_FLG(val)        bfin_write16(SPI_FLG, val)
+#define pSPI_STAT                      ((uint16_t volatile *)SPI_STAT) /* SPI Status register */
+#define bfin_read_SPI_STAT()           bfin_read16(SPI_STAT)
+#define bfin_write_SPI_STAT(val)       bfin_write16(SPI_STAT, val)
+#define pSPI_TDBR                      ((uint16_t volatile *)SPI_TDBR) /* SPI Transmit Data Buffer Register */
+#define bfin_read_SPI_TDBR()           bfin_read16(SPI_TDBR)
+#define bfin_write_SPI_TDBR(val)       bfin_write16(SPI_TDBR, val)
+#define pSPI_RDBR                      ((uint16_t volatile *)SPI_RDBR) /* SPI Receive Data Buffer Register */
+#define bfin_read_SPI_RDBR()           bfin_read16(SPI_RDBR)
+#define bfin_write_SPI_RDBR(val)       bfin_write16(SPI_RDBR, val)
+#define pSPI_BAUD                      ((uint16_t volatile *)SPI_BAUD) /* SPI Baud rate Register */
+#define bfin_read_SPI_BAUD()           bfin_read16(SPI_BAUD)
+#define bfin_write_SPI_BAUD(val)       bfin_write16(SPI_BAUD, val)
+#define pSPI_SHADOW                    ((uint16_t volatile *)SPI_SHADOW) /* SPI_RDBR Shadow Register */
+#define bfin_read_SPI_SHADOW()         bfin_read16(SPI_SHADOW)
+#define bfin_write_SPI_SHADOW(val)     bfin_write16(SPI_SHADOW, val)
+#define pTIMER0_CONFIG                 ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */
+#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
+#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
+#define pTIMER0_COUNTER                ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */
+#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
+#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
+#define pTIMER0_PERIOD                 ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */
+#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
+#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
+#define pTIMER0_WIDTH                  ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */
+#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
+#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
+#define pTIMER1_CONFIG                 ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */
+#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
+#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
+#define pTIMER1_COUNTER                ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */
+#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
+#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
+#define pTIMER1_PERIOD                 ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */
+#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
+#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
+#define pTIMER1_WIDTH                  ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */
+#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
+#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
+#define pTIMER2_CONFIG                 ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */
+#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
+#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
+#define pTIMER2_COUNTER                ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */
+#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
+#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
+#define pTIMER2_PERIOD                 ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */
+#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
+#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
+#define pTIMER2_WIDTH                  ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */
+#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
+#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
+#define pTIMER3_CONFIG                 ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */
+#define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
+#define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
+#define pTIMER3_COUNTER                ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */
+#define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
+#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
+#define pTIMER3_PERIOD                 ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */
+#define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
+#define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
+#define pTIMER3_WIDTH                  ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */
+#define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
+#define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
+#define pTIMER4_CONFIG                 ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */
+#define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
+#define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
+#define pTIMER4_COUNTER                ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */
+#define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
+#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
+#define pTIMER4_PERIOD                 ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */
+#define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
+#define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
+#define pTIMER4_WIDTH                  ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */
+#define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
+#define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
+#define pTIMER5_CONFIG                 ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */
+#define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
+#define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
+#define pTIMER5_COUNTER                ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */
+#define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
+#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
+#define pTIMER5_PERIOD                 ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */
+#define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
+#define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
+#define pTIMER5_WIDTH                  ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */
+#define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
+#define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
+#define pTIMER6_CONFIG                 ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */
+#define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
+#define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
+#define pTIMER6_COUNTER                ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */
+#define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
+#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
+#define pTIMER6_PERIOD                 ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */
+#define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
+#define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
+#define pTIMER6_WIDTH                  ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register\n */
+#define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
+#define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
+#define pTIMER7_CONFIG                 ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */
+#define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
+#define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
+#define pTIMER7_COUNTER                ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */
+#define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
+#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
+#define pTIMER7_PERIOD                 ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */
+#define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
+#define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
+#define pTIMER7_WIDTH                  ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */
+#define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
+#define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
+#define pTIMER_ENABLE                  ((uint16_t volatile *)TIMER_ENABLE) /* Timer Enable Register */
+#define bfin_read_TIMER_ENABLE()       bfin_read16(TIMER_ENABLE)
+#define bfin_write_TIMER_ENABLE(val)   bfin_write16(TIMER_ENABLE, val)
+#define pTIMER_DISABLE                 ((uint16_t volatile *)TIMER_DISABLE) /* Timer Disable Register */
+#define bfin_read_TIMER_DISABLE()      bfin_read16(TIMER_DISABLE)
+#define bfin_write_TIMER_DISABLE(val)  bfin_write16(TIMER_DISABLE, val)
+#define pTIMER_STATUS                  ((uint32_t volatile *)TIMER_STATUS) /* Timer Status Register */
+#define bfin_read_TIMER_STATUS()       bfin_read32(TIMER_STATUS)
+#define bfin_write_TIMER_STATUS(val)   bfin_write32(TIMER_STATUS, val)
+#define pPORTFIO                       ((uint16_t volatile *)PORTFIO) /* Port F I/O Pin State Specify Register */
+#define bfin_read_PORTFIO()            bfin_read16(PORTFIO)
+#define bfin_write_PORTFIO(val)        bfin_write16(PORTFIO, val)
+#define pPORTFIO_CLEAR                 ((uint16_t volatile *)PORTFIO_CLEAR) /* Port F I/O Peripheral Interrupt Clear Register */
+#define bfin_read_PORTFIO_CLEAR()      bfin_read16(PORTFIO_CLEAR)
+#define bfin_write_PORTFIO_CLEAR(val)  bfin_write16(PORTFIO_CLEAR, val)
+#define pPORTFIO_SET                   ((uint16_t volatile *)PORTFIO_SET) /* Port F I/O Peripheral Interrupt Set Register */
+#define bfin_read_PORTFIO_SET()        bfin_read16(PORTFIO_SET)
+#define bfin_write_PORTFIO_SET(val)    bfin_write16(PORTFIO_SET, val)
+#define pPORTFIO_TOGGLE                ((uint16_t volatile *)PORTFIO_TOGGLE) /* Port F I/O Pin State Toggle Register */
+#define bfin_read_PORTFIO_TOGGLE()     bfin_read16(PORTFIO_TOGGLE)
+#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
+#define pPORTFIO_MASKA                 ((uint16_t volatile *)PORTFIO_MASKA) /* Port F I/O Mask State Specify Interrupt A Register */
+#define bfin_read_PORTFIO_MASKA()      bfin_read16(PORTFIO_MASKA)
+#define bfin_write_PORTFIO_MASKA(val)  bfin_write16(PORTFIO_MASKA, val)
+#define pPORTFIO_MASKA_CLEAR           ((uint16_t volatile *)PORTFIO_MASKA_CLEAR) /* Port F I/O Mask Disable Interrupt A Register */
+#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
+#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
+#define pPORTFIO_MASKA_SET             ((uint16_t volatile *)PORTFIO_MASKA_SET) /* Port F I/O Mask Enable Interrupt A Register */
+#define bfin_read_PORTFIO_MASKA_SET()  bfin_read16(PORTFIO_MASKA_SET)
+#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
+#define pPORTFIO_MASKA_TOGGLE          ((uint16_t volatile *)PORTFIO_MASKA_TOGGLE) /* Port F I/O Mask Toggle Enable Interrupt A Register */
+#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
+#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
+#define pPORTFIO_MASKB                 ((uint16_t volatile *)PORTFIO_MASKB) /* Port F I/O Mask State Specify Interrupt B Register */
+#define bfin_read_PORTFIO_MASKB()      bfin_read16(PORTFIO_MASKB)
+#define bfin_write_PORTFIO_MASKB(val)  bfin_write16(PORTFIO_MASKB, val)
+#define pPORTFIO_MASKB_CLEAR           ((uint16_t volatile *)PORTFIO_MASKB_CLEAR) /* Port F I/O Mask Disable Interrupt B Register */
+#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
+#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
+#define pPORTFIO_MASKB_SET             ((uint16_t volatile *)PORTFIO_MASKB_SET) /* Port F I/O Mask Enable Interrupt B Register */
+#define bfin_read_PORTFIO_MASKB_SET()  bfin_read16(PORTFIO_MASKB_SET)
+#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
+#define pPORTFIO_MASKB_TOGGLE          ((uint16_t volatile *)PORTFIO_MASKB_TOGGLE) /* Port F I/O Mask Toggle Enable Interrupt B Register */
+#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
+#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
+#define pPORTFIO_DIR                   ((uint16_t volatile *)PORTFIO_DIR) /* Port F I/O Direction Register */
+#define bfin_read_PORTFIO_DIR()        bfin_read16(PORTFIO_DIR)
+#define bfin_write_PORTFIO_DIR(val)    bfin_write16(PORTFIO_DIR, val)
+#define pPORTFIO_POLAR                 ((uint16_t volatile *)PORTFIO_POLAR) /* Port F I/O Source Polarity Register */
+#define bfin_read_PORTFIO_POLAR()      bfin_read16(PORTFIO_POLAR)
+#define bfin_write_PORTFIO_POLAR(val)  bfin_write16(PORTFIO_POLAR, val)
+#define pPORTFIO_EDGE                  ((uint16_t volatile *)PORTFIO_EDGE) /* Port F I/O Source Sensitivity Register */
+#define bfin_read_PORTFIO_EDGE()       bfin_read16(PORTFIO_EDGE)
+#define bfin_write_PORTFIO_EDGE(val)   bfin_write16(PORTFIO_EDGE, val)
+#define pPORTFIO_BOTH                  ((uint16_t volatile *)PORTFIO_BOTH) /* Port F I/O Set on BOTH Edges Register */
+#define bfin_read_PORTFIO_BOTH()       bfin_read16(PORTFIO_BOTH)
+#define bfin_write_PORTFIO_BOTH(val)   bfin_write16(PORTFIO_BOTH, val)
+#define pPORTFIO_INEN                  ((uint16_t volatile *)PORTFIO_INEN) /* Port F I/O Input Enable Register  */
+#define bfin_read_PORTFIO_INEN()       bfin_read16(PORTFIO_INEN)
+#define bfin_write_PORTFIO_INEN(val)   bfin_write16(PORTFIO_INEN, val)
+#define pSPORT0_TCR1                   ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */
+#define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)
+#define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)
+#define pSPORT0_TCR2                   ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */
+#define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)
+#define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)
+#define pSPORT0_TCLKDIV                ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Clock Divider */
+#define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)
+#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
+#define pSPORT0_TFSDIV                 ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider */
+#define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
+#define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
+#define pSPORT0_TX                     ((uint32_t volatile *)SPORT0_TX) /* SPORT0 TX Data Register */
+#define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
+#define pSPORT0_RX                     ((uint32_t volatile *)SPORT0_RX) /* SPORT0 RX Data Register */
+#define bfin_read_SPORT0_RX()          bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)
+#define pSPORT0_RCR1                   ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Transmit Configuration 1 Register */
+#define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
+#define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
+#define pSPORT0_RCR2                   ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Transmit Configuration 2 Register */
+#define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
+#define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
+#define pSPORT0_RCLKDIV                ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Clock Divider */
+#define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
+#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
+#define pSPORT0_RFSDIV                 ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider */
+#define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
+#define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
+#define pSPORT0_STAT                   ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */
+#define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
+#define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
+#define pSPORT0_CHNL                   ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */
+#define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
+#define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
+#define pSPORT0_MCMC1                  ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi-Channel Configuration Register 1 */
+#define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
+#define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
+#define pSPORT0_MCMC2                  ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi-Channel Configuration Register 2 */
+#define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
+#define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
+#define pSPORT0_MTCS0                  ((uint32_t volatile *)SPORT0_MTCS0) /* SPORT0 Multi-Channel Transmit Select Register 0 */
+#define bfin_read_SPORT0_MTCS0()       bfin_read32(SPORT0_MTCS0)
+#define bfin_write_SPORT0_MTCS0(val)   bfin_write32(SPORT0_MTCS0, val)
+#define pSPORT0_MTCS1                  ((uint32_t volatile *)SPORT0_MTCS1) /* SPORT0 Multi-Channel Transmit Select Register 1 */
+#define bfin_read_SPORT0_MTCS1()       bfin_read32(SPORT0_MTCS1)
+#define bfin_write_SPORT0_MTCS1(val)   bfin_write32(SPORT0_MTCS1, val)
+#define pSPORT0_MTCS2                  ((uint32_t volatile *)SPORT0_MTCS2) /* SPORT0 Multi-Channel Transmit Select Register 2 */
+#define bfin_read_SPORT0_MTCS2()       bfin_read32(SPORT0_MTCS2)
+#define bfin_write_SPORT0_MTCS2(val)   bfin_write32(SPORT0_MTCS2, val)
+#define pSPORT0_MTCS3                  ((uint32_t volatile *)SPORT0_MTCS3) /* SPORT0 Multi-Channel Transmit Select Register 3 */
+#define bfin_read_SPORT0_MTCS3()       bfin_read32(SPORT0_MTCS3)
+#define bfin_write_SPORT0_MTCS3(val)   bfin_write32(SPORT0_MTCS3, val)
+#define pSPORT0_MRCS0                  ((uint32_t volatile *)SPORT0_MRCS0) /* SPORT0 Multi-Channel Receive Select Register 0 */
+#define bfin_read_SPORT0_MRCS0()       bfin_read32(SPORT0_MRCS0)
+#define bfin_write_SPORT0_MRCS0(val)   bfin_write32(SPORT0_MRCS0, val)
+#define pSPORT0_MRCS1                  ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi-Channel Receive Select Register 1 */
+#define bfin_read_SPORT0_MRCS1()       bfin_read32(SPORT0_MRCS1)
+#define bfin_write_SPORT0_MRCS1(val)   bfin_write32(SPORT0_MRCS1, val)
+#define pSPORT0_MRCS2                  ((uint32_t volatile *)SPORT0_MRCS2) /* SPORT0 Multi-Channel Receive Select Register 2 */
+#define bfin_read_SPORT0_MRCS2()       bfin_read32(SPORT0_MRCS2)
+#define bfin_write_SPORT0_MRCS2(val)   bfin_write32(SPORT0_MRCS2, val)
+#define pSPORT0_MRCS3                  ((uint32_t volatile *)SPORT0_MRCS3) /* SPORT0 Multi-Channel Receive Select Register 3 */
+#define bfin_read_SPORT0_MRCS3()       bfin_read32(SPORT0_MRCS3)
+#define bfin_write_SPORT0_MRCS3(val)   bfin_write32(SPORT0_MRCS3, val)
+#define pSPORT1_TCR1                   ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
+#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
+#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
+#define pSPORT1_TCR2                   ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
+#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
+#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
+#define pSPORT1_TCLKDIV                ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Clock Divider */
+#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
+#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
+#define pSPORT1_TFSDIV                 ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider */
+#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
+#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
+#define pSPORT1_TX                     ((uint32_t volatile *)SPORT1_TX) /* SPORT1 TX Data Register */
+#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
+#define pSPORT1_RX                     ((uint32_t volatile *)SPORT1_RX) /* SPORT1 RX Data Register */
+#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
+#define pSPORT1_RCR1                   ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Transmit Configuration 1 Register */
+#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
+#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
+#define pSPORT1_RCR2                   ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Transmit Configuration 2 Register */
+#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
+#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
+#define pSPORT1_RCLKDIV                ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Clock Divider */
+#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
+#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
+#define pSPORT1_RFSDIV                 ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider */
+#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
+#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
+#define pSPORT1_STAT                   ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
+#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
+#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
+#define pSPORT1_CHNL                   ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
+#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
+#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
+#define pSPORT1_MCMC1                  ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi-Channel Configuration Register 1 */
+#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
+#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
+#define pSPORT1_MCMC2                  ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi-Channel Configuration Register 2 */
+#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
+#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
+#define pSPORT1_MTCS0                  ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi-Channel Transmit Select Register 0 */
+#define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
+#define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
+#define pSPORT1_MTCS1                  ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi-Channel Transmit Select Register 1 */
+#define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
+#define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
+#define pSPORT1_MTCS2                  ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi-Channel Transmit Select Register 2 */
+#define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
+#define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
+#define pSPORT1_MTCS3                  ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi-Channel Transmit Select Register 3 */
+#define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
+#define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
+#define pSPORT1_MRCS0                  ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi-Channel Receive Select Register 0 */
+#define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
+#define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
+#define pSPORT1_MRCS1                  ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi-Channel Receive Select Register 1 */
+#define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
+#define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
+#define pSPORT1_MRCS2                  ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi-Channel Receive Select Register 2 */
+#define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
+#define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
+#define pSPORT1_MRCS3                  ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi-Channel Receive Select Register 3 */
+#define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
+#define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
+#define pEBIU_AMGCTL                   ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */
+#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
+#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
+#define pEBIU_AMBCTL0                  ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register 0 */
+#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
+#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
+#define pEBIU_AMBCTL1                  ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register 1 */
+#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
+#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
+#define pEBIU_SDGCTL                   ((uint32_t volatile *)EBIU_SDGCTL) /* SDRAM Global Control Register */
+#define bfin_read_EBIU_SDGCTL()        bfin_read32(EBIU_SDGCTL)
+#define bfin_write_EBIU_SDGCTL(val)    bfin_write32(EBIU_SDGCTL, val)
+#define pEBIU_SDBCTL                   ((uint16_t volatile *)EBIU_SDBCTL) /* SDRAM Bank Control Register */
+#define bfin_read_EBIU_SDBCTL()        bfin_read16(EBIU_SDBCTL)
+#define bfin_write_EBIU_SDBCTL(val)    bfin_write16(EBIU_SDBCTL, val)
+#define pEBIU_SDRRC                    ((uint16_t volatile *)EBIU_SDRRC) /* SDRAM Refresh Rate Control Register */
+#define bfin_read_EBIU_SDRRC()         bfin_read16(EBIU_SDRRC)
+#define bfin_write_EBIU_SDRRC(val)     bfin_write16(EBIU_SDRRC, val)
+#define pEBIU_SDSTAT                   ((uint16_t volatile *)EBIU_SDSTAT) /* SDRAM Status Register */
+#define bfin_read_EBIU_SDSTAT()        bfin_read16(EBIU_SDSTAT)
+#define bfin_write_EBIU_SDSTAT(val)    bfin_write16(EBIU_SDSTAT, val)
+#define pDMA0_NEXT_DESC_PTR            ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */
+#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
+#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
+#define pDMA0_START_ADDR               ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
+#define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
+#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
+#define pDMA0_CONFIG                   ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
+#define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
+#define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
+#define pDMA0_X_COUNT                  ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */
+#define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
+#define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
+#define pDMA0_X_MODIFY                 ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */
+#define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
+#define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
+#define pDMA0_Y_COUNT                  ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */
+#define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
+#define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
+#define pDMA0_Y_MODIFY                 ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */
+#define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
+#define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
+#define pDMA0_CURR_DESC_PTR            ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */
+#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
+#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
+#define pDMA0_CURR_ADDR                ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
+#define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
+#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
+#define pDMA0_IRQ_STATUS               ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
+#define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
+#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
+#define pDMA0_PERIPHERAL_MAP           ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */
+#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
+#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
+#define pDMA0_CURR_X_COUNT             ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */
+#define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
+#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
+#define pDMA0_CURR_Y_COUNT             ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */
+#define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
+#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
+#define pDMA1_NEXT_DESC_PTR            ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */
+#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
+#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
+#define pDMA1_START_ADDR               ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
+#define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
+#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
+#define pDMA1_CONFIG                   ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
+#define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
+#define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
+#define pDMA1_X_COUNT                  ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */
+#define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
+#define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
+#define pDMA1_X_MODIFY                 ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */
+#define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
+#define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
+#define pDMA1_Y_COUNT                  ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */
+#define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
+#define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
+#define pDMA1_Y_MODIFY                 ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */
+#define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
+#define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
+#define pDMA1_CURR_DESC_PTR            ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */
+#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
+#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
+#define pDMA1_CURR_ADDR                ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
+#define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
+#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
+#define pDMA1_IRQ_STATUS               ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
+#define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
+#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
+#define pDMA1_PERIPHERAL_MAP           ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */
+#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
+#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
+#define pDMA1_CURR_X_COUNT             ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */
+#define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
+#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
+#define pDMA1_CURR_Y_COUNT             ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */
+#define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
+#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
+#define pDMA2_NEXT_DESC_PTR            ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */
+#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
+#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
+#define pDMA2_START_ADDR               ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
+#define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
+#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
+#define pDMA2_CONFIG                   ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
+#define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
+#define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
+#define pDMA2_X_COUNT                  ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */
+#define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
+#define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
+#define pDMA2_X_MODIFY                 ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */
+#define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
+#define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
+#define pDMA2_Y_COUNT                  ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */
+#define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
+#define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
+#define pDMA2_Y_MODIFY                 ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */
+#define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
+#define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
+#define pDMA2_CURR_DESC_PTR            ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */
+#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
+#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
+#define pDMA2_CURR_ADDR                ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
+#define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
+#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
+#define pDMA2_IRQ_STATUS               ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
+#define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
+#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
+#define pDMA2_PERIPHERAL_MAP           ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */
+#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
+#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
+#define pDMA2_CURR_X_COUNT             ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */
+#define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
+#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
+#define pDMA2_CURR_Y_COUNT             ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */
+#define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
+#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
+#define pDMA3_NEXT_DESC_PTR            ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */
+#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
+#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
+#define pDMA3_START_ADDR               ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
+#define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
+#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
+#define pDMA3_CONFIG                   ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
+#define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
+#define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
+#define pDMA3_X_COUNT                  ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */
+#define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
+#define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
+#define pDMA3_X_MODIFY                 ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */
+#define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
+#define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
+#define pDMA3_Y_COUNT                  ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */
+#define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
+#define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
+#define pDMA3_Y_MODIFY                 ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */
+#define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
+#define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
+#define pDMA3_CURR_DESC_PTR            ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */
+#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
+#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
+#define pDMA3_CURR_ADDR                ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
+#define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
+#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
+#define pDMA3_IRQ_STATUS               ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
+#define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
+#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
+#define pDMA3_PERIPHERAL_MAP           ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */
+#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
+#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
+#define pDMA3_CURR_X_COUNT             ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */
+#define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
+#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
+#define pDMA3_CURR_Y_COUNT             ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */
+#define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
+#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
+#define pDMA4_NEXT_DESC_PTR            ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */
+#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
+#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
+#define pDMA4_START_ADDR               ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
+#define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
+#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
+#define pDMA4_CONFIG                   ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
+#define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
+#define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
+#define pDMA4_X_COUNT                  ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */
+#define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
+#define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
+#define pDMA4_X_MODIFY                 ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */
+#define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
+#define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
+#define pDMA4_Y_COUNT                  ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */
+#define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
+#define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
+#define pDMA4_Y_MODIFY                 ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */
+#define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
+#define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
+#define pDMA4_CURR_DESC_PTR            ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */
+#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
+#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
+#define pDMA4_CURR_ADDR                ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
+#define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
+#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
+#define pDMA4_IRQ_STATUS               ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
+#define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
+#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
+#define pDMA4_PERIPHERAL_MAP           ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */
+#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
+#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
+#define pDMA4_CURR_X_COUNT             ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */
+#define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
+#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
+#define pDMA4_CURR_Y_COUNT             ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */
+#define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
+#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
+#define pDMA5_NEXT_DESC_PTR            ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */
+#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
+#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
+#define pDMA5_START_ADDR               ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
+#define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
+#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
+#define pDMA5_CONFIG                   ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
+#define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
+#define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
+#define pDMA5_X_COUNT                  ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */
+#define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
+#define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
+#define pDMA5_X_MODIFY                 ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */
+#define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
+#define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
+#define pDMA5_Y_COUNT                  ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */
+#define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
+#define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
+#define pDMA5_Y_MODIFY                 ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */
+#define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
+#define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
+#define pDMA5_CURR_DESC_PTR            ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */
+#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
+#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
+#define pDMA5_CURR_ADDR                ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
+#define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
+#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
+#define pDMA5_IRQ_STATUS               ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
+#define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
+#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
+#define pDMA5_PERIPHERAL_MAP           ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */
+#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
+#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
+#define pDMA5_CURR_X_COUNT             ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */
+#define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
+#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
+#define pDMA5_CURR_Y_COUNT             ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */
+#define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
+#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
+#define pDMA6_NEXT_DESC_PTR            ((uint32_t volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */
+#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
+#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
+#define pDMA6_START_ADDR               ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
+#define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
+#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
+#define pDMA6_CONFIG                   ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
+#define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
+#define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
+#define pDMA6_X_COUNT                  ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */
+#define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
+#define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
+#define pDMA6_X_MODIFY                 ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */
+#define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
+#define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
+#define pDMA6_Y_COUNT                  ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */
+#define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
+#define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
+#define pDMA6_Y_MODIFY                 ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */
+#define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
+#define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
+#define pDMA6_CURR_DESC_PTR            ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */
+#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
+#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
+#define pDMA6_CURR_ADDR                ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
+#define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
+#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
+#define pDMA6_IRQ_STATUS               ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
+#define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
+#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
+#define pDMA6_PERIPHERAL_MAP           ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */
+#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
+#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
+#define pDMA6_CURR_X_COUNT             ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */
+#define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
+#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
+#define pDMA6_CURR_Y_COUNT             ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */
+#define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
+#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
+#define pDMA7_NEXT_DESC_PTR            ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */
+#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
+#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
+#define pDMA7_START_ADDR               ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
+#define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
+#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
+#define pDMA7_CONFIG                   ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
+#define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
+#define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
+#define pDMA7_X_COUNT                  ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */
+#define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
+#define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
+#define pDMA7_X_MODIFY                 ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */
+#define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
+#define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
+#define pDMA7_Y_COUNT                  ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */
+#define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
+#define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
+#define pDMA7_Y_MODIFY                 ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */
+#define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
+#define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
+#define pDMA7_CURR_DESC_PTR            ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */
+#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
+#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
+#define pDMA7_CURR_ADDR                ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
+#define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
+#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
+#define pDMA7_IRQ_STATUS               ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
+#define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
+#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
+#define pDMA7_PERIPHERAL_MAP           ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */
+#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
+#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
+#define pDMA7_CURR_X_COUNT             ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */
+#define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
+#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
+#define pDMA7_CURR_Y_COUNT             ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */
+#define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
+#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
+#define pDMA8_NEXT_DESC_PTR            ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */
+#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
+#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
+#define pDMA8_START_ADDR               ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
+#define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
+#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
+#define pDMA8_CONFIG                   ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
+#define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
+#define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
+#define pDMA8_X_COUNT                  ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */
+#define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
+#define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
+#define pDMA8_X_MODIFY                 ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */
+#define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
+#define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
+#define pDMA8_Y_COUNT                  ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */
+#define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
+#define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
+#define pDMA8_Y_MODIFY                 ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */
+#define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
+#define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
+#define pDMA8_CURR_DESC_PTR            ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */
+#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
+#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
+#define pDMA8_CURR_ADDR                ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
+#define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
+#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
+#define pDMA8_IRQ_STATUS               ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
+#define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
+#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
+#define pDMA8_PERIPHERAL_MAP           ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */
+#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
+#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
+#define pDMA8_CURR_X_COUNT             ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */
+#define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
+#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
+#define pDMA8_CURR_Y_COUNT             ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */
+#define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
+#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
+#define pDMA9_NEXT_DESC_PTR            ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */
+#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
+#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
+#define pDMA9_START_ADDR               ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
+#define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
+#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
+#define pDMA9_CONFIG                   ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
+#define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
+#define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
+#define pDMA9_X_COUNT                  ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */
+#define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
+#define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
+#define pDMA9_X_MODIFY                 ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */
+#define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
+#define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
+#define pDMA9_Y_COUNT                  ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */
+#define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
+#define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
+#define pDMA9_Y_MODIFY                 ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */
+#define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
+#define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
+#define pDMA9_CURR_DESC_PTR            ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */
+#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
+#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
+#define pDMA9_CURR_ADDR                ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
+#define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
+#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
+#define pDMA9_IRQ_STATUS               ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
+#define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
+#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
+#define pDMA9_PERIPHERAL_MAP           ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */
+#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
+#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
+#define pDMA9_CURR_X_COUNT             ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */
+#define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
+#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
+#define pDMA9_CURR_Y_COUNT             ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */
+#define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
+#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
+#define pDMA10_NEXT_DESC_PTR           ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */
+#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
+#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
+#define pDMA10_START_ADDR              ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
+#define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
+#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
+#define pDMA10_CONFIG                  ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
+#define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
+#define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
+#define pDMA10_X_COUNT                 ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */
+#define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
+#define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
+#define pDMA10_X_MODIFY                ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */
+#define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
+#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
+#define pDMA10_Y_COUNT                 ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */
+#define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
+#define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
+#define pDMA10_Y_MODIFY                ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */
+#define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
+#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
+#define pDMA10_CURR_DESC_PTR           ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */
+#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
+#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
+#define pDMA10_CURR_ADDR               ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
+#define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
+#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
+#define pDMA10_IRQ_STATUS              ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
+#define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
+#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
+#define pDMA10_PERIPHERAL_MAP          ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */
+#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
+#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
+#define pDMA10_CURR_X_COUNT            ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */
+#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
+#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
+#define pDMA10_CURR_Y_COUNT            ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */
+#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
+#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
+#define pDMA11_NEXT_DESC_PTR           ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */
+#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
+#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
+#define pDMA11_START_ADDR              ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
+#define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
+#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
+#define pDMA11_CONFIG                  ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
+#define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
+#define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
+#define pDMA11_X_COUNT                 ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */
+#define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
+#define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
+#define pDMA11_X_MODIFY                ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */
+#define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
+#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
+#define pDMA11_Y_COUNT                 ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */
+#define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
+#define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
+#define pDMA11_Y_MODIFY                ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */
+#define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
+#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
+#define pDMA11_CURR_DESC_PTR           ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */
+#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
+#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
+#define pDMA11_CURR_ADDR               ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
+#define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
+#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
+#define pDMA11_IRQ_STATUS              ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
+#define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
+#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
+#define pDMA11_PERIPHERAL_MAP          ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */
+#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
+#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
+#define pDMA11_CURR_X_COUNT            ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */
+#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
+#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
+#define pDMA11_CURR_Y_COUNT            ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */
+#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
+#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
+#define pMDMA_S0_NEXT_DESC_PTR         ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
+#define pMDMA_S0_START_ADDR            ((void * volatile *)MDMA_S0_START_ADDR) /* MemDMA Stream 0 Source Start Address Register */
+#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
+#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
+#define pMDMA_S0_CONFIG                ((uint16_t volatile *)MDMA_S0_CONFIG) /* MemDMA Stream 0 Source Configuration Register */
+#define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
+#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
+#define pMDMA_S0_X_COUNT               ((uint16_t volatile *)MDMA_S0_X_COUNT) /* MemDMA Stream 0 Source X Count Register */
+#define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
+#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
+#define pMDMA_S0_X_MODIFY              ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* MemDMA Stream 0 Source X Modify Register */
+#define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
+#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
+#define pMDMA_S0_Y_COUNT               ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* MemDMA Stream 0 Source Y Count Register */
+#define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
+#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
+#define pMDMA_S0_Y_MODIFY              ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* MemDMA Stream 0 Source Y Modify Register */
+#define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
+#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
+#define pMDMA_S0_CURR_DESC_PTR         ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
+#define pMDMA_S0_CURR_ADDR             ((void * volatile *)MDMA_S0_CURR_ADDR) /* MemDMA Stream 0 Source Current Address Register */
+#define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
+#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
+#define pMDMA_S0_IRQ_STATUS            ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* MemDMA Stream 0 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
+#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
+#define pMDMA_S0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* MemDMA Stream 0 Source Peripheral Map Register */
+#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
+#define pMDMA_S0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* MemDMA Stream 0 Source Current X Count Register */
+#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
+#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
+#define pMDMA_S0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* MemDMA Stream 0 Source Current Y Count Register */
+#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
+#define pMDMA_D0_NEXT_DESC_PTR         ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
+#define pMDMA_D0_START_ADDR            ((void * volatile *)MDMA_D0_START_ADDR) /* MemDMA Stream 0 Destination Start Address Register */
+#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
+#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
+#define pMDMA_D0_CONFIG                ((uint16_t volatile *)MDMA_D0_CONFIG) /* MemDMA Stream 0 Destination Configuration Register */
+#define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
+#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
+#define pMDMA_D0_X_COUNT               ((uint16_t volatile *)MDMA_D0_X_COUNT) /* MemDMA Stream 0 Destination X Count Register */
+#define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
+#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
+#define pMDMA_D0_X_MODIFY              ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* MemDMA Stream 0 Destination X Modify Register */
+#define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
+#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
+#define pMDMA_D0_Y_COUNT               ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* MemDMA Stream 0 Destination Y Count Register */
+#define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
+#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
+#define pMDMA_D0_Y_MODIFY              ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* MemDMA Stream 0 Destination Y Modify Register */
+#define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
+#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
+#define pMDMA_D0_CURR_DESC_PTR         ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
+#define pMDMA_D0_CURR_ADDR             ((void * volatile *)MDMA_D0_CURR_ADDR) /* MemDMA Stream 0 Destination Current Address Register */
+#define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
+#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
+#define pMDMA_D0_IRQ_STATUS            ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* MemDMA Stream 0 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
+#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
+#define pMDMA_D0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* MemDMA Stream 0 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
+#define pMDMA_D0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* MemDMA Stream 0 Destination Current X Count Register */
+#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
+#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
+#define pMDMA_D0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* MemDMA Stream 0 Destination Current Y Count Register */
+#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
+#define pMDMA_S1_NEXT_DESC_PTR         ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
+#define pMDMA_S1_START_ADDR            ((void * volatile *)MDMA_S1_START_ADDR) /* MemDMA Stream 1 Source Start Address Register */
+#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
+#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
+#define pMDMA_S1_CONFIG                ((uint16_t volatile *)MDMA_S1_CONFIG) /* MemDMA Stream 1 Source Configuration Register */
+#define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
+#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
+#define pMDMA_S1_X_COUNT               ((uint16_t volatile *)MDMA_S1_X_COUNT) /* MemDMA Stream 1 Source X Count Register */
+#define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
+#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
+#define pMDMA_S1_X_MODIFY              ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* MemDMA Stream 1 Source X Modify Register */
+#define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
+#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
+#define pMDMA_S1_Y_COUNT               ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* MemDMA Stream 1 Source Y Count Register */
+#define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
+#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
+#define pMDMA_S1_Y_MODIFY              ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* MemDMA Stream 1 Source Y Modify Register */
+#define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
+#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
+#define pMDMA_S1_CURR_DESC_PTR         ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
+#define pMDMA_S1_CURR_ADDR             ((void * volatile *)MDMA_S1_CURR_ADDR) /* MemDMA Stream 1 Source Current Address Register */
+#define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
+#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
+#define pMDMA_S1_IRQ_STATUS            ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* MemDMA Stream 1 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
+#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
+#define pMDMA_S1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* MemDMA Stream 1 Source Peripheral Map Register */
+#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
+#define pMDMA_S1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* MemDMA Stream 1 Source Current X Count Register */
+#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
+#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
+#define pMDMA_S1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* MemDMA Stream 1 Source Current Y Count Register */
+#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
+#define pMDMA_D1_NEXT_DESC_PTR         ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
+#define pMDMA_D1_START_ADDR            ((void * volatile *)MDMA_D1_START_ADDR) /* MemDMA Stream 1 Destination Start Address Register */
+#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
+#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
+#define pMDMA_D1_CONFIG                ((uint16_t volatile *)MDMA_D1_CONFIG) /* MemDMA Stream 1 Destination Configuration Register */
+#define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
+#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
+#define pMDMA_D1_X_COUNT               ((uint16_t volatile *)MDMA_D1_X_COUNT) /* MemDMA Stream 1 Destination X Count Register */
+#define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
+#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
+#define pMDMA_D1_X_MODIFY              ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* MemDMA Stream 1 Destination X Modify Register */
+#define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
+#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
+#define pMDMA_D1_Y_COUNT               ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* MemDMA Stream 1 Destination Y Count Register */
+#define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
+#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
+#define pMDMA_D1_Y_MODIFY              ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* MemDMA Stream 1 Destination Y Modify Register */
+#define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
+#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
+#define pMDMA_D1_CURR_DESC_PTR         ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
+#define pMDMA_D1_CURR_ADDR             ((void * volatile *)MDMA_D1_CURR_ADDR) /* MemDMA Stream 1 Destination Current Address Register */
+#define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
+#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
+#define pMDMA_D1_IRQ_STATUS            ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* MemDMA Stream 1 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
+#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
+#define pMDMA_D1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* MemDMA Stream 1 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
+#define pMDMA_D1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* MemDMA Stream 1 Destination Current X Count Register */
+#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
+#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
+#define pMDMA_D1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* MemDMA Stream 1 Destination Current Y Count Register */
+#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
+#define pPPI_CONTROL                   ((uint16_t volatile *)PPI_CONTROL) /* PPI Control Register */
+#define bfin_read_PPI_CONTROL()        bfin_read16(PPI_CONTROL)
+#define bfin_write_PPI_CONTROL(val)    bfin_write16(PPI_CONTROL, val)
+#define pPPI_STATUS                    ((uint16_t volatile *)PPI_STATUS) /* PPI Status Register */
+#define bfin_read_PPI_STATUS()         bfin_read16(PPI_STATUS)
+#define bfin_write_PPI_STATUS(val)     bfin_write16(PPI_STATUS, val)
+#define pPPI_COUNT                     ((uint16_t volatile *)PPI_COUNT) /* PPI Transfer Count Register */
+#define bfin_read_PPI_COUNT()          bfin_read16(PPI_COUNT)
+#define bfin_write_PPI_COUNT(val)      bfin_write16(PPI_COUNT, val)
+#define pPPI_DELAY                     ((uint16_t volatile *)PPI_DELAY) /* PPI Delay Count Register */
+#define bfin_read_PPI_DELAY()          bfin_read16(PPI_DELAY)
+#define bfin_write_PPI_DELAY(val)      bfin_write16(PPI_DELAY, val)
+#define pPPI_FRAME                     ((uint16_t volatile *)PPI_FRAME) /* PPI Frame Length Register */
+#define bfin_read_PPI_FRAME()          bfin_read16(PPI_FRAME)
+#define bfin_write_PPI_FRAME(val)      bfin_write16(PPI_FRAME, val)
+#define pTWI_CLKDIV                    ((uint16_t volatile *)TWI_CLKDIV) /* Serial Clock Divider Register */
+#define bfin_read_TWI_CLKDIV()         bfin_read16(TWI_CLKDIV)
+#define bfin_write_TWI_CLKDIV(val)     bfin_write16(TWI_CLKDIV, val)
+#define pTWI_CONTROL                   ((uint16_t volatile *)TWI_CONTROL) /* TWI Control Register */
+#define bfin_read_TWI_CONTROL()        bfin_read16(TWI_CONTROL)
+#define bfin_write_TWI_CONTROL(val)    bfin_write16(TWI_CONTROL, val)
+#define pTWI_SLAVE_CTL                 ((uint16_t volatile *)TWI_SLAVE_CTL) /* Slave Mode Control Register */
+#define bfin_read_TWI_SLAVE_CTL()      bfin_read16(TWI_SLAVE_CTL)
+#define bfin_write_TWI_SLAVE_CTL(val)  bfin_write16(TWI_SLAVE_CTL, val)
+#define pTWI_SLAVE_STAT                ((uint16_t volatile *)TWI_SLAVE_STAT) /* Slave Mode Status Register */
+#define bfin_read_TWI_SLAVE_STAT()     bfin_read16(TWI_SLAVE_STAT)
+#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val)
+#define pTWI_SLAVE_ADDR                ((uint16_t volatile *)TWI_SLAVE_ADDR) /* Slave Mode Address Register */
+#define bfin_read_TWI_SLAVE_ADDR()     bfin_read16(TWI_SLAVE_ADDR)
+#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val)
+#define pTWI_MASTER_CTL                ((uint16_t volatile *)TWI_MASTER_CTL) /* Master Mode Control Register */
+#define bfin_read_TWI_MASTER_CTL()     bfin_read16(TWI_MASTER_CTL)
+#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val)
+#define pTWI_MASTER_STAT               ((uint16_t volatile *)TWI_MASTER_STAT) /* Master Mode Status Register */
+#define bfin_read_TWI_MASTER_STAT()    bfin_read16(TWI_MASTER_STAT)
+#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val)
+#define pTWI_MASTER_ADDR               ((uint16_t volatile *)TWI_MASTER_ADDR) /* Master Mode Address Register */
+#define bfin_read_TWI_MASTER_ADDR()    bfin_read16(TWI_MASTER_ADDR)
+#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val)
+#define pTWI_INT_STAT                  ((uint16_t volatile *)TWI_INT_STAT) /* TWI Interrupt Status Register */
+#define bfin_read_TWI_INT_STAT()       bfin_read16(TWI_INT_STAT)
+#define bfin_write_TWI_INT_STAT(val)   bfin_write16(TWI_INT_STAT, val)
+#define pTWI_INT_MASK                  ((uint16_t volatile *)TWI_INT_MASK) /* TWI Master Interrupt Mask Register */
+#define bfin_read_TWI_INT_MASK()       bfin_read16(TWI_INT_MASK)
+#define bfin_write_TWI_INT_MASK(val)   bfin_write16(TWI_INT_MASK, val)
+#define pTWI_FIFO_CTL                  ((uint16_t volatile *)TWI_FIFO_CTL) /* FIFO Control Register */
+#define bfin_read_TWI_FIFO_CTL()       bfin_read16(TWI_FIFO_CTL)
+#define bfin_write_TWI_FIFO_CTL(val)   bfin_write16(TWI_FIFO_CTL, val)
+#define pTWI_FIFO_STAT                 ((uint16_t volatile *)TWI_FIFO_STAT) /* FIFO Status Register */
+#define bfin_read_TWI_FIFO_STAT()      bfin_read16(TWI_FIFO_STAT)
+#define bfin_write_TWI_FIFO_STAT(val)  bfin_write16(TWI_FIFO_STAT, val)
+#define pTWI_XMT_DATA8                 ((uint16_t volatile *)TWI_XMT_DATA8) /* FIFO Transmit Data Single Byte Register */
+#define bfin_read_TWI_XMT_DATA8()      bfin_read16(TWI_XMT_DATA8)
+#define bfin_write_TWI_XMT_DATA8(val)  bfin_write16(TWI_XMT_DATA8, val)
+#define pTWI_XMT_DATA16                ((uint16_t volatile *)TWI_XMT_DATA16) /* FIFO Transmit Data Double Byte Register */
+#define bfin_read_TWI_XMT_DATA16()     bfin_read16(TWI_XMT_DATA16)
+#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val)
+#define pTWI_RCV_DATA8                 ((uint16_t volatile *)TWI_RCV_DATA8) /* FIFO Receive Data Single Byte Register */
+#define bfin_read_TWI_RCV_DATA8()      bfin_read16(TWI_RCV_DATA8)
+#define bfin_write_TWI_RCV_DATA8(val)  bfin_write16(TWI_RCV_DATA8, val)
+#define pTWI_RCV_DATA16                ((uint16_t volatile *)TWI_RCV_DATA16) /* FIFO Receive Data Double Byte Register */
+#define bfin_read_TWI_RCV_DATA16()     bfin_read16(TWI_RCV_DATA16)
+#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val)
+#define pPORTGIO                       ((uint16_t volatile *)PORTGIO) /* Port G I/O Pin State Specify Register */
+#define bfin_read_PORTGIO()            bfin_read16(PORTGIO)
+#define bfin_write_PORTGIO(val)        bfin_write16(PORTGIO, val)
+#define pPORTGIO_CLEAR                 ((uint16_t volatile *)PORTGIO_CLEAR) /* Port G I/O Peripheral Interrupt Clear Register */
+#define bfin_read_PORTGIO_CLEAR()      bfin_read16(PORTGIO_CLEAR)
+#define bfin_write_PORTGIO_CLEAR(val)  bfin_write16(PORTGIO_CLEAR, val)
+#define pPORTGIO_SET                   ((uint16_t volatile *)PORTGIO_SET) /* Port G I/O Peripheral Interrupt Set Register */
+#define bfin_read_PORTGIO_SET()        bfin_read16(PORTGIO_SET)
+#define bfin_write_PORTGIO_SET(val)    bfin_write16(PORTGIO_SET, val)
+#define pPORTGIO_TOGGLE                ((uint16_t volatile *)PORTGIO_TOGGLE) /* Port G I/O Pin State Toggle Register */
+#define bfin_read_PORTGIO_TOGGLE()     bfin_read16(PORTGIO_TOGGLE)
+#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
+#define pPORTGIO_MASKA                 ((uint16_t volatile *)PORTGIO_MASKA) /* Port G I/O Mask State Specify Interrupt A Register */
+#define bfin_read_PORTGIO_MASKA()      bfin_read16(PORTGIO_MASKA)
+#define bfin_write_PORTGIO_MASKA(val)  bfin_write16(PORTGIO_MASKA, val)
+#define pPORTGIO_MASKA_CLEAR           ((uint16_t volatile *)PORTGIO_MASKA_CLEAR) /* Port G I/O Mask Disable Interrupt A Register */
+#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
+#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
+#define pPORTGIO_MASKA_SET             ((uint16_t volatile *)PORTGIO_MASKA_SET) /* Port G I/O Mask Enable Interrupt A Register */
+#define bfin_read_PORTGIO_MASKA_SET()  bfin_read16(PORTGIO_MASKA_SET)
+#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
+#define pPORTGIO_MASKA_TOGGLE          ((uint16_t volatile *)PORTGIO_MASKA_TOGGLE) /* Port G I/O Mask Toggle Enable Interrupt A Register */
+#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
+#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
+#define pPORTGIO_MASKB                 ((uint16_t volatile *)PORTGIO_MASKB) /* Port G I/O Mask State Specify Interrupt B Register */
+#define bfin_read_PORTGIO_MASKB()      bfin_read16(PORTGIO_MASKB)
+#define bfin_write_PORTGIO_MASKB(val)  bfin_write16(PORTGIO_MASKB, val)
+#define pPORTGIO_MASKB_CLEAR           ((uint16_t volatile *)PORTGIO_MASKB_CLEAR) /* Port G I/O Mask Disable Interrupt B Register */
+#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
+#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
+#define pPORTGIO_MASKB_SET             ((uint16_t volatile *)PORTGIO_MASKB_SET) /* Port G I/O Mask Enable Interrupt B Register */
+#define bfin_read_PORTGIO_MASKB_SET()  bfin_read16(PORTGIO_MASKB_SET)
+#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
+#define pPORTGIO_MASKB_TOGGLE          ((uint16_t volatile *)PORTGIO_MASKB_TOGGLE) /* Port G I/O Mask Toggle Enable Interrupt B Register */
+#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
+#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
+#define pPORTGIO_DIR                   ((uint16_t volatile *)PORTGIO_DIR) /* Port G I/O Direction Register */
+#define bfin_read_PORTGIO_DIR()        bfin_read16(PORTGIO_DIR)
+#define bfin_write_PORTGIO_DIR(val)    bfin_write16(PORTGIO_DIR, val)
+#define pPORTGIO_POLAR                 ((uint16_t volatile *)PORTGIO_POLAR) /* Port G I/O Source Polarity Register */
+#define bfin_read_PORTGIO_POLAR()      bfin_read16(PORTGIO_POLAR)
+#define bfin_write_PORTGIO_POLAR(val)  bfin_write16(PORTGIO_POLAR, val)
+#define pPORTGIO_EDGE                  ((uint16_t volatile *)PORTGIO_EDGE) /* Port G I/O Source Sensitivity Register */
+#define bfin_read_PORTGIO_EDGE()       bfin_read16(PORTGIO_EDGE)
+#define bfin_write_PORTGIO_EDGE(val)   bfin_write16(PORTGIO_EDGE, val)
+#define pPORTGIO_BOTH                  ((uint16_t volatile *)PORTGIO_BOTH) /* Port G I/O Set on BOTH Edges Register */
+#define bfin_read_PORTGIO_BOTH()       bfin_read16(PORTGIO_BOTH)
+#define bfin_write_PORTGIO_BOTH(val)   bfin_write16(PORTGIO_BOTH, val)
+#define pPORTGIO_INEN                  ((uint16_t volatile *)PORTGIO_INEN) /* Port G I/O Input Enable Register */
+#define bfin_read_PORTGIO_INEN()       bfin_read16(PORTGIO_INEN)
+#define bfin_write_PORTGIO_INEN(val)   bfin_write16(PORTGIO_INEN, val)
+#define pPORTHIO                       ((uint16_t volatile *)PORTHIO) /* Port H I/O Pin State Specify Register */
+#define bfin_read_PORTHIO()            bfin_read16(PORTHIO)
+#define bfin_write_PORTHIO(val)        bfin_write16(PORTHIO, val)
+#define pPORTHIO_CLEAR                 ((uint16_t volatile *)PORTHIO_CLEAR) /* Port H I/O Peripheral Interrupt Clear Register */
+#define bfin_read_PORTHIO_CLEAR()      bfin_read16(PORTHIO_CLEAR)
+#define bfin_write_PORTHIO_CLEAR(val)  bfin_write16(PORTHIO_CLEAR, val)
+#define pPORTHIO_SET                   ((uint16_t volatile *)PORTHIO_SET) /* Port H I/O Peripheral Interrupt Set Register */
+#define bfin_read_PORTHIO_SET()        bfin_read16(PORTHIO_SET)
+#define bfin_write_PORTHIO_SET(val)    bfin_write16(PORTHIO_SET, val)
+#define pPORTHIO_TOGGLE                ((uint16_t volatile *)PORTHIO_TOGGLE) /* Port H I/O Pin State Toggle Register */
+#define bfin_read_PORTHIO_TOGGLE()     bfin_read16(PORTHIO_TOGGLE)
+#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
+#define pPORTHIO_MASKA                 ((uint16_t volatile *)PORTHIO_MASKA) /* Port H I/O Mask State Specify Interrupt A Register */
+#define bfin_read_PORTHIO_MASKA()      bfin_read16(PORTHIO_MASKA)
+#define bfin_write_PORTHIO_MASKA(val)  bfin_write16(PORTHIO_MASKA, val)
+#define pPORTHIO_MASKA_CLEAR           ((uint16_t volatile *)PORTHIO_MASKA_CLEAR) /* Port H I/O Mask Disable Interrupt A Register */
+#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
+#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
+#define pPORTHIO_MASKA_SET             ((uint16_t volatile *)PORTHIO_MASKA_SET) /* Port H I/O Mask Enable Interrupt A Register */
+#define bfin_read_PORTHIO_MASKA_SET()  bfin_read16(PORTHIO_MASKA_SET)
+#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
+#define pPORTHIO_MASKA_TOGGLE          ((uint16_t volatile *)PORTHIO_MASKA_TOGGLE) /* Port H I/O Mask Toggle Enable Interrupt A Register */
+#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
+#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
+#define pPORTHIO_MASKB                 ((uint16_t volatile *)PORTHIO_MASKB) /* Port H I/O Mask State Specify Interrupt B Register */
+#define bfin_read_PORTHIO_MASKB()      bfin_read16(PORTHIO_MASKB)
+#define bfin_write_PORTHIO_MASKB(val)  bfin_write16(PORTHIO_MASKB, val)
+#define pPORTHIO_MASKB_CLEAR           ((uint16_t volatile *)PORTHIO_MASKB_CLEAR) /* Port H I/O Mask Disable Interrupt B Register */
+#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
+#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
+#define pPORTHIO_MASKB_SET             ((uint16_t volatile *)PORTHIO_MASKB_SET) /* Port H I/O Mask Enable Interrupt B Register */
+#define bfin_read_PORTHIO_MASKB_SET()  bfin_read16(PORTHIO_MASKB_SET)
+#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
+#define pPORTHIO_MASKB_TOGGLE          ((uint16_t volatile *)PORTHIO_MASKB_TOGGLE) /* Port H I/O Mask Toggle Enable Interrupt B Register */
+#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
+#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
+#define pPORTHIO_DIR                   ((uint16_t volatile *)PORTHIO_DIR) /* Port H I/O Direction Register */
+#define bfin_read_PORTHIO_DIR()        bfin_read16(PORTHIO_DIR)
+#define bfin_write_PORTHIO_DIR(val)    bfin_write16(PORTHIO_DIR, val)
+#define pPORTHIO_POLAR                 ((uint16_t volatile *)PORTHIO_POLAR) /* Port H I/O Source Polarity Register */
+#define bfin_read_PORTHIO_POLAR()      bfin_read16(PORTHIO_POLAR)
+#define bfin_write_PORTHIO_POLAR(val)  bfin_write16(PORTHIO_POLAR, val)
+#define pPORTHIO_EDGE                  ((uint16_t volatile *)PORTHIO_EDGE) /* Port H I/O Source Sensitivity Register */
+#define bfin_read_PORTHIO_EDGE()       bfin_read16(PORTHIO_EDGE)
+#define bfin_write_PORTHIO_EDGE(val)   bfin_write16(PORTHIO_EDGE, val)
+#define pPORTHIO_BOTH                  ((uint16_t volatile *)PORTHIO_BOTH) /* Port H I/O Set on BOTH Edges Register */
+#define bfin_read_PORTHIO_BOTH()       bfin_read16(PORTHIO_BOTH)
+#define bfin_write_PORTHIO_BOTH(val)   bfin_write16(PORTHIO_BOTH, val)
+#define pPORTHIO_INEN                  ((uint16_t volatile *)PORTHIO_INEN) /* Port H I/O Input Enable Register */
+#define bfin_read_PORTHIO_INEN()       bfin_read16(PORTHIO_INEN)
+#define bfin_write_PORTHIO_INEN(val)   bfin_write16(PORTHIO_INEN, val)
+#define pUART1_THR                     ((uint16_t volatile *)UART1_THR) /* Transmit Holding register */
+#define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
+#define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
+#define pUART1_RBR                     ((uint16_t volatile *)UART1_RBR) /* Receive Buffer register */
+#define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
+#define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
+#define pUART1_DLL                     ((uint16_t volatile *)UART1_DLL) /* Divisor Latch (Low-Byte) */
+#define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
+#define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
+#define pUART1_IER                     ((uint16_t volatile *)UART1_IER) /* Interrupt Enable Register */
+#define bfin_read_UART1_IER()          bfin_read16(UART1_IER)
+#define bfin_write_UART1_IER(val)      bfin_write16(UART1_IER, val)
+#define pUART1_DLH                     ((uint16_t volatile *)UART1_DLH) /* Divisor Latch (High-Byte) */
+#define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
+#define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
+#define pUART1_IIR                     ((uint16_t volatile *)UART1_IIR) /* Interrupt Identification Register */
+#define bfin_read_UART1_IIR()          bfin_read16(UART1_IIR)
+#define bfin_write_UART1_IIR(val)      bfin_write16(UART1_IIR, val)
+#define pUART1_LCR                     ((uint16_t volatile *)UART1_LCR) /* Line Control Register */
+#define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
+#define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
+#define pUART1_MCR                     ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */
+#define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
+#define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
+#define pUART1_LSR                     ((uint16_t volatile *)UART1_LSR) /* Line Status Register */
+#define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
+#define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
+#define pUART1_MSR                     ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */
+#define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
+#define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
+#define pUART1_SCR                     ((uint16_t volatile *)UART1_SCR) /* SCR Scratch Register */
+#define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
+#define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
+#define pUART1_GCTL                    ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */
+#define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
+#define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
+#define pPORTF_FER                     ((uint16_t volatile *)PORTF_FER) /* Port F Function Enable Register (Alternate/Flag*) */
+#define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
+#define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
+#define pPORTG_FER                     ((uint16_t volatile *)PORTG_FER) /* Port G Function Enable Register (Alternate/Flag*) */
+#define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
+#define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
+#define pPORTH_FER                     ((uint16_t volatile *)PORTH_FER) /* Port H Function Enable Register (Alternate/Flag*) */
+#define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
+#define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
+#define pHMDMA0_CONTROL                ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */
+#define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
+#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
+#define pHMDMA0_ECINIT                 ((uint16_t volatile *)HMDMA0_ECINIT) /* HMDMA0 Initial Edge Count Register */
+#define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
+#define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
+#define pHMDMA0_BCINIT                 ((uint16_t volatile *)HMDMA0_BCINIT) /* HMDMA0 Initial Block Count Register */
+#define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
+#define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
+#define pHMDMA0_ECURGENT               ((uint16_t volatile *)HMDMA0_ECURGENT) /* HMDMA0 Urgent Edge Count Threshhold Register */
+#define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
+#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
+#define pHMDMA0_ECOVERFLOW             ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* HMDMA0 Edge Count Overflow Interrupt Register */
+#define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
+#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
+#define pHMDMA0_ECOUNT                 ((uint16_t volatile *)HMDMA0_ECOUNT) /* HMDMA0 Current Edge Count Register */
+#define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
+#define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
+#define pHMDMA0_BCOUNT                 ((uint16_t volatile *)HMDMA0_BCOUNT) /* HMDMA0 Current Block Count Register */
+#define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
+#define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
+#define pHMDMA1_CONTROL                ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */
+#define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
+#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
+#define pHMDMA1_ECINIT                 ((uint16_t volatile *)HMDMA1_ECINIT) /* HMDMA1 Initial Edge Count Register */
+#define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
+#define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
+#define pHMDMA1_BCINIT                 ((uint16_t volatile *)HMDMA1_BCINIT) /* HMDMA1 Initial Block Count Register */
+#define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
+#define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
+#define pHMDMA1_ECURGENT               ((uint16_t volatile *)HMDMA1_ECURGENT) /* HMDMA1 Urgent Edge Count Threshhold Register */
+#define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
+#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
+#define pHMDMA1_ECOVERFLOW             ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* HMDMA1 Edge Count Overflow Interrupt Register */
+#define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
+#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
+#define pHMDMA1_ECOUNT                 ((uint16_t volatile *)HMDMA1_ECOUNT) /* HMDMA1 Current Edge Count Register */
+#define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
+#define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
+#define pHMDMA1_BCOUNT                 ((uint16_t volatile *)HMDMA1_BCOUNT) /* HMDMA1 Current Block Count Register */
+#define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
+#define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
+#define pPORTF_MUX                     ((uint16_t volatile *)PORTF_MUX) /* Port F mux control */
+#define bfin_read_PORTF_MUX()          bfin_read16(PORTF_MUX)
+#define bfin_write_PORTF_MUX(val)      bfin_write16(PORTF_MUX, val)
+#define pPORTG_MUX                     ((uint16_t volatile *)PORTG_MUX) /* Port G mux control */
+#define bfin_read_PORTG_MUX()          bfin_read16(PORTG_MUX)
+#define bfin_write_PORTG_MUX(val)      bfin_write16(PORTG_MUX, val)
+#define pPORTH_MUX                     ((uint16_t volatile *)PORTH_MUX) /* Port H mux control */
+#define bfin_read_PORTH_MUX()          bfin_read16(PORTH_MUX)
+#define bfin_write_PORTH_MUX(val)      bfin_write16(PORTH_MUX, val)
+#define pPORTF_DRIVE                   ((uint16_t volatile *)PORTF_DRIVE) /* Port F drive strength control */
+#define bfin_read_PORTF_DRIVE()        bfin_read16(PORTF_DRIVE)
+#define bfin_write_PORTF_DRIVE(val)    bfin_write16(PORTF_DRIVE, val)
+#define pPORTG_DRIVE                   ((uint16_t volatile *)PORTG_DRIVE) /* Port G drive strength control */
+#define bfin_read_PORTG_DRIVE()        bfin_read16(PORTG_DRIVE)
+#define bfin_write_PORTG_DRIVE(val)    bfin_write16(PORTG_DRIVE, val)
+#define pPORTH_DRIVE                   ((uint16_t volatile *)PORTH_DRIVE) /* Port H drive strength control */
+#define bfin_read_PORTH_DRIVE()        bfin_read16(PORTH_DRIVE)
+#define bfin_write_PORTH_DRIVE(val)    bfin_write16(PORTH_DRIVE, val)
+#define pPORTF_SLEW                    ((uint16_t volatile *)PORTF_SLEW) /* Port F slew control */
+#define bfin_read_PORTF_SLEW()         bfin_read16(PORTF_SLEW)
+#define bfin_write_PORTF_SLEW(val)     bfin_write16(PORTF_SLEW, val)
+#define pPORTG_SLEW                    ((uint16_t volatile *)PORTG_SLEW) /* Port G slew control */
+#define bfin_read_PORTG_SLEW()         bfin_read16(PORTG_SLEW)
+#define bfin_write_PORTG_SLEW(val)     bfin_write16(PORTG_SLEW, val)
+#define pPORTH_SLEW                    ((uint16_t volatile *)PORTH_SLEW) /* Port H slew control */
+#define bfin_read_PORTH_SLEW()         bfin_read16(PORTH_SLEW)
+#define bfin_write_PORTH_SLEW(val)     bfin_write16(PORTH_SLEW, val)
+#define pPORTF_HYSTERESIS              ((uint16_t volatile *)PORTF_HYSTERESIS) /* Port F Schmitt trigger control */
+#define bfin_read_PORTF_HYSTERESIS()   bfin_read16(PORTF_HYSTERESIS)
+#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val)
+#define pPORTG_HYSTERESIS              ((uint16_t volatile *)PORTG_HYSTERESIS) /* Port G Schmitt trigger control */
+#define bfin_read_PORTG_HYSTERESIS()   bfin_read16(PORTG_HYSTERESIS)
+#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val)
+#define pPORTH_HYSTERESIS              ((uint16_t volatile *)PORTH_HYSTERESIS) /* Port H Schmitt trigger control */
+#define bfin_read_PORTH_HYSTERESIS()   bfin_read16(PORTH_HYSTERESIS)
+#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val)
+#define pNONGPIO_DRIVE                 ((uint16_t volatile *)NONGPIO_DRIVE) /* Non-GPIO Port drive strength control */
+#define bfin_read_NONGPIO_DRIVE()      bfin_read16(NONGPIO_DRIVE)
+#define bfin_write_NONGPIO_DRIVE(val)  bfin_write16(NONGPIO_DRIVE, val)
+#define pNONGPIO_SLEW                  ((uint16_t volatile *)NONGPIO_SLEW) /* Non-GPIO Port slew control */
+#define bfin_read_NONGPIO_SLEW()       bfin_read16(NONGPIO_SLEW)
+#define bfin_write_NONGPIO_SLEW(val)   bfin_write16(NONGPIO_SLEW, val)
+#define pNONGPIO_HYSTERESIS            ((uint16_t volatile *)NONGPIO_HYSTERESIS) /* Non-GPIO Port Schmitt trigger control */
+#define bfin_read_NONGPIO_HYSTERESIS() bfin_read16(NONGPIO_HYSTERESIS)
+#define bfin_write_NONGPIO_HYSTERESIS(val) bfin_write16(NONGPIO_HYSTERESIS, val)
+#define pHOST_CONTROL                  ((uint16_t volatile *)HOST_CONTROL) /* HOST Control Register */
+#define bfin_read_HOST_CONTROL()       bfin_read16(HOST_CONTROL)
+#define bfin_write_HOST_CONTROL(val)   bfin_write16(HOST_CONTROL, val)
+#define pHOST_STATUS                   ((uint16_t volatile *)HOST_STATUS) /* HOST Status Register */
+#define bfin_read_HOST_STATUS()        bfin_read16(HOST_STATUS)
+#define bfin_write_HOST_STATUS(val)    bfin_write16(HOST_STATUS, val)
+#define pHOST_TIMEOUT                  ((uint16_t volatile *)HOST_TIMEOUT) /* HOST Acknowledge Mode Timeout Register */
+#define bfin_read_HOST_TIMEOUT()       bfin_read16(HOST_TIMEOUT)
+#define bfin_write_HOST_TIMEOUT(val)   bfin_write16(HOST_TIMEOUT, val)
+#define pCNT_CONFIG                    ((uint16_t volatile *)CNT_CONFIG) /* Configuration/Control Register */
+#define bfin_read_CNT_CONFIG()         bfin_read16(CNT_CONFIG)
+#define bfin_write_CNT_CONFIG(val)     bfin_write16(CNT_CONFIG, val)
+#define pCNT_IMASK                     ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */
+#define bfin_read_CNT_IMASK()          bfin_read16(CNT_IMASK)
+#define bfin_write_CNT_IMASK(val)      bfin_write16(CNT_IMASK, val)
+#define pCNT_STATUS                    ((uint16_t volatile *)CNT_STATUS) /* Status Register */
+#define bfin_read_CNT_STATUS()         bfin_read16(CNT_STATUS)
+#define bfin_write_CNT_STATUS(val)     bfin_write16(CNT_STATUS, val)
+#define pCNT_COMMAND                   ((uint16_t volatile *)CNT_COMMAND) /* Command Register */
+#define bfin_read_CNT_COMMAND()        bfin_read16(CNT_COMMAND)
+#define bfin_write_CNT_COMMAND(val)    bfin_write16(CNT_COMMAND, val)
+#define pCNT_DEBOUNCE                  ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Prescaler Register */
+#define bfin_read_CNT_DEBOUNCE()       bfin_read16(CNT_DEBOUNCE)
+#define bfin_write_CNT_DEBOUNCE(val)   bfin_write16(CNT_DEBOUNCE, val)
+#define pCNT_COUNTER                   ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */
+#define bfin_read_CNT_COUNTER()        bfin_read32(CNT_COUNTER)
+#define bfin_write_CNT_COUNTER(val)    bfin_write32(CNT_COUNTER, val)
+#define pCNT_MAX                       ((uint32_t volatile *)CNT_MAX) /* Maximal Count Boundary Value Register */
+#define bfin_read_CNT_MAX()            bfin_read32(CNT_MAX)
+#define bfin_write_CNT_MAX(val)        bfin_write32(CNT_MAX, val)
+#define pCNT_MIN                       ((uint32_t volatile *)CNT_MIN) /* Minimal Count Boundary Value Register */
+#define bfin_read_CNT_MIN()            bfin_read32(CNT_MIN)
+#define bfin_write_CNT_MIN(val)        bfin_write32(CNT_MIN, val)
+#define pOTP_CONTROL                   ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */
+#define bfin_read_OTP_CONTROL()        bfin_read16(OTP_CONTROL)
+#define bfin_write_OTP_CONTROL(val)    bfin_write16(OTP_CONTROL, val)
+#define pOTP_BEN                       ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */
+#define bfin_read_OTP_BEN()            bfin_read16(OTP_BEN)
+#define bfin_write_OTP_BEN(val)        bfin_write16(OTP_BEN, val)
+#define pOTP_STATUS                    ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */
+#define bfin_read_OTP_STATUS()         bfin_read16(OTP_STATUS)
+#define bfin_write_OTP_STATUS(val)     bfin_write16(OTP_STATUS, val)
+#define pOTP_TIMING                    ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */
+#define bfin_read_OTP_TIMING()         bfin_read32(OTP_TIMING)
+#define bfin_write_OTP_TIMING(val)     bfin_write32(OTP_TIMING, val)
+#define pSECURE_SYSSWT                 ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */
+#define bfin_read_SECURE_SYSSWT()      bfin_read32(SECURE_SYSSWT)
+#define bfin_write_SECURE_SYSSWT(val)  bfin_write32(SECURE_SYSSWT, val)
+#define pSECURE_CONTROL                ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */
+#define bfin_read_SECURE_CONTROL()     bfin_read16(SECURE_CONTROL)
+#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
+#define pSECURE_STATUS                 ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */
+#define bfin_read_SECURE_STATUS()      bfin_read16(SECURE_STATUS)
+#define bfin_write_SECURE_STATUS(val)  bfin_write16(SECURE_STATUS, val)
+#define pOTP_DATA0                     ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA0()          bfin_read32(OTP_DATA0)
+#define bfin_write_OTP_DATA0(val)      bfin_write32(OTP_DATA0, val)
+#define pOTP_DATA1                     ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA1()          bfin_read32(OTP_DATA1)
+#define bfin_write_OTP_DATA1(val)      bfin_write32(OTP_DATA1, val)
+#define pOTP_DATA2                     ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA2()          bfin_read32(OTP_DATA2)
+#define bfin_write_OTP_DATA2(val)      bfin_write32(OTP_DATA2, val)
+#define pOTP_DATA3                     ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA3()          bfin_read32(OTP_DATA3)
+#define bfin_write_OTP_DATA3(val)      bfin_write32(OTP_DATA3, val)
+#define pNFC_CTL                       ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */
+#define bfin_read_NFC_CTL()            bfin_read16(NFC_CTL)
+#define bfin_write_NFC_CTL(val)        bfin_write16(NFC_CTL, val)
+#define pNFC_STAT                      ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */
+#define bfin_read_NFC_STAT()           bfin_read16(NFC_STAT)
+#define bfin_write_NFC_STAT(val)       bfin_write16(NFC_STAT, val)
+#define pNFC_IRQSTAT                   ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */
+#define bfin_read_NFC_IRQSTAT()        bfin_read16(NFC_IRQSTAT)
+#define bfin_write_NFC_IRQSTAT(val)    bfin_write16(NFC_IRQSTAT, val)
+#define pNFC_IRQMASK                   ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */
+#define bfin_read_NFC_IRQMASK()        bfin_read16(NFC_IRQMASK)
+#define bfin_write_NFC_IRQMASK(val)    bfin_write16(NFC_IRQMASK, val)
+#define pNFC_ECC0                      ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */
+#define bfin_read_NFC_ECC0()           bfin_read16(NFC_ECC0)
+#define bfin_write_NFC_ECC0(val)       bfin_write16(NFC_ECC0, val)
+#define pNFC_ECC1                      ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */
+#define bfin_read_NFC_ECC1()           bfin_read16(NFC_ECC1)
+#define bfin_write_NFC_ECC1(val)       bfin_write16(NFC_ECC1, val)
+#define pNFC_ECC2                      ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */
+#define bfin_read_NFC_ECC2()           bfin_read16(NFC_ECC2)
+#define bfin_write_NFC_ECC2(val)       bfin_write16(NFC_ECC2, val)
+#define pNFC_ECC3                      ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */
+#define bfin_read_NFC_ECC3()           bfin_read16(NFC_ECC3)
+#define bfin_write_NFC_ECC3(val)       bfin_write16(NFC_ECC3, val)
+#define pNFC_COUNT                     ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */
+#define bfin_read_NFC_COUNT()          bfin_read16(NFC_COUNT)
+#define bfin_write_NFC_COUNT(val)      bfin_write16(NFC_COUNT, val)
+#define pNFC_RST                       ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */
+#define bfin_read_NFC_RST()            bfin_read16(NFC_RST)
+#define bfin_write_NFC_RST(val)        bfin_write16(NFC_RST, val)
+#define pNFC_PGCTL                     ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */
+#define bfin_read_NFC_PGCTL()          bfin_read16(NFC_PGCTL)
+#define bfin_write_NFC_PGCTL(val)      bfin_write16(NFC_PGCTL, val)
+#define pNFC_READ                      ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */
+#define bfin_read_NFC_READ()           bfin_read16(NFC_READ)
+#define bfin_write_NFC_READ(val)       bfin_write16(NFC_READ, val)
+#define pNFC_ADDR                      ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */
+#define bfin_read_NFC_ADDR()           bfin_read16(NFC_ADDR)
+#define bfin_write_NFC_ADDR(val)       bfin_write16(NFC_ADDR, val)
+#define pNFC_CMD                       ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */
+#define bfin_read_NFC_CMD()            bfin_read16(NFC_CMD)
+#define bfin_write_NFC_CMD(val)        bfin_write16(NFC_CMD, val)
+#define pNFC_DATA_WR                   ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */
+#define bfin_read_NFC_DATA_WR()        bfin_read16(NFC_DATA_WR)
+#define bfin_write_NFC_DATA_WR(val)    bfin_write16(NFC_DATA_WR, val)
+#define pNFC_DATA_RD                   ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */
+#define bfin_read_NFC_DATA_RD()        bfin_read16(NFC_DATA_RD)
+#define bfin_write_NFC_DATA_RD(val)    bfin_write16(NFC_DATA_RD, val)
+#define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
+#define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
+#define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
+#define pTBUFSTAT                      ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
+#define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
+#define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
+#define pTBUF                          ((void * volatile *)TBUF) /* Trace Buffer */
+#define bfin_read_TBUF()               bfin_readPTR(TBUF)
+#define bfin_write_TBUF(val)           bfin_writePTR(TBUF, val)
+#define pPFCTL                         ((uint32_t volatile *)PFCTL)
+#define bfin_read_PFCTL()              bfin_read32(PFCTL)
+#define bfin_write_PFCTL(val)          bfin_write32(PFCTL, val)
+#define pPFCNTR0                       ((uint32_t volatile *)PFCNTR0)
+#define bfin_read_PFCNTR0()            bfin_read32(PFCNTR0)
+#define bfin_write_PFCNTR0(val)        bfin_write32(PFCNTR0, val)
+#define pPFCNTR1                       ((uint32_t volatile *)PFCNTR1)
+#define bfin_read_PFCNTR1()            bfin_read32(PFCNTR1)
+#define bfin_write_PFCNTR1(val)        bfin_write32(PFCNTR1, val)
+#define pDMA_TC_CNT                    ((uint16_t volatile *)DMA_TC_CNT)
+#define bfin_read_DMA_TC_CNT()         bfin_read16(DMA_TC_CNT)
+#define bfin_write_DMA_TC_CNT(val)     bfin_write16(DMA_TC_CNT, val)
+#define pDMA_TC_PER                    ((uint16_t volatile *)DMA_TC_PER)
+#define bfin_read_DMA_TC_PER()         bfin_read16(DMA_TC_PER)
+#define bfin_write_DMA_TC_PER(val)     bfin_write16(DMA_TC_PER, val)
+
+#endif /* __BFIN_CDEF_ADSP_EDN_BF52x_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_def.h b/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_def.h
new file mode 100644
index 000000000..0b384808e
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_def.h
@@ -0,0 +1,509 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_EDN_BF52x_extended__
+#define __BFIN_DEF_ADSP_EDN_BF52x_extended__
+
+#define SIC_RVECT                      0xFFC00108 /* Interrupt Reset Vector Address Register */
+#define SIC_IMASK0                     0xFFC0010C /* Interrupt Mask Register */
+#define SIC_IAR0                       0xFFC00110 /* Interrupt Assignment Register 0 */
+#define SIC_IAR1                       0xFFC00114 /* Interrupt Assignment Register 1 */
+#define SIC_IAR2                       0xFFC00118 /* Interrupt Assignment Register 2 */
+#define SIC_IAR3                       0xFFC0011C /* Interrupt Assignment Register 3 */
+#define SIC_ISR0                       0xFFC00120 /* Interrupt Status Register */
+#define SIC_IWR0                       0xFFC00124 /* Interrupt Wakeup Register */
+#define SIC_IMASK1                     0xFFC0014C /* Interrupt Mask register of SIC2 */
+#define SIC_IAR4                       0xFFC00150 /* Interrupt Assignment register4 */
+#define SIC_IAR5                       0xFFC00154 /* Interrupt Assignment register5 */
+#define SIC_IAR6                       0xFFC00158 /* Interrupt Assignment register6 */
+#define SIC_IAR7                       0xFFC0015C /* Interrupt Assignment register7 */
+#define SIC_ISR1                       0xFFC00160 /* Interrupt Status register */
+#define SIC_IWR1                       0xFFC00164 /* Interrupt Wakeup register */
+#define WDOG_CTL                       0xFFC00200 /* Watchdog Control Register */
+#define WDOG_CNT                       0xFFC00204 /* Watchdog Count Register */
+#define WDOG_STAT                      0xFFC00208 /* Watchdog Status Register */
+#define RTC_STAT                       0xFFC00300 /* RTC Status Register */
+#define RTC_ICTL                       0xFFC00304 /* RTC Interrupt Control Register */
+#define RTC_ISTAT                      0xFFC00308 /* RTC Interrupt Status Register */
+#define RTC_SWCNT                      0xFFC0030C /* RTC Stopwatch Count Register */
+#define RTC_ALARM                      0xFFC00310 /* RTC Alarm Time Register */
+#define RTC_PREN                       0xFFC00314 /* RTC Prescaler Enable Register */
+#define UART0_THR                      0xFFC00400 /* Transmit Holding register */
+#define UART0_RBR                      0xFFC00400 /* Receive Buffer register */
+#define UART0_DLL                      0xFFC00400 /* Divisor Latch (Low-Byte) */
+#define UART0_IER                      0xFFC00404 /* Interrupt Enable Register */
+#define UART0_DLH                      0xFFC00404 /* Divisor Latch (High-Byte) */
+#define UART0_IIR                      0xFFC00408 /* Interrupt Identification Register */
+#define UART0_LCR                      0xFFC0040C /* Line Control Register */
+#define UART0_MCR                      0xFFC00410 /* Modem Control Register */
+#define UART0_LSR                      0xFFC00414 /* Line Status Register */
+#define UART0_MSR                      0xFFC00418 /* Modem Status Register */
+#define UART0_SCR                      0xFFC0041C /* SCR Scratch Register */
+#define UART0_GCTL                     0xFFC00424 /* Global Control Register */
+#define SPI_CTL                        0xFFC00500 /* SPI Control Register */
+#define SPI_FLG                        0xFFC00504 /* SPI Flag register */
+#define SPI_STAT                       0xFFC00508 /* SPI Status register */
+#define SPI_TDBR                       0xFFC0050C /* SPI Transmit Data Buffer Register */
+#define SPI_RDBR                       0xFFC00510 /* SPI Receive Data Buffer Register */
+#define SPI_BAUD                       0xFFC00514 /* SPI Baud rate Register */
+#define SPI_SHADOW                     0xFFC00518 /* SPI_RDBR Shadow Register */
+#define TIMER0_CONFIG                  0xFFC00600 /* Timer 0 Configuration Register */
+#define TIMER0_COUNTER                 0xFFC00604 /* Timer 0 Counter Register */
+#define TIMER0_PERIOD                  0xFFC00608 /* Timer 0 Period Register */
+#define TIMER0_WIDTH                   0xFFC0060C /* Timer 0 Width Register */
+#define TIMER1_CONFIG                  0xFFC00610 /* Timer 1 Configuration Register */
+#define TIMER1_COUNTER                 0xFFC00614 /* Timer 1 Counter Register */
+#define TIMER1_PERIOD                  0xFFC00618 /* Timer 1 Period Register */
+#define TIMER1_WIDTH                   0xFFC0061C /* Timer 1 Width Register */
+#define TIMER2_CONFIG                  0xFFC00620 /* Timer 2 Configuration Register */
+#define TIMER2_COUNTER                 0xFFC00624 /* Timer 2 Counter Register */
+#define TIMER2_PERIOD                  0xFFC00628 /* Timer 2 Period Register */
+#define TIMER2_WIDTH                   0xFFC0062C /* Timer 2 Width Register */
+#define TIMER3_CONFIG                  0xFFC00630 /* Timer 3 Configuration Register */
+#define TIMER3_COUNTER                 0xFFC00634 /* Timer 3 Counter Register */
+#define TIMER3_PERIOD                  0xFFC00638 /* Timer 3 Period Register */
+#define TIMER3_WIDTH                   0xFFC0063C /* Timer 3 Width Register */
+#define TIMER4_CONFIG                  0xFFC00640 /* Timer 4 Configuration Register */
+#define TIMER4_COUNTER                 0xFFC00644 /* Timer 4 Counter Register */
+#define TIMER4_PERIOD                  0xFFC00648 /* Timer 4 Period Register */
+#define TIMER4_WIDTH                   0xFFC0064C /* Timer 4 Width Register */
+#define TIMER5_CONFIG                  0xFFC00650 /* Timer 5 Configuration Register */
+#define TIMER5_COUNTER                 0xFFC00654 /* Timer 5 Counter Register */
+#define TIMER5_PERIOD                  0xFFC00658 /* Timer 5 Period Register */
+#define TIMER5_WIDTH                   0xFFC0065C /* Timer 5 Width Register */
+#define TIMER6_CONFIG                  0xFFC00660 /* Timer 6 Configuration Register */
+#define TIMER6_COUNTER                 0xFFC00664 /* Timer 6 Counter Register */
+#define TIMER6_PERIOD                  0xFFC00668 /* Timer 6 Period Register */
+#define TIMER6_WIDTH                   0xFFC0066C /* Timer 6 Width Register\n */
+#define TIMER7_CONFIG                  0xFFC00670 /* Timer 7 Configuration Register */
+#define TIMER7_COUNTER                 0xFFC00674 /* Timer 7 Counter Register */
+#define TIMER7_PERIOD                  0xFFC00678 /* Timer 7 Period Register */
+#define TIMER7_WIDTH                   0xFFC0067C /* Timer 7 Width Register */
+#define TIMER_ENABLE                   0xFFC00680 /* Timer Enable Register */
+#define TIMER_DISABLE                  0xFFC00684 /* Timer Disable Register */
+#define TIMER_STATUS                   0xFFC00688 /* Timer Status Register */
+#define PORTFIO                        0xFFC00700 /* Port F I/O Pin State Specify Register */
+#define PORTFIO_CLEAR                  0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
+#define PORTFIO_SET                    0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
+#define PORTFIO_TOGGLE                 0xFFC0070C /* Port F I/O Pin State Toggle Register */
+#define PORTFIO_MASKA                  0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
+#define PORTFIO_MASKA_CLEAR            0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
+#define PORTFIO_MASKA_SET              0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
+#define PORTFIO_MASKA_TOGGLE           0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
+#define PORTFIO_MASKB                  0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
+#define PORTFIO_MASKB_CLEAR            0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
+#define PORTFIO_MASKB_SET              0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
+#define PORTFIO_MASKB_TOGGLE           0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
+#define PORTFIO_DIR                    0xFFC00730 /* Port F I/O Direction Register */
+#define PORTFIO_POLAR                  0xFFC00734 /* Port F I/O Source Polarity Register */
+#define PORTFIO_EDGE                   0xFFC00738 /* Port F I/O Source Sensitivity Register */
+#define PORTFIO_BOTH                   0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
+#define PORTFIO_INEN                   0xFFC00740 /* Port F I/O Input Enable Register  */
+#define SPORT0_TCR1                    0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_TCR2                    0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_TCLKDIV                 0xFFC00808 /* SPORT0 Transmit Clock Divider */
+#define SPORT0_TFSDIV                  0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
+#define SPORT0_TX                      0xFFC00810 /* SPORT0 TX Data Register */
+#define SPORT0_RX                      0xFFC00818 /* SPORT0 RX Data Register */
+#define SPORT0_RCR1                    0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_RCR2                    0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_RCLKDIV                 0xFFC00828 /* SPORT0 Receive Clock Divider */
+#define SPORT0_RFSDIV                  0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
+#define SPORT0_STAT                    0xFFC00830 /* SPORT0 Status Register */
+#define SPORT0_CHNL                    0xFFC00834 /* SPORT0 Current Channel Register */
+#define SPORT0_MCMC1                   0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
+#define SPORT0_MCMC2                   0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
+#define SPORT0_MTCS0                   0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
+#define SPORT0_MTCS1                   0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
+#define SPORT0_MTCS2                   0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
+#define SPORT0_MTCS3                   0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
+#define SPORT0_MRCS0                   0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
+#define SPORT0_MRCS1                   0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
+#define SPORT0_MRCS2                   0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
+#define SPORT0_MRCS3                   0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
+#define SPORT1_TCR1                    0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_TCR2                    0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_TCLKDIV                 0xFFC00908 /* SPORT1 Transmit Clock Divider */
+#define SPORT1_TFSDIV                  0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
+#define SPORT1_TX                      0xFFC00910 /* SPORT1 TX Data Register */
+#define SPORT1_RX                      0xFFC00918 /* SPORT1 RX Data Register */
+#define SPORT1_RCR1                    0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_RCR2                    0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_RCLKDIV                 0xFFC00928 /* SPORT1 Receive Clock Divider */
+#define SPORT1_RFSDIV                  0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
+#define SPORT1_STAT                    0xFFC00930 /* SPORT1 Status Register */
+#define SPORT1_CHNL                    0xFFC00934 /* SPORT1 Current Channel Register */
+#define SPORT1_MCMC1                   0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
+#define SPORT1_MCMC2                   0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
+#define SPORT1_MTCS0                   0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
+#define SPORT1_MTCS1                   0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
+#define SPORT1_MTCS2                   0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
+#define SPORT1_MTCS3                   0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
+#define SPORT1_MRCS0                   0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
+#define SPORT1_MRCS1                   0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
+#define SPORT1_MRCS2                   0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
+#define SPORT1_MRCS3                   0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
+#define EBIU_AMGCTL                    0xFFC00A00 /* Asynchronous Memory Global Control Register */
+#define EBIU_AMBCTL0                   0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
+#define EBIU_AMBCTL1                   0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
+#define EBIU_SDGCTL                    0xFFC00A10 /* SDRAM Global Control Register */
+#define EBIU_SDBCTL                    0xFFC00A14 /* SDRAM Bank Control Register */
+#define EBIU_SDRRC                     0xFFC00A18 /* SDRAM Refresh Rate Control Register */
+#define EBIU_SDSTAT                    0xFFC00A1C /* SDRAM Status Register */
+#define DMA0_NEXT_DESC_PTR             0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
+#define DMA0_START_ADDR                0xFFC00C04 /* DMA Channel 0 Start Address Register */
+#define DMA0_CONFIG                    0xFFC00C08 /* DMA Channel 0 Configuration Register */
+#define DMA0_X_COUNT                   0xFFC00C10 /* DMA Channel 0 X Count Register */
+#define DMA0_X_MODIFY                  0xFFC00C14 /* DMA Channel 0 X Modify Register */
+#define DMA0_Y_COUNT                   0xFFC00C18 /* DMA Channel 0 Y Count Register */
+#define DMA0_Y_MODIFY                  0xFFC00C1C /* DMA Channel 0 Y Modify Register */
+#define DMA0_CURR_DESC_PTR             0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
+#define DMA0_CURR_ADDR                 0xFFC00C24 /* DMA Channel 0 Current Address Register */
+#define DMA0_IRQ_STATUS                0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
+#define DMA0_PERIPHERAL_MAP            0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
+#define DMA0_CURR_X_COUNT              0xFFC00C30 /* DMA Channel 0 Current X Count Register */
+#define DMA0_CURR_Y_COUNT              0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
+#define DMA1_NEXT_DESC_PTR             0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
+#define DMA1_START_ADDR                0xFFC00C44 /* DMA Channel 1 Start Address Register */
+#define DMA1_CONFIG                    0xFFC00C48 /* DMA Channel 1 Configuration Register */
+#define DMA1_X_COUNT                   0xFFC00C50 /* DMA Channel 1 X Count Register */
+#define DMA1_X_MODIFY                  0xFFC00C54 /* DMA Channel 1 X Modify Register */
+#define DMA1_Y_COUNT                   0xFFC00C58 /* DMA Channel 1 Y Count Register */
+#define DMA1_Y_MODIFY                  0xFFC00C5C /* DMA Channel 1 Y Modify Register */
+#define DMA1_CURR_DESC_PTR             0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
+#define DMA1_CURR_ADDR                 0xFFC00C64 /* DMA Channel 1 Current Address Register */
+#define DMA1_IRQ_STATUS                0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
+#define DMA1_PERIPHERAL_MAP            0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
+#define DMA1_CURR_X_COUNT              0xFFC00C70 /* DMA Channel 1 Current X Count Register */
+#define DMA1_CURR_Y_COUNT              0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
+#define DMA2_NEXT_DESC_PTR             0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
+#define DMA2_START_ADDR                0xFFC00C84 /* DMA Channel 2 Start Address Register */
+#define DMA2_CONFIG                    0xFFC00C88 /* DMA Channel 2 Configuration Register */
+#define DMA2_X_COUNT                   0xFFC00C90 /* DMA Channel 2 X Count Register */
+#define DMA2_X_MODIFY                  0xFFC00C94 /* DMA Channel 2 X Modify Register */
+#define DMA2_Y_COUNT                   0xFFC00C98 /* DMA Channel 2 Y Count Register */
+#define DMA2_Y_MODIFY                  0xFFC00C9C /* DMA Channel 2 Y Modify Register */
+#define DMA2_CURR_DESC_PTR             0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
+#define DMA2_CURR_ADDR                 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
+#define DMA2_IRQ_STATUS                0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
+#define DMA2_PERIPHERAL_MAP            0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
+#define DMA2_CURR_X_COUNT              0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
+#define DMA2_CURR_Y_COUNT              0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
+#define DMA3_NEXT_DESC_PTR             0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
+#define DMA3_START_ADDR                0xFFC00CC4 /* DMA Channel 3 Start Address Register */
+#define DMA3_CONFIG                    0xFFC00CC8 /* DMA Channel 3 Configuration Register */
+#define DMA3_X_COUNT                   0xFFC00CD0 /* DMA Channel 3 X Count Register */
+#define DMA3_X_MODIFY                  0xFFC00CD4 /* DMA Channel 3 X Modify Register */
+#define DMA3_Y_COUNT                   0xFFC00CD8 /* DMA Channel 3 Y Count Register */
+#define DMA3_Y_MODIFY                  0xFFC00CDC /* DMA Channel 3 Y Modify Register */
+#define DMA3_CURR_DESC_PTR             0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
+#define DMA3_CURR_ADDR                 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
+#define DMA3_IRQ_STATUS                0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
+#define DMA3_PERIPHERAL_MAP            0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
+#define DMA3_CURR_X_COUNT              0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
+#define DMA3_CURR_Y_COUNT              0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
+#define DMA4_NEXT_DESC_PTR             0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
+#define DMA4_START_ADDR                0xFFC00D04 /* DMA Channel 4 Start Address Register */
+#define DMA4_CONFIG                    0xFFC00D08 /* DMA Channel 4 Configuration Register */
+#define DMA4_X_COUNT                   0xFFC00D10 /* DMA Channel 4 X Count Register */
+#define DMA4_X_MODIFY                  0xFFC00D14 /* DMA Channel 4 X Modify Register */
+#define DMA4_Y_COUNT                   0xFFC00D18 /* DMA Channel 4 Y Count Register */
+#define DMA4_Y_MODIFY                  0xFFC00D1C /* DMA Channel 4 Y Modify Register */
+#define DMA4_CURR_DESC_PTR             0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
+#define DMA4_CURR_ADDR                 0xFFC00D24 /* DMA Channel 4 Current Address Register */
+#define DMA4_IRQ_STATUS                0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
+#define DMA4_PERIPHERAL_MAP            0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
+#define DMA4_CURR_X_COUNT              0xFFC00D30 /* DMA Channel 4 Current X Count Register */
+#define DMA4_CURR_Y_COUNT              0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
+#define DMA5_NEXT_DESC_PTR             0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
+#define DMA5_START_ADDR                0xFFC00D44 /* DMA Channel 5 Start Address Register */
+#define DMA5_CONFIG                    0xFFC00D48 /* DMA Channel 5 Configuration Register */
+#define DMA5_X_COUNT                   0xFFC00D50 /* DMA Channel 5 X Count Register */
+#define DMA5_X_MODIFY                  0xFFC00D54 /* DMA Channel 5 X Modify Register */
+#define DMA5_Y_COUNT                   0xFFC00D58 /* DMA Channel 5 Y Count Register */
+#define DMA5_Y_MODIFY                  0xFFC00D5C /* DMA Channel 5 Y Modify Register */
+#define DMA5_CURR_DESC_PTR             0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
+#define DMA5_CURR_ADDR                 0xFFC00D64 /* DMA Channel 5 Current Address Register */
+#define DMA5_IRQ_STATUS                0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
+#define DMA5_PERIPHERAL_MAP            0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
+#define DMA5_CURR_X_COUNT              0xFFC00D70 /* DMA Channel 5 Current X Count Register */
+#define DMA5_CURR_Y_COUNT              0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
+#define DMA6_NEXT_DESC_PTR             0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
+#define DMA6_START_ADDR                0xFFC00D84 /* DMA Channel 6 Start Address Register */
+#define DMA6_CONFIG                    0xFFC00D88 /* DMA Channel 6 Configuration Register */
+#define DMA6_X_COUNT                   0xFFC00D90 /* DMA Channel 6 X Count Register */
+#define DMA6_X_MODIFY                  0xFFC00D94 /* DMA Channel 6 X Modify Register */
+#define DMA6_Y_COUNT                   0xFFC00D98 /* DMA Channel 6 Y Count Register */
+#define DMA6_Y_MODIFY                  0xFFC00D9C /* DMA Channel 6 Y Modify Register */
+#define DMA6_CURR_DESC_PTR             0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
+#define DMA6_CURR_ADDR                 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
+#define DMA6_IRQ_STATUS                0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
+#define DMA6_PERIPHERAL_MAP            0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
+#define DMA6_CURR_X_COUNT              0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
+#define DMA6_CURR_Y_COUNT              0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
+#define DMA7_NEXT_DESC_PTR             0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
+#define DMA7_START_ADDR                0xFFC00DC4 /* DMA Channel 7 Start Address Register */
+#define DMA7_CONFIG                    0xFFC00DC8 /* DMA Channel 7 Configuration Register */
+#define DMA7_X_COUNT                   0xFFC00DD0 /* DMA Channel 7 X Count Register */
+#define DMA7_X_MODIFY                  0xFFC00DD4 /* DMA Channel 7 X Modify Register */
+#define DMA7_Y_COUNT                   0xFFC00DD8 /* DMA Channel 7 Y Count Register */
+#define DMA7_Y_MODIFY                  0xFFC00DDC /* DMA Channel 7 Y Modify Register */
+#define DMA7_CURR_DESC_PTR             0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
+#define DMA7_CURR_ADDR                 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
+#define DMA7_IRQ_STATUS                0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
+#define DMA7_PERIPHERAL_MAP            0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
+#define DMA7_CURR_X_COUNT              0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
+#define DMA7_CURR_Y_COUNT              0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
+#define DMA8_NEXT_DESC_PTR             0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
+#define DMA8_START_ADDR                0xFFC00E04 /* DMA Channel 8 Start Address Register */
+#define DMA8_CONFIG                    0xFFC00E08 /* DMA Channel 8 Configuration Register */
+#define DMA8_X_COUNT                   0xFFC00E10 /* DMA Channel 8 X Count Register */
+#define DMA8_X_MODIFY                  0xFFC00E14 /* DMA Channel 8 X Modify Register */
+#define DMA8_Y_COUNT                   0xFFC00E18 /* DMA Channel 8 Y Count Register */
+#define DMA8_Y_MODIFY                  0xFFC00E1C /* DMA Channel 8 Y Modify Register */
+#define DMA8_CURR_DESC_PTR             0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
+#define DMA8_CURR_ADDR                 0xFFC00E24 /* DMA Channel 8 Current Address Register */
+#define DMA8_IRQ_STATUS                0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
+#define DMA8_PERIPHERAL_MAP            0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
+#define DMA8_CURR_X_COUNT              0xFFC00E30 /* DMA Channel 8 Current X Count Register */
+#define DMA8_CURR_Y_COUNT              0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
+#define DMA9_NEXT_DESC_PTR             0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
+#define DMA9_START_ADDR                0xFFC00E44 /* DMA Channel 9 Start Address Register */
+#define DMA9_CONFIG                    0xFFC00E48 /* DMA Channel 9 Configuration Register */
+#define DMA9_X_COUNT                   0xFFC00E50 /* DMA Channel 9 X Count Register */
+#define DMA9_X_MODIFY                  0xFFC00E54 /* DMA Channel 9 X Modify Register */
+#define DMA9_Y_COUNT                   0xFFC00E58 /* DMA Channel 9 Y Count Register */
+#define DMA9_Y_MODIFY                  0xFFC00E5C /* DMA Channel 9 Y Modify Register */
+#define DMA9_CURR_DESC_PTR             0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
+#define DMA9_CURR_ADDR                 0xFFC00E64 /* DMA Channel 9 Current Address Register */
+#define DMA9_IRQ_STATUS                0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
+#define DMA9_PERIPHERAL_MAP            0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
+#define DMA9_CURR_X_COUNT              0xFFC00E70 /* DMA Channel 9 Current X Count Register */
+#define DMA9_CURR_Y_COUNT              0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
+#define DMA10_NEXT_DESC_PTR            0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
+#define DMA10_START_ADDR               0xFFC00E84 /* DMA Channel 10 Start Address Register */
+#define DMA10_CONFIG                   0xFFC00E88 /* DMA Channel 10 Configuration Register */
+#define DMA10_X_COUNT                  0xFFC00E90 /* DMA Channel 10 X Count Register */
+#define DMA10_X_MODIFY                 0xFFC00E94 /* DMA Channel 10 X Modify Register */
+#define DMA10_Y_COUNT                  0xFFC00E98 /* DMA Channel 10 Y Count Register */
+#define DMA10_Y_MODIFY                 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
+#define DMA10_CURR_DESC_PTR            0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
+#define DMA10_CURR_ADDR                0xFFC00EA4 /* DMA Channel 10 Current Address Register */
+#define DMA10_IRQ_STATUS               0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
+#define DMA10_PERIPHERAL_MAP           0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
+#define DMA10_CURR_X_COUNT             0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
+#define DMA10_CURR_Y_COUNT             0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
+#define DMA11_NEXT_DESC_PTR            0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
+#define DMA11_START_ADDR               0xFFC00EC4 /* DMA Channel 11 Start Address Register */
+#define DMA11_CONFIG                   0xFFC00EC8 /* DMA Channel 11 Configuration Register */
+#define DMA11_X_COUNT                  0xFFC00ED0 /* DMA Channel 11 X Count Register */
+#define DMA11_X_MODIFY                 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
+#define DMA11_Y_COUNT                  0xFFC00ED8 /* DMA Channel 11 Y Count Register */
+#define DMA11_Y_MODIFY                 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
+#define DMA11_CURR_DESC_PTR            0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
+#define DMA11_CURR_ADDR                0xFFC00EE4 /* DMA Channel 11 Current Address Register */
+#define DMA11_IRQ_STATUS               0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
+#define DMA11_PERIPHERAL_MAP           0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
+#define DMA11_CURR_X_COUNT             0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
+#define DMA11_CURR_Y_COUNT             0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
+#define MDMA_S0_NEXT_DESC_PTR          0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA_S0_START_ADDR             0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
+#define MDMA_S0_CONFIG                 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
+#define MDMA_S0_X_COUNT                0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
+#define MDMA_S0_X_MODIFY               0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
+#define MDMA_S0_Y_COUNT                0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
+#define MDMA_S0_Y_MODIFY               0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
+#define MDMA_S0_CURR_DESC_PTR          0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA_S0_CURR_ADDR              0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
+#define MDMA_S0_IRQ_STATUS             0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
+#define MDMA_S0_PERIPHERAL_MAP         0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
+#define MDMA_S0_CURR_X_COUNT           0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
+#define MDMA_S0_CURR_Y_COUNT           0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
+#define MDMA_D0_NEXT_DESC_PTR          0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA_D0_START_ADDR             0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
+#define MDMA_D0_CONFIG                 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
+#define MDMA_D0_X_COUNT                0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
+#define MDMA_D0_X_MODIFY               0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
+#define MDMA_D0_Y_COUNT                0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
+#define MDMA_D0_Y_MODIFY               0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
+#define MDMA_D0_CURR_DESC_PTR          0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
+#define MDMA_D0_CURR_ADDR              0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
+#define MDMA_D0_IRQ_STATUS             0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
+#define MDMA_D0_PERIPHERAL_MAP         0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
+#define MDMA_D0_CURR_X_COUNT           0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
+#define MDMA_D0_CURR_Y_COUNT           0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
+#define MDMA_S1_NEXT_DESC_PTR          0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA_S1_START_ADDR             0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
+#define MDMA_S1_CONFIG                 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
+#define MDMA_S1_X_COUNT                0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
+#define MDMA_S1_X_MODIFY               0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
+#define MDMA_S1_Y_COUNT                0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
+#define MDMA_S1_Y_MODIFY               0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
+#define MDMA_S1_CURR_DESC_PTR          0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA_S1_CURR_ADDR              0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
+#define MDMA_S1_IRQ_STATUS             0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
+#define MDMA_S1_PERIPHERAL_MAP         0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
+#define MDMA_S1_CURR_X_COUNT           0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
+#define MDMA_S1_CURR_Y_COUNT           0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
+#define MDMA_D1_NEXT_DESC_PTR          0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA_D1_START_ADDR             0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
+#define MDMA_D1_CONFIG                 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
+#define MDMA_D1_X_COUNT                0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
+#define MDMA_D1_X_MODIFY               0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
+#define MDMA_D1_Y_COUNT                0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
+#define MDMA_D1_Y_MODIFY               0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
+#define MDMA_D1_CURR_DESC_PTR          0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
+#define MDMA_D1_CURR_ADDR              0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
+#define MDMA_D1_IRQ_STATUS             0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
+#define MDMA_D1_PERIPHERAL_MAP         0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
+#define MDMA_D1_CURR_X_COUNT           0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
+#define MDMA_D1_CURR_Y_COUNT           0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
+#define PPI_CONTROL                    0xFFC01000 /* PPI Control Register */
+#define PPI_STATUS                     0xFFC01004 /* PPI Status Register */
+#define PPI_COUNT                      0xFFC01008 /* PPI Transfer Count Register */
+#define PPI_DELAY                      0xFFC0100C /* PPI Delay Count Register */
+#define PPI_FRAME                      0xFFC01010 /* PPI Frame Length Register */
+#define TWI_CLKDIV                     0xFFC01400 /* Serial Clock Divider Register */
+#define TWI_CONTROL                    0xFFC01404 /* TWI Control Register */
+#define TWI_SLAVE_CTL                  0xFFC01408 /* Slave Mode Control Register */
+#define TWI_SLAVE_STAT                 0xFFC0140C /* Slave Mode Status Register */
+#define TWI_SLAVE_ADDR                 0xFFC01410 /* Slave Mode Address Register */
+#define TWI_MASTER_CTL                 0xFFC01414 /* Master Mode Control Register */
+#define TWI_MASTER_STAT                0xFFC01418 /* Master Mode Status Register */
+#define TWI_MASTER_ADDR                0xFFC0141C /* Master Mode Address Register */
+#define TWI_INT_STAT                   0xFFC01420 /* TWI Interrupt Status Register */
+#define TWI_INT_MASK                   0xFFC01424 /* TWI Master Interrupt Mask Register */
+#define TWI_FIFO_CTL                   0xFFC01428 /* FIFO Control Register */
+#define TWI_FIFO_STAT                  0xFFC0142C /* FIFO Status Register */
+#define TWI_XMT_DATA8                  0xFFC01480 /* FIFO Transmit Data Single Byte Register */
+#define TWI_XMT_DATA16                 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
+#define TWI_RCV_DATA8                  0xFFC01488 /* FIFO Receive Data Single Byte Register */
+#define TWI_RCV_DATA16                 0xFFC0148C /* FIFO Receive Data Double Byte Register */
+#define PORTGIO                        0xFFC01500 /* Port G I/O Pin State Specify Register */
+#define PORTGIO_CLEAR                  0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
+#define PORTGIO_SET                    0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
+#define PORTGIO_TOGGLE                 0xFFC0150C /* Port G I/O Pin State Toggle Register */
+#define PORTGIO_MASKA                  0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
+#define PORTGIO_MASKA_CLEAR            0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
+#define PORTGIO_MASKA_SET              0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
+#define PORTGIO_MASKA_TOGGLE           0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
+#define PORTGIO_MASKB                  0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
+#define PORTGIO_MASKB_CLEAR            0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
+#define PORTGIO_MASKB_SET              0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
+#define PORTGIO_MASKB_TOGGLE           0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
+#define PORTGIO_DIR                    0xFFC01530 /* Port G I/O Direction Register */
+#define PORTGIO_POLAR                  0xFFC01534 /* Port G I/O Source Polarity Register */
+#define PORTGIO_EDGE                   0xFFC01538 /* Port G I/O Source Sensitivity Register */
+#define PORTGIO_BOTH                   0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
+#define PORTGIO_INEN                   0xFFC01540 /* Port G I/O Input Enable Register */
+#define PORTHIO                        0xFFC01700 /* Port H I/O Pin State Specify Register */
+#define PORTHIO_CLEAR                  0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
+#define PORTHIO_SET                    0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
+#define PORTHIO_TOGGLE                 0xFFC0170C /* Port H I/O Pin State Toggle Register */
+#define PORTHIO_MASKA                  0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
+#define PORTHIO_MASKA_CLEAR            0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
+#define PORTHIO_MASKA_SET              0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
+#define PORTHIO_MASKA_TOGGLE           0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
+#define PORTHIO_MASKB                  0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
+#define PORTHIO_MASKB_CLEAR            0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
+#define PORTHIO_MASKB_SET              0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
+#define PORTHIO_MASKB_TOGGLE           0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
+#define PORTHIO_DIR                    0xFFC01730 /* Port H I/O Direction Register */
+#define PORTHIO_POLAR                  0xFFC01734 /* Port H I/O Source Polarity Register */
+#define PORTHIO_EDGE                   0xFFC01738 /* Port H I/O Source Sensitivity Register */
+#define PORTHIO_BOTH                   0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
+#define PORTHIO_INEN                   0xFFC01740 /* Port H I/O Input Enable Register */
+#define UART1_THR                      0xFFC02000 /* Transmit Holding register */
+#define UART1_RBR                      0xFFC02000 /* Receive Buffer register */
+#define UART1_DLL                      0xFFC02000 /* Divisor Latch (Low-Byte) */
+#define UART1_IER                      0xFFC02004 /* Interrupt Enable Register */
+#define UART1_DLH                      0xFFC02004 /* Divisor Latch (High-Byte) */
+#define UART1_IIR                      0xFFC02008 /* Interrupt Identification Register */
+#define UART1_LCR                      0xFFC0200C /* Line Control Register */
+#define UART1_MCR                      0xFFC02010 /* Modem Control Register */
+#define UART1_LSR                      0xFFC02014 /* Line Status Register */
+#define UART1_MSR                      0xFFC02018 /* Modem Status Register */
+#define UART1_SCR                      0xFFC0201C /* SCR Scratch Register */
+#define UART1_GCTL                     0xFFC02024 /* Global Control Register */
+#define PORTF_FER                      0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
+#define PORTG_FER                      0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
+#define PORTH_FER                      0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
+#define HMDMA0_CONTROL                 0xFFC03300 /* Handshake MDMA0 Control Register */
+#define HMDMA0_ECINIT                  0xFFC03304 /* HMDMA0 Initial Edge Count Register */
+#define HMDMA0_BCINIT                  0xFFC03308 /* HMDMA0 Initial Block Count Register */
+#define HMDMA0_ECURGENT                0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
+#define HMDMA0_ECOVERFLOW              0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
+#define HMDMA0_ECOUNT                  0xFFC03314 /* HMDMA0 Current Edge Count Register */
+#define HMDMA0_BCOUNT                  0xFFC03318 /* HMDMA0 Current Block Count Register */
+#define HMDMA1_CONTROL                 0xFFC03340 /* Handshake MDMA1 Control Register */
+#define HMDMA1_ECINIT                  0xFFC03344 /* HMDMA1 Initial Edge Count Register */
+#define HMDMA1_BCINIT                  0xFFC03348 /* HMDMA1 Initial Block Count Register */
+#define HMDMA1_ECURGENT                0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
+#define HMDMA1_ECOVERFLOW              0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
+#define HMDMA1_ECOUNT                  0xFFC03354 /* HMDMA1 Current Edge Count Register */
+#define HMDMA1_BCOUNT                  0xFFC03358 /* HMDMA1 Current Block Count Register */
+#define PORTF_MUX                      0xFFC03210 /* Port F mux control */
+#define PORTG_MUX                      0xFFC03214 /* Port G mux control */
+#define PORTH_MUX                      0xFFC03218 /* Port H mux control */
+#define PORTF_DRIVE                    0xFFC03220 /* Port F drive strength control */
+#define PORTG_DRIVE                    0xFFC03224 /* Port G drive strength control */
+#define PORTH_DRIVE                    0xFFC03228 /* Port H drive strength control */
+#define PORTF_SLEW                     0xFFC03230 /* Port F slew control */
+#define PORTG_SLEW                     0xFFC03234 /* Port G slew control */
+#define PORTH_SLEW                     0xFFC03238 /* Port H slew control */
+#define PORTF_HYSTERESIS               0xFFC03240 /* Port F Schmitt trigger control */
+#define PORTG_HYSTERESIS               0xFFC03244 /* Port G Schmitt trigger control */
+#define PORTH_HYSTERESIS               0xFFC03248 /* Port H Schmitt trigger control */
+#define NONGPIO_DRIVE                  0xFFC03280 /* Non-GPIO Port drive strength control */
+#define NONGPIO_SLEW                   0xFFC03284 /* Non-GPIO Port slew control */
+#define NONGPIO_HYSTERESIS             0xFFC03288 /* Non-GPIO Port Schmitt trigger control */
+#define HOST_CONTROL                   0xFFC03400 /* HOST Control Register */
+#define HOST_STATUS                    0xFFC03404 /* HOST Status Register */
+#define HOST_TIMEOUT                   0xFFC03408 /* HOST Acknowledge Mode Timeout Register */
+#define CNT_CONFIG                     0xFFC03500 /* Configuration/Control Register */
+#define CNT_IMASK                      0xFFC03504 /* Interrupt Mask Register */
+#define CNT_STATUS                     0xFFC03508 /* Status Register */
+#define CNT_COMMAND                    0xFFC0350C /* Command Register */
+#define CNT_DEBOUNCE                   0xFFC03510 /* Debounce Prescaler Register */
+#define CNT_COUNTER                    0xFFC03514 /* Counter Register */
+#define CNT_MAX                        0xFFC03518 /* Maximal Count Boundary Value Register */
+#define CNT_MIN                        0xFFC0351C /* Minimal Count Boundary Value Register */
+#define OTP_CONTROL                    0xFFC03600 /* OTP/Fuse Control Register */
+#define OTP_BEN                        0xFFC03604 /* OTP/Fuse Byte Enable */
+#define OTP_STATUS                     0xFFC03608 /* OTP/Fuse Status */
+#define OTP_TIMING                     0xFFC0360C /* OTP/Fuse Access Timing */
+#define SECURE_SYSSWT                  0xFFC03620 /* Secure System Switches */
+#define SECURE_CONTROL                 0xFFC03624 /* Secure Control */
+#define SECURE_STATUS                  0xFFC03628 /* Secure Status */
+#define OTP_DATA0                      0xFFC03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA1                      0xFFC03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA2                      0xFFC03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA3                      0xFFC0368C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define NFC_CTL                        0xFFC03700 /* NAND Control Register */
+#define NFC_STAT                       0xFFC03704 /* NAND Status Register */
+#define NFC_IRQSTAT                    0xFFC03708 /* NAND Interrupt Status Register */
+#define NFC_IRQMASK                    0xFFC0370C /* NAND Interrupt Mask Register */
+#define NFC_ECC0                       0xFFC03710 /* NAND ECC Register 0 */
+#define NFC_ECC1                       0xFFC03714 /* NAND ECC Register 1 */
+#define NFC_ECC2                       0xFFC03718 /* NAND ECC Register 2 */
+#define NFC_ECC3                       0xFFC0371C /* NAND ECC Register 3 */
+#define NFC_COUNT                      0xFFC03720 /* NAND ECC Count Register */
+#define NFC_RST                        0xFFC03724 /* NAND ECC Reset Register */
+#define NFC_PGCTL                      0xFFC03728 /* NAND Page Control Register */
+#define NFC_READ                       0xFFC0372C /* NAND Read Data Register */
+#define NFC_ADDR                       0xFFC03740 /* NAND Address Register */
+#define NFC_CMD                        0xFFC03744 /* NAND Command Register */
+#define NFC_DATA_WR                    0xFFC03748 /* NAND Data Write Register */
+#define NFC_DATA_RD                    0xFFC0374C /* NAND Data Read Register */
+#define TBUFCTL                        0xFFE06000 /* Trace Buffer Control Register */
+#define TBUFSTAT                       0xFFE06004 /* Trace Buffer Status Register */
+#define TBUF                           0xFFE06100 /* Trace Buffer */
+#define PFCTL                          0xFFE08000
+#define PFCNTR0                        0xFFE08100
+#define PFCNTR1                        0xFFE08104
+#define DMA_TC_CNT                     0xFFC00B0C
+#define DMA_TC_PER                     0xFFC00B10
+
+#endif /* __BFIN_DEF_ADSP_EDN_BF52x_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h
new file mode 100644
index 000000000..987cc862c
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h
@@ -0,0 +1,341 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF522_proc__
+#define __BFIN_CDEF_ADSP_BF522_proc__
+
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
+#include "ADSP-EDN-BF52x-extended_cdef.h"
+
+#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
+#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
+#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
+#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */
+#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
+#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
+#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
+#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
+#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
+#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
+#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
+#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
+#define pCHIPID                        ((uint32_t volatile *)CHIPID)
+#define bfin_read_CHIPID()             bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
+#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
+#define bfin_read_SWRST()              bfin_read16(SWRST)
+#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
+#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
+#define bfin_read_SYSCR()              bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
+#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
+#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
+#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
+#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
+#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
+#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
+#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
+#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
+#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
+#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
+#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
+#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
+#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
+#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
+#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
+#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
+#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
+#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
+#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
+#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
+#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
+#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
+#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
+#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
+#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
+#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
+#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
+#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
+#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
+#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
+#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
+#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
+#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
+#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
+#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
+#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
+#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
+#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
+#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
+#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
+#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
+#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
+#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
+#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
+#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
+#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
+#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
+#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
+#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
+#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
+#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
+#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
+#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
+#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
+#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
+#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
+#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
+#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
+#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
+#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
+#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
+#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
+#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
+#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
+#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
+#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
+#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
+#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
+#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
+#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
+#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
+#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
+#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
+#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
+#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
+#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
+#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
+#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
+#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
+#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
+#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
+#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
+#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
+#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
+#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
+#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
+#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
+#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
+#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
+#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
+#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
+#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
+#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
+#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
+#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
+#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
+#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
+#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
+#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
+#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
+#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
+#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
+#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
+#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
+#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
+#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
+#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
+#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
+#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
+#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
+#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
+#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
+#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
+#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
+#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
+#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
+#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
+#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
+#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
+#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
+#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
+#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
+#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
+#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
+#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
+#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
+#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
+#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
+#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
+#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
+#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
+#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
+#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
+#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
+#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
+#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
+#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
+#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
+#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
+#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
+#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
+#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
+#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
+#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
+#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
+#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
+#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
+#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
+#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
+#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
+#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
+#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
+#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
+#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
+#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
+#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
+#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
+#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
+#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
+#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
+#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
+#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
+#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
+#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
+#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
+#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
+#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
+#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
+#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
+#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
+#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
+#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
+#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
+#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
+#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
+#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
+#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
+#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
+#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
+#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
+#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
+#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
+#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
+#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
+#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
+#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
+#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
+#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
+#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
+#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
+#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
+#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
+#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
+#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
+#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
+#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
+#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
+#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
+#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
+#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
+#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
+#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
+#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
+#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
+#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
+#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
+#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
+#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
+#define bfin_read_EVT0()               bfin_readPTR(EVT0)
+#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
+#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
+#define bfin_read_EVT1()               bfin_readPTR(EVT1)
+#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
+#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
+#define bfin_read_EVT2()               bfin_readPTR(EVT2)
+#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
+#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
+#define bfin_read_EVT3()               bfin_readPTR(EVT3)
+#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
+#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
+#define bfin_read_EVT4()               bfin_readPTR(EVT4)
+#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
+#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
+#define bfin_read_EVT5()               bfin_readPTR(EVT5)
+#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
+#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
+#define bfin_read_EVT6()               bfin_readPTR(EVT6)
+#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
+#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
+#define bfin_read_EVT7()               bfin_readPTR(EVT7)
+#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
+#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
+#define bfin_read_EVT8()               bfin_readPTR(EVT8)
+#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
+#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
+#define bfin_read_EVT9()               bfin_readPTR(EVT9)
+#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
+#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
+#define bfin_read_EVT10()              bfin_readPTR(EVT10)
+#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
+#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
+#define bfin_read_EVT11()              bfin_readPTR(EVT11)
+#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
+#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
+#define bfin_read_EVT12()              bfin_readPTR(EVT12)
+#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
+#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
+#define bfin_read_EVT13()              bfin_readPTR(EVT13)
+#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
+#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
+#define bfin_read_EVT14()              bfin_readPTR(EVT14)
+#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
+#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
+#define bfin_read_EVT15()              bfin_readPTR(EVT15)
+#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
+#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
+#define bfin_read_ILAT()               bfin_read32(ILAT)
+#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
+#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
+#define bfin_read_IMASK()              bfin_read32(IMASK)
+#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
+#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
+#define bfin_read_IPEND()              bfin_read32(IPEND)
+#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
+#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
+#define bfin_read_IPRIO()              bfin_read32(IPRIO)
+#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
+#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
+#define bfin_read_TCNTL()              bfin_read32(TCNTL)
+#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
+#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
+#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
+#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
+#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
+#define bfin_read_TSCALE()             bfin_read32(TSCALE)
+#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
+#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
+#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
+#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
+
+#endif /* __BFIN_CDEF_ADSP_BF522_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF522_def.h b/arch/blackfin/include/asm/mach-bf527/BF522_def.h
new file mode 100644
index 000000000..bc05029aa
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf527/BF522_def.h
@@ -0,0 +1,123 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF522_proc__
+#define __BFIN_DEF_ADSP_BF522_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#include "ADSP-EDN-BF52x-extended_def.h"
+
+#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
+#define PLL_DIV                        0xFFC00004 /* PLL Divide Register */
+#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
+#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
+#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
+#define CHIPID                         0xFFC00014
+#define SWRST                          0xFFC00100 /* Software Reset Register */
+#define SYSCR                          0xFFC00104 /* System Configuration register */
+#define SRAM_BASE_ADDR                 0xFFE00000 /* SRAM Base Address (Read Only) */
+#define DMEM_CONTROL                   0xFFE00004 /* Data memory control */
+#define DCPLB_STATUS                   0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
+#define DCPLB_FAULT_ADDR               0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define DCPLB_ADDR0                    0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
+#define DCPLB_ADDR1                    0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
+#define DCPLB_ADDR2                    0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
+#define DCPLB_ADDR3                    0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
+#define DCPLB_ADDR4                    0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
+#define DCPLB_ADDR5                    0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
+#define DCPLB_ADDR6                    0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
+#define DCPLB_ADDR7                    0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
+#define DCPLB_ADDR8                    0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
+#define DCPLB_ADDR9                    0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
+#define DCPLB_ADDR10                   0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
+#define DCPLB_ADDR11                   0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
+#define DCPLB_ADDR12                   0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
+#define DCPLB_ADDR13                   0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
+#define DCPLB_ADDR14                   0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
+#define DCPLB_ADDR15                   0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
+#define DCPLB_DATA0                    0xFFE00200 /* Data Cache 0 Status */
+#define DCPLB_DATA1                    0xFFE00204 /* Data Cache 1 Status */
+#define DCPLB_DATA2                    0xFFE00208 /* Data Cache 2 Status */
+#define DCPLB_DATA3                    0xFFE0020C /* Data Cache 3 Status */
+#define DCPLB_DATA4                    0xFFE00210 /* Data Cache 4 Status */
+#define DCPLB_DATA5                    0xFFE00214 /* Data Cache 5 Status */
+#define DCPLB_DATA6                    0xFFE00218 /* Data Cache 6 Status */
+#define DCPLB_DATA7                    0xFFE0021C /* Data Cache 7 Status */
+#define DCPLB_DATA8                    0xFFE00220 /* Data Cache 8 Status */
+#define DCPLB_DATA9                    0xFFE00224 /* Data Cache 9 Status */
+#define DCPLB_DATA10                   0xFFE00228 /* Data Cache 10 Status */
+#define DCPLB_DATA11                   0xFFE0022C /* Data Cache 11 Status */
+#define DCPLB_DATA12                   0xFFE00230 /* Data Cache 12 Status */
+#define DCPLB_DATA13                   0xFFE00234 /* Data Cache 13 Status */
+#define DCPLB_DATA14                   0xFFE00238 /* Data Cache 14 Status */
+#define DCPLB_DATA15                   0xFFE0023C /* Data Cache 15 Status */
+#define DTEST_COMMAND                  0xFFE00300 /* Data Test Command Register */
+#define DTEST_DATA0                    0xFFE00400 /* Data Test Data Register */
+#define DTEST_DATA1                    0xFFE00404 /* Data Test Data Register */
+#define IMEM_CONTROL                   0xFFE01004 /* Instruction Memory Control */
+#define ICPLB_STATUS                   0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define ICPLB_FAULT_ADDR               0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define ICPLB_ADDR0                    0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define ICPLB_ADDR1                    0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define ICPLB_ADDR2                    0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define ICPLB_ADDR3                    0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define ICPLB_ADDR4                    0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define ICPLB_ADDR5                    0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define ICPLB_ADDR6                    0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define ICPLB_ADDR7                    0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define ICPLB_ADDR8                    0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define ICPLB_ADDR9                    0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define ICPLB_ADDR10                   0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define ICPLB_ADDR11                   0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define ICPLB_ADDR12                   0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define ICPLB_ADDR13                   0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define ICPLB_ADDR14                   0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define ICPLB_ADDR15                   0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define ICPLB_DATA0                    0xFFE01200 /* Instruction Cache 0 Status */
+#define ICPLB_DATA1                    0xFFE01204 /* Instruction Cache 1 Status */
+#define ICPLB_DATA2                    0xFFE01208 /* Instruction Cache 2 Status */
+#define ICPLB_DATA3                    0xFFE0120C /* Instruction Cache 3 Status */
+#define ICPLB_DATA4                    0xFFE01210 /* Instruction Cache 4 Status */
+#define ICPLB_DATA5                    0xFFE01214 /* Instruction Cache 5 Status */
+#define ICPLB_DATA6                    0xFFE01218 /* Instruction Cache 6 Status */
+#define ICPLB_DATA7                    0xFFE0121C /* Instruction Cache 7 Status */
+#define ICPLB_DATA8                    0xFFE01220 /* Instruction Cache 8 Status */
+#define ICPLB_DATA9                    0xFFE01224 /* Instruction Cache 9 Status */
+#define ICPLB_DATA10                   0xFFE01228 /* Instruction Cache 10 Status */
+#define ICPLB_DATA11                   0xFFE0122C /* Instruction Cache 11 Status */
+#define ICPLB_DATA12                   0xFFE01230 /* Instruction Cache 12 Status */
+#define ICPLB_DATA13                   0xFFE01234 /* Instruction Cache 13 Status */
+#define ICPLB_DATA14                   0xFFE01238 /* Instruction Cache 14 Status */
+#define ICPLB_DATA15                   0xFFE0123C /* Instruction Cache 15 Status */
+#define ITEST_COMMAND                  0xFFE01300 /* Instruction Test Command Register */
+#define ITEST_DATA0                    0xFFE01400 /* Instruction Test Data Register */
+#define ITEST_DATA1                    0xFFE01404 /* Instruction Test Data Register */
+#define EVT0                           0xFFE02000 /* Event Vector 0 ESR Address */
+#define EVT1                           0xFFE02004 /* Event Vector 1 ESR Address */
+#define EVT2                           0xFFE02008 /* Event Vector 2 ESR Address */
+#define EVT3                           0xFFE0200C /* Event Vector 3 ESR Address */
+#define EVT4                           0xFFE02010 /* Event Vector 4 ESR Address */
+#define EVT5                           0xFFE02014 /* Event Vector 5 ESR Address */
+#define EVT6                           0xFFE02018 /* Event Vector 6 ESR Address */
+#define EVT7                           0xFFE0201C /* Event Vector 7 ESR Address */
+#define EVT8                           0xFFE02020 /* Event Vector 8 ESR Address */
+#define EVT9                           0xFFE02024 /* Event Vector 9 ESR Address */
+#define EVT10                          0xFFE02028 /* Event Vector 10 ESR Address */
+#define EVT11                          0xFFE0202C /* Event Vector 11 ESR Address */
+#define EVT12                          0xFFE02030 /* Event Vector 12 ESR Address */
+#define EVT13                          0xFFE02034 /* Event Vector 13 ESR Address */
+#define EVT14                          0xFFE02038 /* Event Vector 14 ESR Address */
+#define EVT15                          0xFFE0203C /* Event Vector 15 ESR Address */
+#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
+#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
+#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
+#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
+#define TCNTL                          0xFFE03000 /* Core Timer Control Register */
+#define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
+#define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
+#define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
+
+#endif /* __BFIN_DEF_ADSP_BF522_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h
new file mode 100644
index 000000000..390f3dc16
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h
@@ -0,0 +1,341 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF523_proc__
+#define __BFIN_CDEF_ADSP_BF523_proc__
+
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
+#include "ADSP-EDN-BF52x-extended_cdef.h"
+
+#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
+#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
+#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
+#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */
+#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
+#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
+#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
+#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
+#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
+#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
+#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
+#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
+#define pCHIPID                        ((uint32_t volatile *)CHIPID)
+#define bfin_read_CHIPID()             bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
+#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
+#define bfin_read_SWRST()              bfin_read16(SWRST)
+#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
+#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
+#define bfin_read_SYSCR()              bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
+#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
+#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
+#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
+#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
+#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
+#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
+#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
+#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
+#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
+#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
+#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
+#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
+#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
+#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
+#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
+#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
+#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
+#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
+#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
+#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
+#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
+#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
+#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
+#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
+#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
+#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
+#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
+#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
+#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
+#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
+#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
+#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
+#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
+#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
+#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
+#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
+#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
+#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
+#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
+#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
+#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
+#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
+#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
+#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
+#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
+#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
+#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
+#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
+#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
+#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
+#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
+#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
+#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
+#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
+#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
+#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
+#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
+#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
+#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
+#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
+#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
+#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
+#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
+#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
+#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
+#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
+#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
+#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
+#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
+#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
+#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
+#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
+#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
+#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
+#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
+#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
+#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
+#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
+#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
+#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
+#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
+#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
+#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
+#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
+#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
+#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
+#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
+#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
+#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
+#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
+#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
+#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
+#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
+#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
+#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
+#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
+#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
+#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
+#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
+#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
+#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
+#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
+#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
+#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
+#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
+#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
+#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
+#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
+#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
+#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
+#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
+#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
+#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
+#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
+#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
+#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
+#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
+#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
+#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
+#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
+#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
+#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
+#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
+#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
+#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
+#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
+#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
+#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
+#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
+#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
+#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
+#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
+#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
+#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
+#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
+#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
+#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
+#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
+#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
+#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
+#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
+#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
+#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
+#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
+#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
+#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
+#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
+#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
+#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
+#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
+#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
+#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
+#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
+#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
+#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
+#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
+#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
+#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
+#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
+#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
+#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
+#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
+#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
+#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
+#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
+#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
+#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
+#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
+#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
+#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
+#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
+#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
+#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
+#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
+#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
+#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
+#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
+#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
+#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
+#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
+#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
+#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
+#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
+#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
+#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
+#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
+#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
+#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
+#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
+#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
+#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
+#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
+#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
+#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
+#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
+#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
+#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
+#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
+#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
+#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
+#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
+#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
+#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
+#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
+#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
+#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
+#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
+#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
+#define bfin_read_EVT0()               bfin_readPTR(EVT0)
+#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
+#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
+#define bfin_read_EVT1()               bfin_readPTR(EVT1)
+#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
+#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
+#define bfin_read_EVT2()               bfin_readPTR(EVT2)
+#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
+#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
+#define bfin_read_EVT3()               bfin_readPTR(EVT3)
+#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
+#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
+#define bfin_read_EVT4()               bfin_readPTR(EVT4)
+#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
+#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
+#define bfin_read_EVT5()               bfin_readPTR(EVT5)
+#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
+#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
+#define bfin_read_EVT6()               bfin_readPTR(EVT6)
+#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
+#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
+#define bfin_read_EVT7()               bfin_readPTR(EVT7)
+#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
+#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
+#define bfin_read_EVT8()               bfin_readPTR(EVT8)
+#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
+#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
+#define bfin_read_EVT9()               bfin_readPTR(EVT9)
+#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
+#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
+#define bfin_read_EVT10()              bfin_readPTR(EVT10)
+#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
+#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
+#define bfin_read_EVT11()              bfin_readPTR(EVT11)
+#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
+#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
+#define bfin_read_EVT12()              bfin_readPTR(EVT12)
+#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
+#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
+#define bfin_read_EVT13()              bfin_readPTR(EVT13)
+#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
+#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
+#define bfin_read_EVT14()              bfin_readPTR(EVT14)
+#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
+#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
+#define bfin_read_EVT15()              bfin_readPTR(EVT15)
+#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
+#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
+#define bfin_read_ILAT()               bfin_read32(ILAT)
+#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
+#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
+#define bfin_read_IMASK()              bfin_read32(IMASK)
+#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
+#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
+#define bfin_read_IPEND()              bfin_read32(IPEND)
+#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
+#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
+#define bfin_read_IPRIO()              bfin_read32(IPRIO)
+#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
+#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
+#define bfin_read_TCNTL()              bfin_read32(TCNTL)
+#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
+#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
+#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
+#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
+#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
+#define bfin_read_TSCALE()             bfin_read32(TSCALE)
+#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
+#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
+#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
+#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
+
+#endif /* __BFIN_CDEF_ADSP_BF523_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF523_def.h b/arch/blackfin/include/asm/mach-bf527/BF523_def.h
new file mode 100644
index 000000000..c27fd646b
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf527/BF523_def.h
@@ -0,0 +1,123 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF523_proc__
+#define __BFIN_DEF_ADSP_BF523_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#include "ADSP-EDN-BF52x-extended_def.h"
+
+#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
+#define PLL_DIV                        0xFFC00004 /* PLL Divide Register */
+#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
+#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
+#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
+#define CHIPID                         0xFFC00014
+#define SWRST                          0xFFC00100 /* Software Reset Register */
+#define SYSCR                          0xFFC00104 /* System Configuration register */
+#define SRAM_BASE_ADDR                 0xFFE00000 /* SRAM Base Address (Read Only) */
+#define DMEM_CONTROL                   0xFFE00004 /* Data memory control */
+#define DCPLB_STATUS                   0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
+#define DCPLB_FAULT_ADDR               0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define DCPLB_ADDR0                    0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
+#define DCPLB_ADDR1                    0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
+#define DCPLB_ADDR2                    0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
+#define DCPLB_ADDR3                    0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
+#define DCPLB_ADDR4                    0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
+#define DCPLB_ADDR5                    0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
+#define DCPLB_ADDR6                    0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
+#define DCPLB_ADDR7                    0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
+#define DCPLB_ADDR8                    0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
+#define DCPLB_ADDR9                    0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
+#define DCPLB_ADDR10                   0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
+#define DCPLB_ADDR11                   0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
+#define DCPLB_ADDR12                   0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
+#define DCPLB_ADDR13                   0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
+#define DCPLB_ADDR14                   0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
+#define DCPLB_ADDR15                   0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
+#define DCPLB_DATA0                    0xFFE00200 /* Data Cache 0 Status */
+#define DCPLB_DATA1                    0xFFE00204 /* Data Cache 1 Status */
+#define DCPLB_DATA2                    0xFFE00208 /* Data Cache 2 Status */
+#define DCPLB_DATA3                    0xFFE0020C /* Data Cache 3 Status */
+#define DCPLB_DATA4                    0xFFE00210 /* Data Cache 4 Status */
+#define DCPLB_DATA5                    0xFFE00214 /* Data Cache 5 Status */
+#define DCPLB_DATA6                    0xFFE00218 /* Data Cache 6 Status */
+#define DCPLB_DATA7                    0xFFE0021C /* Data Cache 7 Status */
+#define DCPLB_DATA8                    0xFFE00220 /* Data Cache 8 Status */
+#define DCPLB_DATA9                    0xFFE00224 /* Data Cache 9 Status */
+#define DCPLB_DATA10                   0xFFE00228 /* Data Cache 10 Status */
+#define DCPLB_DATA11                   0xFFE0022C /* Data Cache 11 Status */
+#define DCPLB_DATA12                   0xFFE00230 /* Data Cache 12 Status */
+#define DCPLB_DATA13                   0xFFE00234 /* Data Cache 13 Status */
+#define DCPLB_DATA14                   0xFFE00238 /* Data Cache 14 Status */
+#define DCPLB_DATA15                   0xFFE0023C /* Data Cache 15 Status */
+#define DTEST_COMMAND                  0xFFE00300 /* Data Test Command Register */
+#define DTEST_DATA0                    0xFFE00400 /* Data Test Data Register */
+#define DTEST_DATA1                    0xFFE00404 /* Data Test Data Register */
+#define IMEM_CONTROL                   0xFFE01004 /* Instruction Memory Control */
+#define ICPLB_STATUS                   0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define ICPLB_FAULT_ADDR               0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define ICPLB_ADDR0                    0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define ICPLB_ADDR1                    0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define ICPLB_ADDR2                    0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define ICPLB_ADDR3                    0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define ICPLB_ADDR4                    0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define ICPLB_ADDR5                    0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define ICPLB_ADDR6                    0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define ICPLB_ADDR7                    0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define ICPLB_ADDR8                    0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define ICPLB_ADDR9                    0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define ICPLB_ADDR10                   0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define ICPLB_ADDR11                   0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define ICPLB_ADDR12                   0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define ICPLB_ADDR13                   0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define ICPLB_ADDR14                   0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define ICPLB_ADDR15                   0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define ICPLB_DATA0                    0xFFE01200 /* Instruction Cache 0 Status */
+#define ICPLB_DATA1                    0xFFE01204 /* Instruction Cache 1 Status */
+#define ICPLB_DATA2                    0xFFE01208 /* Instruction Cache 2 Status */
+#define ICPLB_DATA3                    0xFFE0120C /* Instruction Cache 3 Status */
+#define ICPLB_DATA4                    0xFFE01210 /* Instruction Cache 4 Status */
+#define ICPLB_DATA5                    0xFFE01214 /* Instruction Cache 5 Status */
+#define ICPLB_DATA6                    0xFFE01218 /* Instruction Cache 6 Status */
+#define ICPLB_DATA7                    0xFFE0121C /* Instruction Cache 7 Status */
+#define ICPLB_DATA8                    0xFFE01220 /* Instruction Cache 8 Status */
+#define ICPLB_DATA9                    0xFFE01224 /* Instruction Cache 9 Status */
+#define ICPLB_DATA10                   0xFFE01228 /* Instruction Cache 10 Status */
+#define ICPLB_DATA11                   0xFFE0122C /* Instruction Cache 11 Status */
+#define ICPLB_DATA12                   0xFFE01230 /* Instruction Cache 12 Status */
+#define ICPLB_DATA13                   0xFFE01234 /* Instruction Cache 13 Status */
+#define ICPLB_DATA14                   0xFFE01238 /* Instruction Cache 14 Status */
+#define ICPLB_DATA15                   0xFFE0123C /* Instruction Cache 15 Status */
+#define ITEST_COMMAND                  0xFFE01300 /* Instruction Test Command Register */
+#define ITEST_DATA0                    0xFFE01400 /* Instruction Test Data Register */
+#define ITEST_DATA1                    0xFFE01404 /* Instruction Test Data Register */
+#define EVT0                           0xFFE02000 /* Event Vector 0 ESR Address */
+#define EVT1                           0xFFE02004 /* Event Vector 1 ESR Address */
+#define EVT2                           0xFFE02008 /* Event Vector 2 ESR Address */
+#define EVT3                           0xFFE0200C /* Event Vector 3 ESR Address */
+#define EVT4                           0xFFE02010 /* Event Vector 4 ESR Address */
+#define EVT5                           0xFFE02014 /* Event Vector 5 ESR Address */
+#define EVT6                           0xFFE02018 /* Event Vector 6 ESR Address */
+#define EVT7                           0xFFE0201C /* Event Vector 7 ESR Address */
+#define EVT8                           0xFFE02020 /* Event Vector 8 ESR Address */
+#define EVT9                           0xFFE02024 /* Event Vector 9 ESR Address */
+#define EVT10                          0xFFE02028 /* Event Vector 10 ESR Address */
+#define EVT11                          0xFFE0202C /* Event Vector 11 ESR Address */
+#define EVT12                          0xFFE02030 /* Event Vector 12 ESR Address */
+#define EVT13                          0xFFE02034 /* Event Vector 13 ESR Address */
+#define EVT14                          0xFFE02038 /* Event Vector 14 ESR Address */
+#define EVT15                          0xFFE0203C /* Event Vector 15 ESR Address */
+#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
+#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
+#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
+#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
+#define TCNTL                          0xFFE03000 /* Core Timer Control Register */
+#define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
+#define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
+#define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
+
+#endif /* __BFIN_DEF_ADSP_BF523_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h
new file mode 100644
index 000000000..9ec89c66a
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h
@@ -0,0 +1,848 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF524_proc__
+#define __BFIN_CDEF_ADSP_BF524_proc__
+
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
+#include "ADSP-EDN-BF52x-extended_cdef.h"
+
+#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
+#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
+#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
+#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */
+#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
+#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
+#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
+#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
+#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
+#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
+#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
+#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
+#define pCHIPID                        ((uint32_t volatile *)CHIPID)
+#define bfin_read_CHIPID()             bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
+#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
+#define bfin_read_SWRST()              bfin_read16(SWRST)
+#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
+#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
+#define bfin_read_SYSCR()              bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
+#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
+#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
+#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
+#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
+#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
+#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
+#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
+#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
+#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
+#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
+#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
+#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
+#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
+#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
+#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
+#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
+#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
+#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
+#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
+#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
+#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
+#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
+#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
+#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
+#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
+#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
+#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
+#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
+#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
+#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
+#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
+#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
+#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
+#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
+#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
+#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
+#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
+#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
+#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
+#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
+#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
+#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
+#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
+#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
+#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
+#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
+#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
+#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
+#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
+#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
+#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
+#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
+#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
+#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
+#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
+#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
+#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
+#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
+#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
+#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
+#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
+#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
+#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
+#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
+#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
+#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
+#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
+#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
+#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
+#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
+#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
+#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
+#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
+#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
+#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
+#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
+#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
+#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
+#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
+#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
+#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
+#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
+#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
+#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
+#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
+#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
+#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
+#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
+#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
+#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
+#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
+#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
+#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
+#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
+#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
+#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
+#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
+#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
+#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
+#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
+#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
+#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
+#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
+#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
+#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
+#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
+#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
+#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
+#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
+#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
+#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
+#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
+#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
+#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
+#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
+#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
+#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
+#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
+#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
+#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
+#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
+#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
+#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
+#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
+#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
+#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
+#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
+#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
+#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
+#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
+#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
+#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
+#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
+#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
+#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
+#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
+#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
+#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
+#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
+#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
+#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
+#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
+#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
+#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
+#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
+#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
+#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
+#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
+#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
+#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
+#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
+#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
+#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
+#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
+#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
+#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
+#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
+#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
+#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
+#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
+#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
+#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
+#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
+#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
+#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
+#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
+#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
+#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
+#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
+#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
+#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
+#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
+#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
+#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
+#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
+#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
+#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
+#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
+#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
+#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
+#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
+#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
+#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
+#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
+#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
+#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
+#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
+#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
+#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
+#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
+#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
+#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
+#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
+#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
+#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
+#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
+#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
+#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
+#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
+#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
+#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
+#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
+#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
+#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
+#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
+#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
+#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
+#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
+#define bfin_read_EVT0()               bfin_readPTR(EVT0)
+#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
+#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
+#define bfin_read_EVT1()               bfin_readPTR(EVT1)
+#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
+#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
+#define bfin_read_EVT2()               bfin_readPTR(EVT2)
+#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
+#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
+#define bfin_read_EVT3()               bfin_readPTR(EVT3)
+#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
+#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
+#define bfin_read_EVT4()               bfin_readPTR(EVT4)
+#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
+#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
+#define bfin_read_EVT5()               bfin_readPTR(EVT5)
+#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
+#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
+#define bfin_read_EVT6()               bfin_readPTR(EVT6)
+#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
+#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
+#define bfin_read_EVT7()               bfin_readPTR(EVT7)
+#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
+#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
+#define bfin_read_EVT8()               bfin_readPTR(EVT8)
+#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
+#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
+#define bfin_read_EVT9()               bfin_readPTR(EVT9)
+#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
+#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
+#define bfin_read_EVT10()              bfin_readPTR(EVT10)
+#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
+#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
+#define bfin_read_EVT11()              bfin_readPTR(EVT11)
+#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
+#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
+#define bfin_read_EVT12()              bfin_readPTR(EVT12)
+#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
+#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
+#define bfin_read_EVT13()              bfin_readPTR(EVT13)
+#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
+#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
+#define bfin_read_EVT14()              bfin_readPTR(EVT14)
+#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
+#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
+#define bfin_read_EVT15()              bfin_readPTR(EVT15)
+#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
+#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
+#define bfin_read_ILAT()               bfin_read32(ILAT)
+#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
+#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
+#define bfin_read_IMASK()              bfin_read32(IMASK)
+#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
+#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
+#define bfin_read_IPEND()              bfin_read32(IPEND)
+#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
+#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
+#define bfin_read_IPRIO()              bfin_read32(IPRIO)
+#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
+#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
+#define bfin_read_TCNTL()              bfin_read32(TCNTL)
+#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
+#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
+#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
+#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
+#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
+#define bfin_read_TSCALE()             bfin_read32(TSCALE)
+#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
+#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
+#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
+#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
+#define pUSB_FADDR                     ((uint16_t volatile *)USB_FADDR) /* Function address register */
+#define bfin_read_USB_FADDR()          bfin_read16(USB_FADDR)
+#define bfin_write_USB_FADDR(val)      bfin_write16(USB_FADDR, val)
+#define pUSB_POWER                     ((uint16_t volatile *)USB_POWER) /* Power management register */
+#define bfin_read_USB_POWER()          bfin_read16(USB_POWER)
+#define bfin_write_USB_POWER(val)      bfin_write16(USB_POWER, val)
+#define pUSB_INTRTX                    ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define bfin_read_USB_INTRTX()         bfin_read16(USB_INTRTX)
+#define bfin_write_USB_INTRTX(val)     bfin_write16(USB_INTRTX, val)
+#define pUSB_INTRRX                    ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */
+#define bfin_read_USB_INTRRX()         bfin_read16(USB_INTRRX)
+#define bfin_write_USB_INTRRX(val)     bfin_write16(USB_INTRRX, val)
+#define pUSB_INTRTXE                   ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */
+#define bfin_read_USB_INTRTXE()        bfin_read16(USB_INTRTXE)
+#define bfin_write_USB_INTRTXE(val)    bfin_write16(USB_INTRTXE, val)
+#define pUSB_INTRRXE                   ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */
+#define bfin_read_USB_INTRRXE()        bfin_read16(USB_INTRRXE)
+#define bfin_write_USB_INTRRXE(val)    bfin_write16(USB_INTRRXE, val)
+#define pUSB_INTRUSB                   ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */
+#define bfin_read_USB_INTRUSB()        bfin_read16(USB_INTRUSB)
+#define bfin_write_USB_INTRUSB(val)    bfin_write16(USB_INTRUSB, val)
+#define pUSB_INTRUSBE                  ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */
+#define bfin_read_USB_INTRUSBE()       bfin_read16(USB_INTRUSBE)
+#define bfin_write_USB_INTRUSBE(val)   bfin_write16(USB_INTRUSBE, val)
+#define pUSB_FRAME                     ((uint16_t volatile *)USB_FRAME) /* USB frame number */
+#define bfin_read_USB_FRAME()          bfin_read16(USB_FRAME)
+#define bfin_write_USB_FRAME(val)      bfin_write16(USB_FRAME, val)
+#define pUSB_INDEX                     ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */
+#define bfin_read_USB_INDEX()          bfin_read16(USB_INDEX)
+#define bfin_write_USB_INDEX(val)      bfin_write16(USB_INDEX, val)
+#define pUSB_TESTMODE                  ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */
+#define bfin_read_USB_TESTMODE()       bfin_read16(USB_TESTMODE)
+#define bfin_write_USB_TESTMODE(val)   bfin_write16(USB_TESTMODE, val)
+#define pUSB_GLOBINTR                  ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define bfin_read_USB_GLOBINTR()       bfin_read16(USB_GLOBINTR)
+#define bfin_write_USB_GLOBINTR(val)   bfin_write16(USB_GLOBINTR, val)
+#define pUSB_GLOBAL_CTL                ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */
+#define bfin_read_USB_GLOBAL_CTL()     bfin_read16(USB_GLOBAL_CTL)
+#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
+#define pUSB_TX_MAX_PACKET             ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */
+#define bfin_read_USB_TX_MAX_PACKET()  bfin_read16(USB_TX_MAX_PACKET)
+#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
+#define pUSB_CSR0                      ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define bfin_read_USB_CSR0()           bfin_read16(USB_CSR0)
+#define bfin_write_USB_CSR0(val)       bfin_write16(USB_CSR0, val)
+#define pUSB_TXCSR                     ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define bfin_read_USB_TXCSR()          bfin_read16(USB_TXCSR)
+#define bfin_write_USB_TXCSR(val)      bfin_write16(USB_TXCSR, val)
+#define pUSB_RX_MAX_PACKET             ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */
+#define bfin_read_USB_RX_MAX_PACKET()  bfin_read16(USB_RX_MAX_PACKET)
+#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
+#define pUSB_RXCSR                     ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */
+#define bfin_read_USB_RXCSR()          bfin_read16(USB_RXCSR)
+#define bfin_write_USB_RXCSR(val)      bfin_write16(USB_RXCSR, val)
+#define pUSB_COUNT0                    ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define bfin_read_USB_COUNT0()         bfin_read16(USB_COUNT0)
+#define bfin_write_USB_COUNT0(val)     bfin_write16(USB_COUNT0, val)
+#define pUSB_RXCOUNT                   ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define bfin_read_USB_RXCOUNT()        bfin_read16(USB_RXCOUNT)
+#define bfin_write_USB_RXCOUNT(val)    bfin_write16(USB_RXCOUNT, val)
+#define pUSB_TXTYPE                    ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define bfin_read_USB_TXTYPE()         bfin_read16(USB_TXTYPE)
+#define bfin_write_USB_TXTYPE(val)     bfin_write16(USB_TXTYPE, val)
+#define pUSB_NAKLIMIT0                 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define bfin_read_USB_NAKLIMIT0()      bfin_read16(USB_NAKLIMIT0)
+#define bfin_write_USB_NAKLIMIT0(val)  bfin_write16(USB_NAKLIMIT0, val)
+#define pUSB_TXINTERVAL                ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define bfin_read_USB_TXINTERVAL()     bfin_read16(USB_TXINTERVAL)
+#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
+#define pUSB_RXTYPE                    ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define bfin_read_USB_RXTYPE()         bfin_read16(USB_RXTYPE)
+#define bfin_write_USB_RXTYPE(val)     bfin_write16(USB_RXTYPE, val)
+#define pUSB_RXINTERVAL                ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define bfin_read_USB_RXINTERVAL()     bfin_read16(USB_RXINTERVAL)
+#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
+#define pUSB_TXCOUNT                   ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */
+#define bfin_read_USB_TXCOUNT()        bfin_read16(USB_TXCOUNT)
+#define bfin_write_USB_TXCOUNT(val)    bfin_write16(USB_TXCOUNT, val)
+#define pUSB_EP0_FIFO                  ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */
+#define bfin_read_USB_EP0_FIFO()       bfin_read16(USB_EP0_FIFO)
+#define bfin_write_USB_EP0_FIFO(val)   bfin_write16(USB_EP0_FIFO, val)
+#define pUSB_EP1_FIFO                  ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */
+#define bfin_read_USB_EP1_FIFO()       bfin_read16(USB_EP1_FIFO)
+#define bfin_write_USB_EP1_FIFO(val)   bfin_write16(USB_EP1_FIFO, val)
+#define pUSB_EP2_FIFO                  ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */
+#define bfin_read_USB_EP2_FIFO()       bfin_read16(USB_EP2_FIFO)
+#define bfin_write_USB_EP2_FIFO(val)   bfin_write16(USB_EP2_FIFO, val)
+#define pUSB_EP3_FIFO                  ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */
+#define bfin_read_USB_EP3_FIFO()       bfin_read16(USB_EP3_FIFO)
+#define bfin_write_USB_EP3_FIFO(val)   bfin_write16(USB_EP3_FIFO, val)
+#define pUSB_EP4_FIFO                  ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */
+#define bfin_read_USB_EP4_FIFO()       bfin_read16(USB_EP4_FIFO)
+#define bfin_write_USB_EP4_FIFO(val)   bfin_write16(USB_EP4_FIFO, val)
+#define pUSB_EP5_FIFO                  ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */
+#define bfin_read_USB_EP5_FIFO()       bfin_read16(USB_EP5_FIFO)
+#define bfin_write_USB_EP5_FIFO(val)   bfin_write16(USB_EP5_FIFO, val)
+#define pUSB_EP6_FIFO                  ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */
+#define bfin_read_USB_EP6_FIFO()       bfin_read16(USB_EP6_FIFO)
+#define bfin_write_USB_EP6_FIFO(val)   bfin_write16(USB_EP6_FIFO, val)
+#define pUSB_EP7_FIFO                  ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */
+#define bfin_read_USB_EP7_FIFO()       bfin_read16(USB_EP7_FIFO)
+#define bfin_write_USB_EP7_FIFO(val)   bfin_write16(USB_EP7_FIFO, val)
+#define pUSB_OTG_DEV_CTL               ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */
+#define bfin_read_USB_OTG_DEV_CTL()    bfin_read16(USB_OTG_DEV_CTL)
+#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
+#define pUSB_OTG_VBUS_IRQ              ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */
+#define bfin_read_USB_OTG_VBUS_IRQ()   bfin_read16(USB_OTG_VBUS_IRQ)
+#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
+#define pUSB_OTG_VBUS_MASK             ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */
+#define bfin_read_USB_OTG_VBUS_MASK()  bfin_read16(USB_OTG_VBUS_MASK)
+#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
+#define pUSB_LINKINFO                  ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */
+#define bfin_read_USB_LINKINFO()       bfin_read16(USB_LINKINFO)
+#define bfin_write_USB_LINKINFO(val)   bfin_write16(USB_LINKINFO, val)
+#define pUSB_VPLEN                     ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */
+#define bfin_read_USB_VPLEN()          bfin_read16(USB_VPLEN)
+#define bfin_write_USB_VPLEN(val)      bfin_write16(USB_VPLEN, val)
+#define pUSB_HS_EOF1                   ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */
+#define bfin_read_USB_HS_EOF1()        bfin_read16(USB_HS_EOF1)
+#define bfin_write_USB_HS_EOF1(val)    bfin_write16(USB_HS_EOF1, val)
+#define pUSB_FS_EOF1                   ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */
+#define bfin_read_USB_FS_EOF1()        bfin_read16(USB_FS_EOF1)
+#define bfin_write_USB_FS_EOF1(val)    bfin_write16(USB_FS_EOF1, val)
+#define pUSB_LS_EOF1                   ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */
+#define bfin_read_USB_LS_EOF1()        bfin_read16(USB_LS_EOF1)
+#define bfin_write_USB_LS_EOF1(val)    bfin_write16(USB_LS_EOF1, val)
+#define pUSB_APHY_CNTRL                ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */
+#define bfin_read_USB_APHY_CNTRL()     bfin_read16(USB_APHY_CNTRL)
+#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
+#define pUSB_APHY_CALIB                ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */
+#define bfin_read_USB_APHY_CALIB()     bfin_read16(USB_APHY_CALIB)
+#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
+#define pUSB_APHY_CNTRL2               ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+#define bfin_read_USB_APHY_CNTRL2()    bfin_read16(USB_APHY_CNTRL2)
+#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
+#define pUSB_PHY_TEST                  ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */
+#define bfin_read_USB_PHY_TEST()       bfin_read16(USB_PHY_TEST)
+#define bfin_write_USB_PHY_TEST(val)   bfin_write16(USB_PHY_TEST, val)
+#define pUSB_PLLOSC_CTRL               ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */
+#define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLLOSC_CTRL)
+#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
+#define pUSB_SRP_CLKDIV                ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */
+#define bfin_read_USB_SRP_CLKDIV()     bfin_read16(USB_SRP_CLKDIV)
+#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
+#define pUSB_EP_NI0_TXMAXP             ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */
+#define bfin_read_USB_EP_NI0_TXMAXP()  bfin_read16(USB_EP_NI0_TXMAXP)
+#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
+#define pUSB_EP_NI0_TXCSR              ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */
+#define bfin_read_USB_EP_NI0_TXCSR()   bfin_read16(USB_EP_NI0_TXCSR)
+#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
+#define pUSB_EP_NI0_RXMAXP             ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXMAXP()  bfin_read16(USB_EP_NI0_RXMAXP)
+#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
+#define pUSB_EP_NI0_RXCSR              ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXCSR()   bfin_read16(USB_EP_NI0_RXCSR)
+#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
+#define pUSB_EP_NI0_RXCOUNT            ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */
+#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
+#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
+#define pUSB_EP_NI0_TXTYPE             ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define bfin_read_USB_EP_NI0_TXTYPE()  bfin_read16(USB_EP_NI0_TXTYPE)
+#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
+#define pUSB_EP_NI0_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */
+#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
+#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
+#define pUSB_EP_NI0_RXTYPE             ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXTYPE()  bfin_read16(USB_EP_NI0_RXTYPE)
+#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
+#define pUSB_EP_NI0_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
+#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
+#define pUSB_EP_NI0_TXCOUNT            ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */
+#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
+#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
+#define pUSB_EP_NI1_TXMAXP             ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */
+#define bfin_read_USB_EP_NI1_TXMAXP()  bfin_read16(USB_EP_NI1_TXMAXP)
+#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
+#define pUSB_EP_NI1_TXCSR              ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */
+#define bfin_read_USB_EP_NI1_TXCSR()   bfin_read16(USB_EP_NI1_TXCSR)
+#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
+#define pUSB_EP_NI1_RXMAXP             ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXMAXP()  bfin_read16(USB_EP_NI1_RXMAXP)
+#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
+#define pUSB_EP_NI1_RXCSR              ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXCSR()   bfin_read16(USB_EP_NI1_RXCSR)
+#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
+#define pUSB_EP_NI1_RXCOUNT            ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */
+#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
+#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
+#define pUSB_EP_NI1_TXTYPE             ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define bfin_read_USB_EP_NI1_TXTYPE()  bfin_read16(USB_EP_NI1_TXTYPE)
+#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
+#define pUSB_EP_NI1_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */
+#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
+#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
+#define pUSB_EP_NI1_RXTYPE             ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXTYPE()  bfin_read16(USB_EP_NI1_RXTYPE)
+#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
+#define pUSB_EP_NI1_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
+#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
+#define pUSB_EP_NI1_TXCOUNT            ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
+#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
+#define pUSB_EP_NI2_TXMAXP             ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */
+#define bfin_read_USB_EP_NI2_TXMAXP()  bfin_read16(USB_EP_NI2_TXMAXP)
+#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
+#define pUSB_EP_NI2_TXCSR              ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */
+#define bfin_read_USB_EP_NI2_TXCSR()   bfin_read16(USB_EP_NI2_TXCSR)
+#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
+#define pUSB_EP_NI2_RXMAXP             ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXMAXP()  bfin_read16(USB_EP_NI2_RXMAXP)
+#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
+#define pUSB_EP_NI2_RXCSR              ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXCSR()   bfin_read16(USB_EP_NI2_RXCSR)
+#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
+#define pUSB_EP_NI2_RXCOUNT            ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */
+#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
+#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
+#define pUSB_EP_NI2_TXTYPE             ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define bfin_read_USB_EP_NI2_TXTYPE()  bfin_read16(USB_EP_NI2_TXTYPE)
+#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
+#define pUSB_EP_NI2_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */
+#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
+#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
+#define pUSB_EP_NI2_RXTYPE             ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXTYPE()  bfin_read16(USB_EP_NI2_RXTYPE)
+#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
+#define pUSB_EP_NI2_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
+#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
+#define pUSB_EP_NI2_TXCOUNT            ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */
+#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
+#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
+#define pUSB_EP_NI3_TXMAXP             ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */
+#define bfin_read_USB_EP_NI3_TXMAXP()  bfin_read16(USB_EP_NI3_TXMAXP)
+#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
+#define pUSB_EP_NI3_TXCSR              ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */
+#define bfin_read_USB_EP_NI3_TXCSR()   bfin_read16(USB_EP_NI3_TXCSR)
+#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
+#define pUSB_EP_NI3_RXMAXP             ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXMAXP()  bfin_read16(USB_EP_NI3_RXMAXP)
+#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
+#define pUSB_EP_NI3_RXCSR              ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXCSR()   bfin_read16(USB_EP_NI3_RXCSR)
+#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
+#define pUSB_EP_NI3_RXCOUNT            ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */
+#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
+#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
+#define pUSB_EP_NI3_TXTYPE             ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define bfin_read_USB_EP_NI3_TXTYPE()  bfin_read16(USB_EP_NI3_TXTYPE)
+#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
+#define pUSB_EP_NI3_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */
+#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
+#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
+#define pUSB_EP_NI3_RXTYPE             ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXTYPE()  bfin_read16(USB_EP_NI3_RXTYPE)
+#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
+#define pUSB_EP_NI3_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
+#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
+#define pUSB_EP_NI3_TXCOUNT            ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
+#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
+#define pUSB_EP_NI4_TXMAXP             ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */
+#define bfin_read_USB_EP_NI4_TXMAXP()  bfin_read16(USB_EP_NI4_TXMAXP)
+#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
+#define pUSB_EP_NI4_TXCSR              ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */
+#define bfin_read_USB_EP_NI4_TXCSR()   bfin_read16(USB_EP_NI4_TXCSR)
+#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
+#define pUSB_EP_NI4_RXMAXP             ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXMAXP()  bfin_read16(USB_EP_NI4_RXMAXP)
+#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
+#define pUSB_EP_NI4_RXCSR              ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXCSR()   bfin_read16(USB_EP_NI4_RXCSR)
+#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
+#define pUSB_EP_NI4_RXCOUNT            ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */
+#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
+#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
+#define pUSB_EP_NI4_TXTYPE             ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define bfin_read_USB_EP_NI4_TXTYPE()  bfin_read16(USB_EP_NI4_TXTYPE)
+#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
+#define pUSB_EP_NI4_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */
+#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
+#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
+#define pUSB_EP_NI4_RXTYPE             ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXTYPE()  bfin_read16(USB_EP_NI4_RXTYPE)
+#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
+#define pUSB_EP_NI4_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
+#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
+#define pUSB_EP_NI4_TXCOUNT            ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */
+#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
+#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
+#define pUSB_EP_NI5_TXMAXP             ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */
+#define bfin_read_USB_EP_NI5_TXMAXP()  bfin_read16(USB_EP_NI5_TXMAXP)
+#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
+#define pUSB_EP_NI5_TXCSR              ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */
+#define bfin_read_USB_EP_NI5_TXCSR()   bfin_read16(USB_EP_NI5_TXCSR)
+#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
+#define pUSB_EP_NI5_RXMAXP             ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXMAXP()  bfin_read16(USB_EP_NI5_RXMAXP)
+#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
+#define pUSB_EP_NI5_RXCSR              ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXCSR()   bfin_read16(USB_EP_NI5_RXCSR)
+#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
+#define pUSB_EP_NI5_RXCOUNT            ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */
+#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
+#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
+#define pUSB_EP_NI5_TXTYPE             ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define bfin_read_USB_EP_NI5_TXTYPE()  bfin_read16(USB_EP_NI5_TXTYPE)
+#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
+#define pUSB_EP_NI5_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */
+#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
+#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
+#define pUSB_EP_NI5_RXTYPE             ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXTYPE()  bfin_read16(USB_EP_NI5_RXTYPE)
+#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
+#define pUSB_EP_NI5_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
+#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
+#define pUSB_EP_NI5_TXCOUNT            ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */
+#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
+#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
+#define pUSB_EP_NI6_TXMAXP             ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */
+#define bfin_read_USB_EP_NI6_TXMAXP()  bfin_read16(USB_EP_NI6_TXMAXP)
+#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
+#define pUSB_EP_NI6_TXCSR              ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */
+#define bfin_read_USB_EP_NI6_TXCSR()   bfin_read16(USB_EP_NI6_TXCSR)
+#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
+#define pUSB_EP_NI6_RXMAXP             ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXMAXP()  bfin_read16(USB_EP_NI6_RXMAXP)
+#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
+#define pUSB_EP_NI6_RXCSR              ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXCSR()   bfin_read16(USB_EP_NI6_RXCSR)
+#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
+#define pUSB_EP_NI6_RXCOUNT            ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */
+#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
+#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
+#define pUSB_EP_NI6_TXTYPE             ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define bfin_read_USB_EP_NI6_TXTYPE()  bfin_read16(USB_EP_NI6_TXTYPE)
+#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
+#define pUSB_EP_NI6_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */
+#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
+#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
+#define pUSB_EP_NI6_RXTYPE             ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXTYPE()  bfin_read16(USB_EP_NI6_RXTYPE)
+#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
+#define pUSB_EP_NI6_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
+#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
+#define pUSB_EP_NI6_TXCOUNT            ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */
+#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
+#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
+#define pUSB_EP_NI7_TXMAXP             ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */
+#define bfin_read_USB_EP_NI7_TXMAXP()  bfin_read16(USB_EP_NI7_TXMAXP)
+#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
+#define pUSB_EP_NI7_TXCSR              ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */
+#define bfin_read_USB_EP_NI7_TXCSR()   bfin_read16(USB_EP_NI7_TXCSR)
+#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
+#define pUSB_EP_NI7_RXMAXP             ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXMAXP()  bfin_read16(USB_EP_NI7_RXMAXP)
+#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
+#define pUSB_EP_NI7_RXCSR              ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXCSR()   bfin_read16(USB_EP_NI7_RXCSR)
+#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
+#define pUSB_EP_NI7_RXCOUNT            ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */
+#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
+#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
+#define pUSB_EP_NI7_TXTYPE             ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define bfin_read_USB_EP_NI7_TXTYPE()  bfin_read16(USB_EP_NI7_TXTYPE)
+#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
+#define pUSB_EP_NI7_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */
+#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
+#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
+#define pUSB_EP_NI7_RXTYPE             ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXTYPE()  bfin_read16(USB_EP_NI7_RXTYPE)
+#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
+#define pUSB_EP_NI7_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
+#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
+#define pUSB_EP_NI7_TXCOUNT            ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
+#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
+#define pUSB_DMA_INTERRUPT             ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */
+#define bfin_read_USB_DMA_INTERRUPT()  bfin_read16(USB_DMA_INTERRUPT)
+#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
+#define pUSB_DMA0_CONTROL              ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */
+#define bfin_read_USB_DMA0_CONTROL()   bfin_read16(USB_DMA0_CONTROL)
+#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
+#define pUSB_DMA0_ADDRLOW              ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define bfin_read_USB_DMA0_ADDRLOW()   bfin_read16(USB_DMA0_ADDRLOW)
+#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
+#define pUSB_DMA0_ADDRHIGH             ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define bfin_read_USB_DMA0_ADDRHIGH()  bfin_read16(USB_DMA0_ADDRHIGH)
+#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
+#define pUSB_DMA0_COUNTLOW             ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define bfin_read_USB_DMA0_COUNTLOW()  bfin_read16(USB_DMA0_COUNTLOW)
+#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
+#define pUSB_DMA0_COUNTHIGH            ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
+#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
+#define pUSB_DMA1_CONTROL              ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */
+#define bfin_read_USB_DMA1_CONTROL()   bfin_read16(USB_DMA1_CONTROL)
+#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
+#define pUSB_DMA1_ADDRLOW              ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define bfin_read_USB_DMA1_ADDRLOW()   bfin_read16(USB_DMA1_ADDRLOW)
+#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
+#define pUSB_DMA1_ADDRHIGH             ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define bfin_read_USB_DMA1_ADDRHIGH()  bfin_read16(USB_DMA1_ADDRHIGH)
+#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
+#define pUSB_DMA1_COUNTLOW             ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define bfin_read_USB_DMA1_COUNTLOW()  bfin_read16(USB_DMA1_COUNTLOW)
+#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
+#define pUSB_DMA1_COUNTHIGH            ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
+#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
+#define pUSB_DMA2_CONTROL              ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */
+#define bfin_read_USB_DMA2_CONTROL()   bfin_read16(USB_DMA2_CONTROL)
+#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
+#define pUSB_DMA2_ADDRLOW              ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define bfin_read_USB_DMA2_ADDRLOW()   bfin_read16(USB_DMA2_ADDRLOW)
+#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
+#define pUSB_DMA2_ADDRHIGH             ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define bfin_read_USB_DMA2_ADDRHIGH()  bfin_read16(USB_DMA2_ADDRHIGH)
+#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
+#define pUSB_DMA2_COUNTLOW             ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define bfin_read_USB_DMA2_COUNTLOW()  bfin_read16(USB_DMA2_COUNTLOW)
+#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
+#define pUSB_DMA2_COUNTHIGH            ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
+#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
+#define pUSB_DMA3_CONTROL              ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */
+#define bfin_read_USB_DMA3_CONTROL()   bfin_read16(USB_DMA3_CONTROL)
+#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
+#define pUSB_DMA3_ADDRLOW              ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define bfin_read_USB_DMA3_ADDRLOW()   bfin_read16(USB_DMA3_ADDRLOW)
+#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
+#define pUSB_DMA3_ADDRHIGH             ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define bfin_read_USB_DMA3_ADDRHIGH()  bfin_read16(USB_DMA3_ADDRHIGH)
+#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
+#define pUSB_DMA3_COUNTLOW             ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define bfin_read_USB_DMA3_COUNTLOW()  bfin_read16(USB_DMA3_COUNTLOW)
+#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
+#define pUSB_DMA3_COUNTHIGH            ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
+#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
+#define pUSB_DMA4_CONTROL              ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */
+#define bfin_read_USB_DMA4_CONTROL()   bfin_read16(USB_DMA4_CONTROL)
+#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
+#define pUSB_DMA4_ADDRLOW              ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define bfin_read_USB_DMA4_ADDRLOW()   bfin_read16(USB_DMA4_ADDRLOW)
+#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
+#define pUSB_DMA4_ADDRHIGH             ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define bfin_read_USB_DMA4_ADDRHIGH()  bfin_read16(USB_DMA4_ADDRHIGH)
+#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
+#define pUSB_DMA4_COUNTLOW             ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define bfin_read_USB_DMA4_COUNTLOW()  bfin_read16(USB_DMA4_COUNTLOW)
+#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
+#define pUSB_DMA4_COUNTHIGH            ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
+#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
+#define pUSB_DMA5_CONTROL              ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */
+#define bfin_read_USB_DMA5_CONTROL()   bfin_read16(USB_DMA5_CONTROL)
+#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
+#define pUSB_DMA5_ADDRLOW              ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define bfin_read_USB_DMA5_ADDRLOW()   bfin_read16(USB_DMA5_ADDRLOW)
+#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
+#define pUSB_DMA5_ADDRHIGH             ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define bfin_read_USB_DMA5_ADDRHIGH()  bfin_read16(USB_DMA5_ADDRHIGH)
+#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
+#define pUSB_DMA5_COUNTLOW             ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define bfin_read_USB_DMA5_COUNTLOW()  bfin_read16(USB_DMA5_COUNTLOW)
+#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
+#define pUSB_DMA5_COUNTHIGH            ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
+#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
+#define pUSB_DMA6_CONTROL              ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */
+#define bfin_read_USB_DMA6_CONTROL()   bfin_read16(USB_DMA6_CONTROL)
+#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
+#define pUSB_DMA6_ADDRLOW              ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define bfin_read_USB_DMA6_ADDRLOW()   bfin_read16(USB_DMA6_ADDRLOW)
+#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
+#define pUSB_DMA6_ADDRHIGH             ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define bfin_read_USB_DMA6_ADDRHIGH()  bfin_read16(USB_DMA6_ADDRHIGH)
+#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
+#define pUSB_DMA6_COUNTLOW             ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define bfin_read_USB_DMA6_COUNTLOW()  bfin_read16(USB_DMA6_COUNTLOW)
+#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
+#define pUSB_DMA6_COUNTHIGH            ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
+#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
+#define pUSB_DMA7_CONTROL              ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */
+#define bfin_read_USB_DMA7_CONTROL()   bfin_read16(USB_DMA7_CONTROL)
+#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
+#define pUSB_DMA7_ADDRLOW              ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define bfin_read_USB_DMA7_ADDRLOW()   bfin_read16(USB_DMA7_ADDRLOW)
+#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
+#define pUSB_DMA7_ADDRHIGH             ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define bfin_read_USB_DMA7_ADDRHIGH()  bfin_read16(USB_DMA7_ADDRHIGH)
+#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
+#define pUSB_DMA7_COUNTLOW             ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define bfin_read_USB_DMA7_COUNTLOW()  bfin_read16(USB_DMA7_COUNTLOW)
+#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
+#define pUSB_DMA7_COUNTHIGH            ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
+#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
+
+#endif /* __BFIN_CDEF_ADSP_BF524_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF524_def.h b/arch/blackfin/include/asm/mach-bf527/BF524_def.h
new file mode 100644
index 000000000..bd6aa8fdb
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf527/BF524_def.h
@@ -0,0 +1,292 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF524_proc__
+#define __BFIN_DEF_ADSP_BF524_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#include "ADSP-EDN-BF52x-extended_def.h"
+
+#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
+#define PLL_DIV                        0xFFC00004 /* PLL Divide Register */
+#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
+#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
+#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
+#define CHIPID                         0xFFC00014
+#define SWRST                          0xFFC00100 /* Software Reset Register */
+#define SYSCR                          0xFFC00104 /* System Configuration register */
+#define SRAM_BASE_ADDR                 0xFFE00000 /* SRAM Base Address (Read Only) */
+#define DMEM_CONTROL                   0xFFE00004 /* Data memory control */
+#define DCPLB_STATUS                   0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
+#define DCPLB_FAULT_ADDR               0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define DCPLB_ADDR0                    0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
+#define DCPLB_ADDR1                    0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
+#define DCPLB_ADDR2                    0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
+#define DCPLB_ADDR3                    0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
+#define DCPLB_ADDR4                    0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
+#define DCPLB_ADDR5                    0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
+#define DCPLB_ADDR6                    0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
+#define DCPLB_ADDR7                    0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
+#define DCPLB_ADDR8                    0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
+#define DCPLB_ADDR9                    0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
+#define DCPLB_ADDR10                   0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
+#define DCPLB_ADDR11                   0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
+#define DCPLB_ADDR12                   0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
+#define DCPLB_ADDR13                   0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
+#define DCPLB_ADDR14                   0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
+#define DCPLB_ADDR15                   0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
+#define DCPLB_DATA0                    0xFFE00200 /* Data Cache 0 Status */
+#define DCPLB_DATA1                    0xFFE00204 /* Data Cache 1 Status */
+#define DCPLB_DATA2                    0xFFE00208 /* Data Cache 2 Status */
+#define DCPLB_DATA3                    0xFFE0020C /* Data Cache 3 Status */
+#define DCPLB_DATA4                    0xFFE00210 /* Data Cache 4 Status */
+#define DCPLB_DATA5                    0xFFE00214 /* Data Cache 5 Status */
+#define DCPLB_DATA6                    0xFFE00218 /* Data Cache 6 Status */
+#define DCPLB_DATA7                    0xFFE0021C /* Data Cache 7 Status */
+#define DCPLB_DATA8                    0xFFE00220 /* Data Cache 8 Status */
+#define DCPLB_DATA9                    0xFFE00224 /* Data Cache 9 Status */
+#define DCPLB_DATA10                   0xFFE00228 /* Data Cache 10 Status */
+#define DCPLB_DATA11                   0xFFE0022C /* Data Cache 11 Status */
+#define DCPLB_DATA12                   0xFFE00230 /* Data Cache 12 Status */
+#define DCPLB_DATA13                   0xFFE00234 /* Data Cache 13 Status */
+#define DCPLB_DATA14                   0xFFE00238 /* Data Cache 14 Status */
+#define DCPLB_DATA15                   0xFFE0023C /* Data Cache 15 Status */
+#define DTEST_COMMAND                  0xFFE00300 /* Data Test Command Register */
+#define DTEST_DATA0                    0xFFE00400 /* Data Test Data Register */
+#define DTEST_DATA1                    0xFFE00404 /* Data Test Data Register */
+#define IMEM_CONTROL                   0xFFE01004 /* Instruction Memory Control */
+#define ICPLB_STATUS                   0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define ICPLB_FAULT_ADDR               0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define ICPLB_ADDR0                    0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define ICPLB_ADDR1                    0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define ICPLB_ADDR2                    0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define ICPLB_ADDR3                    0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define ICPLB_ADDR4                    0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define ICPLB_ADDR5                    0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define ICPLB_ADDR6                    0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define ICPLB_ADDR7                    0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define ICPLB_ADDR8                    0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define ICPLB_ADDR9                    0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define ICPLB_ADDR10                   0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define ICPLB_ADDR11                   0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define ICPLB_ADDR12                   0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define ICPLB_ADDR13                   0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define ICPLB_ADDR14                   0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define ICPLB_ADDR15                   0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define ICPLB_DATA0                    0xFFE01200 /* Instruction Cache 0 Status */
+#define ICPLB_DATA1                    0xFFE01204 /* Instruction Cache 1 Status */
+#define ICPLB_DATA2                    0xFFE01208 /* Instruction Cache 2 Status */
+#define ICPLB_DATA3                    0xFFE0120C /* Instruction Cache 3 Status */
+#define ICPLB_DATA4                    0xFFE01210 /* Instruction Cache 4 Status */
+#define ICPLB_DATA5                    0xFFE01214 /* Instruction Cache 5 Status */
+#define ICPLB_DATA6                    0xFFE01218 /* Instruction Cache 6 Status */
+#define ICPLB_DATA7                    0xFFE0121C /* Instruction Cache 7 Status */
+#define ICPLB_DATA8                    0xFFE01220 /* Instruction Cache 8 Status */
+#define ICPLB_DATA9                    0xFFE01224 /* Instruction Cache 9 Status */
+#define ICPLB_DATA10                   0xFFE01228 /* Instruction Cache 10 Status */
+#define ICPLB_DATA11                   0xFFE0122C /* Instruction Cache 11 Status */
+#define ICPLB_DATA12                   0xFFE01230 /* Instruction Cache 12 Status */
+#define ICPLB_DATA13                   0xFFE01234 /* Instruction Cache 13 Status */
+#define ICPLB_DATA14                   0xFFE01238 /* Instruction Cache 14 Status */
+#define ICPLB_DATA15                   0xFFE0123C /* Instruction Cache 15 Status */
+#define ITEST_COMMAND                  0xFFE01300 /* Instruction Test Command Register */
+#define ITEST_DATA0                    0xFFE01400 /* Instruction Test Data Register */
+#define ITEST_DATA1                    0xFFE01404 /* Instruction Test Data Register */
+#define EVT0                           0xFFE02000 /* Event Vector 0 ESR Address */
+#define EVT1                           0xFFE02004 /* Event Vector 1 ESR Address */
+#define EVT2                           0xFFE02008 /* Event Vector 2 ESR Address */
+#define EVT3                           0xFFE0200C /* Event Vector 3 ESR Address */
+#define EVT4                           0xFFE02010 /* Event Vector 4 ESR Address */
+#define EVT5                           0xFFE02014 /* Event Vector 5 ESR Address */
+#define EVT6                           0xFFE02018 /* Event Vector 6 ESR Address */
+#define EVT7                           0xFFE0201C /* Event Vector 7 ESR Address */
+#define EVT8                           0xFFE02020 /* Event Vector 8 ESR Address */
+#define EVT9                           0xFFE02024 /* Event Vector 9 ESR Address */
+#define EVT10                          0xFFE02028 /* Event Vector 10 ESR Address */
+#define EVT11                          0xFFE0202C /* Event Vector 11 ESR Address */
+#define EVT12                          0xFFE02030 /* Event Vector 12 ESR Address */
+#define EVT13                          0xFFE02034 /* Event Vector 13 ESR Address */
+#define EVT14                          0xFFE02038 /* Event Vector 14 ESR Address */
+#define EVT15                          0xFFE0203C /* Event Vector 15 ESR Address */
+#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
+#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
+#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
+#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
+#define TCNTL                          0xFFE03000 /* Core Timer Control Register */
+#define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
+#define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
+#define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
+#define USB_FADDR                      0xFFC03800 /* Function address register */
+#define USB_POWER                      0xFFC03804 /* Power management register */
+#define USB_INTRTX                     0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define USB_INTRRX                     0xFFC0380C /* Interrupt register for Rx endpoints 1 to 7 */
+#define USB_INTRTXE                    0xFFC03810 /* Interrupt enable register for IntrTx */
+#define USB_INTRRXE                    0xFFC03814 /* Interrupt enable register for IntrRx */
+#define USB_INTRUSB                    0xFFC03818 /* Interrupt register for common USB interrupts */
+#define USB_INTRUSBE                   0xFFC0381C /* Interrupt enable register for IntrUSB */
+#define USB_FRAME                      0xFFC03820 /* USB frame number */
+#define USB_INDEX                      0xFFC03824 /* Index register for selecting the indexed endpoint registers */
+#define USB_TESTMODE                   0xFFC03828 /* Enabled USB 20 test modes */
+#define USB_GLOBINTR                   0xFFC0382C /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define USB_GLOBAL_CTL                 0xFFC03830 /* Global Clock Control for the core */
+#define USB_TX_MAX_PACKET              0xFFC03840 /* Maximum packet size for Host Tx endpoint */
+#define USB_CSR0                       0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_TXCSR                      0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_RX_MAX_PACKET              0xFFC03848 /* Maximum packet size for Host Rx endpoint */
+#define USB_RXCSR                      0xFFC0384C /* Control Status register for Host Rx endpoint */
+#define USB_COUNT0                     0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_RXCOUNT                    0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_TXTYPE                     0xFFC03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define USB_NAKLIMIT0                  0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_TXINTERVAL                 0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_RXTYPE                     0xFFC0385C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define USB_RXINTERVAL                 0xFFC03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define USB_TXCOUNT                    0xFFC03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
+#define USB_EP0_FIFO                   0xFFC03880 /* Endpoint 0 FIFO */
+#define USB_EP1_FIFO                   0xFFC03888 /* Endpoint 1 FIFO */
+#define USB_EP2_FIFO                   0xFFC03890 /* Endpoint 2 FIFO */
+#define USB_EP3_FIFO                   0xFFC03898 /* Endpoint 3 FIFO */
+#define USB_EP4_FIFO                   0xFFC038A0 /* Endpoint 4 FIFO */
+#define USB_EP5_FIFO                   0xFFC038A8 /* Endpoint 5 FIFO */
+#define USB_EP6_FIFO                   0xFFC038B0 /* Endpoint 6 FIFO */
+#define USB_EP7_FIFO                   0xFFC038B8 /* Endpoint 7 FIFO */
+#define USB_OTG_DEV_CTL                0xFFC03900 /* OTG Device Control Register */
+#define USB_OTG_VBUS_IRQ               0xFFC03904 /* OTG VBUS Control Interrupts */
+#define USB_OTG_VBUS_MASK              0xFFC03908 /* VBUS Control Interrupt Enable */
+#define USB_LINKINFO                   0xFFC03948 /* Enables programming of some PHY-side delays */
+#define USB_VPLEN                      0xFFC0394C /* Determines duration of VBUS pulse for VBUS charging */
+#define USB_HS_EOF1                    0xFFC03950 /* Time buffer for High-Speed transactions */
+#define USB_FS_EOF1                    0xFFC03954 /* Time buffer for Full-Speed transactions */
+#define USB_LS_EOF1                    0xFFC03958 /* Time buffer for Low-Speed transactions */
+#define USB_APHY_CNTRL                 0xFFC039E0 /* Register that increases visibility of Analog PHY */
+#define USB_APHY_CALIB                 0xFFC039E4 /* Register used to set some calibration values */
+#define USB_APHY_CNTRL2                0xFFC039E8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+#define USB_PHY_TEST                   0xFFC039EC /* Used for reducing simulation time and simplifies FIFO testability */
+#define USB_PLLOSC_CTRL                0xFFC039F0 /* Used to program different parameters for USB PLL and Oscillator */
+#define USB_SRP_CLKDIV                 0xFFC039F4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
+#define USB_EP_NI0_TXMAXP              0xFFC03A00 /* Maximum packet size for Host Tx endpoint0 */
+#define USB_EP_NI0_TXCSR               0xFFC03A04 /* Control Status register for endpoint 0 */
+#define USB_EP_NI0_RXMAXP              0xFFC03A08 /* Maximum packet size for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCSR               0xFFC03A0C /* Control Status register for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCOUNT             0xFFC03A10 /* Number of bytes received in endpoint 0 FIFO */
+#define USB_EP_NI0_TXTYPE              0xFFC03A14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define USB_EP_NI0_TXINTERVAL          0xFFC03A18 /* Sets the NAK response timeout on Endpoint 0 */
+#define USB_EP_NI0_RXTYPE              0xFFC03A1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define USB_EP_NI0_RXINTERVAL          0xFFC03A20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+#define USB_EP_NI0_TXCOUNT             0xFFC03A28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
+#define USB_EP_NI1_TXMAXP              0xFFC03A40 /* Maximum packet size for Host Tx endpoint1 */
+#define USB_EP_NI1_TXCSR               0xFFC03A44 /* Control Status register for endpoint1 */
+#define USB_EP_NI1_RXMAXP              0xFFC03A48 /* Maximum packet size for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCSR               0xFFC03A4C /* Control Status register for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCOUNT             0xFFC03A50 /* Number of bytes received in endpoint1 FIFO */
+#define USB_EP_NI1_TXTYPE              0xFFC03A54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define USB_EP_NI1_TXINTERVAL          0xFFC03A58 /* Sets the NAK response timeout on Endpoint1 */
+#define USB_EP_NI1_RXTYPE              0xFFC03A5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define USB_EP_NI1_RXINTERVAL          0xFFC03A60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+#define USB_EP_NI1_TXCOUNT             0xFFC03A68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+#define USB_EP_NI2_TXMAXP              0xFFC03A80 /* Maximum packet size for Host Tx endpoint2 */
+#define USB_EP_NI2_TXCSR               0xFFC03A84 /* Control Status register for endpoint2 */
+#define USB_EP_NI2_RXMAXP              0xFFC03A88 /* Maximum packet size for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCSR               0xFFC03A8C /* Control Status register for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCOUNT             0xFFC03A90 /* Number of bytes received in endpoint2 FIFO */
+#define USB_EP_NI2_TXTYPE              0xFFC03A94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define USB_EP_NI2_TXINTERVAL          0xFFC03A98 /* Sets the NAK response timeout on Endpoint2 */
+#define USB_EP_NI2_RXTYPE              0xFFC03A9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define USB_EP_NI2_RXINTERVAL          0xFFC03AA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+#define USB_EP_NI2_TXCOUNT             0xFFC03AA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
+#define USB_EP_NI3_TXMAXP              0xFFC03AC0 /* Maximum packet size for Host Tx endpoint3 */
+#define USB_EP_NI3_TXCSR               0xFFC03AC4 /* Control Status register for endpoint3 */
+#define USB_EP_NI3_RXMAXP              0xFFC03AC8 /* Maximum packet size for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCSR               0xFFC03ACC /* Control Status register for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCOUNT             0xFFC03AD0 /* Number of bytes received in endpoint3 FIFO */
+#define USB_EP_NI3_TXTYPE              0xFFC03AD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define USB_EP_NI3_TXINTERVAL          0xFFC03AD8 /* Sets the NAK response timeout on Endpoint3 */
+#define USB_EP_NI3_RXTYPE              0xFFC03ADC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define USB_EP_NI3_RXINTERVAL          0xFFC03AE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+#define USB_EP_NI3_TXCOUNT             0xFFC03AE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+#define USB_EP_NI4_TXMAXP              0xFFC03B00 /* Maximum packet size for Host Tx endpoint4 */
+#define USB_EP_NI4_TXCSR               0xFFC03B04 /* Control Status register for endpoint4 */
+#define USB_EP_NI4_RXMAXP              0xFFC03B08 /* Maximum packet size for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCSR               0xFFC03B0C /* Control Status register for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCOUNT             0xFFC03B10 /* Number of bytes received in endpoint4 FIFO */
+#define USB_EP_NI4_TXTYPE              0xFFC03B14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define USB_EP_NI4_TXINTERVAL          0xFFC03B18 /* Sets the NAK response timeout on Endpoint4 */
+#define USB_EP_NI4_RXTYPE              0xFFC03B1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define USB_EP_NI4_RXINTERVAL          0xFFC03B20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+#define USB_EP_NI4_TXCOUNT             0xFFC03B28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
+#define USB_EP_NI5_TXMAXP              0xFFC03B40 /* Maximum packet size for Host Tx endpoint5 */
+#define USB_EP_NI5_TXCSR               0xFFC03B44 /* Control Status register for endpoint5 */
+#define USB_EP_NI5_RXMAXP              0xFFC03B48 /* Maximum packet size for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCSR               0xFFC03B4C /* Control Status register for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCOUNT             0xFFC03B50 /* Number of bytes received in endpoint5 FIFO */
+#define USB_EP_NI5_TXTYPE              0xFFC03B54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define USB_EP_NI5_TXINTERVAL          0xFFC03B58 /* Sets the NAK response timeout on Endpoint5 */
+#define USB_EP_NI5_RXTYPE              0xFFC03B5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define USB_EP_NI5_RXINTERVAL          0xFFC03B60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+#define USB_EP_NI5_TXCOUNT             0xFFC03B68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
+#define USB_EP_NI6_TXMAXP              0xFFC03B80 /* Maximum packet size for Host Tx endpoint6 */
+#define USB_EP_NI6_TXCSR               0xFFC03B84 /* Control Status register for endpoint6 */
+#define USB_EP_NI6_RXMAXP              0xFFC03B88 /* Maximum packet size for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCSR               0xFFC03B8C /* Control Status register for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCOUNT             0xFFC03B90 /* Number of bytes received in endpoint6 FIFO */
+#define USB_EP_NI6_TXTYPE              0xFFC03B94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define USB_EP_NI6_TXINTERVAL          0xFFC03B98 /* Sets the NAK response timeout on Endpoint6 */
+#define USB_EP_NI6_RXTYPE              0xFFC03B9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define USB_EP_NI6_RXINTERVAL          0xFFC03BA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+#define USB_EP_NI6_TXCOUNT             0xFFC03BA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
+#define USB_EP_NI7_TXMAXP              0xFFC03BC0 /* Maximum packet size for Host Tx endpoint7 */
+#define USB_EP_NI7_TXCSR               0xFFC03BC4 /* Control Status register for endpoint7 */
+#define USB_EP_NI7_RXMAXP              0xFFC03BC8 /* Maximum packet size for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCSR               0xFFC03BCC /* Control Status register for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCOUNT             0xFFC03BD0 /* Number of bytes received in endpoint7 FIFO */
+#define USB_EP_NI7_TXTYPE              0xFFC03BD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define USB_EP_NI7_TXINTERVAL          0xFFC03BD8 /* Sets the NAK response timeout on Endpoint7 */
+#define USB_EP_NI7_RXTYPE              0xFFC03BDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define USB_EP_NI7_RXINTERVAL          0xFFC03BF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define USB_EP_NI7_TXCOUNT             0xFFC03BF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define USB_DMA_INTERRUPT              0xFFC03C00 /* Indicates pending interrupts for the DMA channels */
+#define USB_DMA0_CONTROL               0xFFC03C04 /* DMA master channel 0 configuration */
+#define USB_DMA0_ADDRLOW               0xFFC03C08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0_ADDRHIGH              0xFFC03C0C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0_COUNTLOW              0xFFC03C10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA0_COUNTHIGH             0xFFC03C14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA1_CONTROL               0xFFC03C24