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authorAneesh V <aneesh@ti.com>2011-07-21 09:10:04 -0400
committerU-Boot <uboot@aari01-12.(none)>2011-08-03 12:49:19 +0200
commitad577c8a487ac0ab277540f5fe2ea654d98d8e9f (patch)
treea869f688a4677fa63de49fce45a293f8a1df1d1d /arch/arm
parent469ec1e35354e45dce48299248c641367ed9e68a (diff)
downloadu-boot-linaro-stable-ad577c8a487ac0ab277540f5fe2ea654d98d8e9f.tar.gz
omap4: add OMAP4430 revision check
Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/cpu/armv7/omap4/board.c64
-rw-r--r--arch/arm/include/asm/arch-omap4/omap4.h29
-rw-r--r--arch/arm/include/asm/arch-omap4/sys_proto.h7
-rw-r--r--arch/arm/include/asm/armv7.h5
4 files changed, 97 insertions, 8 deletions
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 3fd6f8459..09861a99f 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -28,6 +28,7 @@
* MA 02111-1307 USA
*/
#include <common.h>
+#include <asm/armv7.h>
#include <asm/arch/cpu.h>
#include <asm/arch/sys_proto.h>
#include <asm/sizes.h>
@@ -35,6 +36,8 @@
DECLARE_GLOBAL_DATA_PTR;
+u32 *const omap4_revision = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV;
+
void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
{
int i;
@@ -72,6 +75,66 @@ static void set_mux_conf_regs(void)
}
}
+static u32 cortex_a9_rev(void)
+{
+
+ unsigned int rev;
+
+ /* Read Main ID Register (MIDR) */
+ asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
+
+ return rev;
+}
+
+static void init_omap4_revision(void)
+{
+ /*
+ * For some of the ES2/ES1 boards ID_CODE is not reliable:
+ * Also, ES1 and ES2 have different ARM revisions
+ * So use ARM revision for identification
+ */
+ unsigned int arm_rev = cortex_a9_rev();
+
+ switch (arm_rev) {
+ case MIDR_CORTEX_A9_R0P1:
+ *omap4_revision = OMAP4430_ES1_0;
+ break;
+ case MIDR_CORTEX_A9_R1P2:
+ switch (readl(CONTROL_ID_CODE)) {
+ case OMAP4_CONTROL_ID_CODE_ES2_0:
+ *omap4_revision = OMAP4430_ES2_0;
+ break;
+ case OMAP4_CONTROL_ID_CODE_ES2_1:
+ *omap4_revision = OMAP4430_ES2_1;
+ break;
+ case OMAP4_CONTROL_ID_CODE_ES2_2:
+ *omap4_revision = OMAP4430_ES2_2;
+ break;
+ default:
+ *omap4_revision = OMAP4430_ES2_0;
+ break;
+ }
+ break;
+ case MIDR_CORTEX_A9_R1P3:
+ *omap4_revision = OMAP4430_ES2_3;
+ break;
+ default:
+ *omap4_revision = OMAP4430_SILICON_ID_INVALID;
+ break;
+ }
+}
+
+void omap_rev_string(char *omap4_rev_string)
+{
+ u32 omap4_rev = omap_revision();
+ u32 omap4_variant = (omap4_rev & 0xFFFF0000) >> 16;
+ u32 major_rev = (omap4_rev & 0x00000F00) >> 8;
+ u32 minor_rev = (omap4_rev & 0x000000F0) >> 4;
+
+ sprintf(omap4_rev_string, "OMAP%x ES%x.%x", omap4_variant, major_rev,
+ minor_rev);
+}
+
/*
* Routine: s_init
* Description: Does early system init of watchdog, muxing, andclocks
@@ -88,6 +151,7 @@ static void set_mux_conf_regs(void)
*/
void s_init(void)
{
+ init_omap4_revision();
watchdog_init();
set_mux_conf_regs();
}
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
index a30bb332e..76b06c2fd 100644
--- a/arch/arm/include/asm/arch-omap4/omap4.h
+++ b/arch/arm/include/asm/arch-omap4/omap4.h
@@ -51,6 +51,15 @@
#define CONTROL_PADCONF_CORE (OMAP44XX_L4_CORE_BASE + 0x100000)
#define CONTROL_PADCONF_WKUP (OMAP44XX_L4_CORE_BASE + 0x31E000)
+/* CONTROL_ID_CODE */
+#define CONTROL_ID_CODE 0x4A002204
+
+#define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F
+#define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F
+#define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F
+#define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F
+#define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F
+
/* UART */
#define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000)
#define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000)
@@ -119,13 +128,17 @@ struct s32ktimer {
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4030D000
/* Temporary SRAM stack used while low level init is done */
-#define LOW_LEVEL_SRAM_STACK NON_SECURE_SRAM_END
-
-/*
- * OMAP4 real hardware:
- * TODO: Change this to the IDCODE in the hw regsiter
- */
-#define CPU_OMAP4430_ES10 1
-#define CPU_OMAP4430_ES20 2
+#define LOW_LEVEL_SRAM_STACK NON_SECURE_SRAM_END
+#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
+/* SRAM scratch space entries */
+#define OMAP4_SRAM_SCRATCH_OMAP4_REV SRAM_SCRATCH_SPACE_ADDR
+
+/* Silicon revisions */
+#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF
+#define OMAP4430_ES1_0 0x44300100
+#define OMAP4430_ES2_0 0x44300200
+#define OMAP4430_ES2_1 0x44300210
+#define OMAP4430_ES2_2 0x44300220
+#define OMAP4430_ES2_3 0x44300230
#endif
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 3624378f2..c10fa1870 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -40,6 +40,7 @@ void sr32(void *, u32, u32, u32);
u32 wait_on_value(u32, u32, void *, u32);
void sdelay(unsigned long);
void set_pl310_ctrl_reg(u32 val);
+void omap_rev_string(char *omap4_rev_string);
static inline u32 running_from_sdram(void)
{
@@ -88,4 +89,10 @@ static inline u32 omap4_hw_init_context(void)
#endif
}
+static inline u32 omap_revision(void)
+{
+ extern u32 *const omap4_revision;
+ return *omap4_revision;
+}
+
#endif
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
index 88b9c62dd..b5784d832 100644
--- a/arch/arm/include/asm/armv7.h
+++ b/arch/arm/include/asm/armv7.h
@@ -25,6 +25,11 @@
#define ARMV7_H
#include <linux/types.h>
+/* Cortex-A9 revisions */
+#define MIDR_CORTEX_A9_R0P1 0x410FC091
+#define MIDR_CORTEX_A9_R1P2 0x411FC092
+#define MIDR_CORTEX_A9_R1P3 0x411FC093
+
/* CCSIDR */
#define CCSIDR_LINE_SIZE_OFFSET 0
#define CCSIDR_LINE_SIZE_MASK 0x7