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authorVaibhav Hiremath <hvaibhav@ti.com>2012-03-08 17:15:47 +0530
committerTom Rini <trini@ti.com>2012-10-25 11:30:22 -0700
commit000820b5835c2b8b863af992b66dc973dc4bd202 (patch)
treef6abab9e0b1e696f8a21a8e7defbf6bd0fae0ee6 /arch/arm
parent3530a35d747508e98976a1d86a6d3f9b31cb3fd2 (diff)
downloadu-boot-linaro-stable-000820b5835c2b8b863af992b66dc973dc4bd202.tar.gz
am335x: Enable RTC 32K OSC clock
In order to support low power state, you must source kernel system timers to persistent clock, available across suspend/resume. In case of AM335x device, the only source we have is, RTC32K, available in wakeup/always-on domain. Having said that, during validation it has been observed that, RTC clock need couple of seconds delay to stabilize the RTC OSC clock; and such a huge delay is not acceptable in kernel especially during early init and also it will impact quick/fast boot use-cases. So, RTC32k OSC enable dependency has been shifted to SPL/first-bootloader. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/cpu/armv7/am33xx/board.c21
-rw-r--r--arch/arm/cpu/armv7/am33xx/clock.c6
-rw-r--r--arch/arm/include/asm/arch-am33xx/cpu.h15
-rw-r--r--arch/arm/include/asm/arch-am33xx/hardware.h4
4 files changed, 45 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 6de03fd65..772203fe5 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -116,11 +116,27 @@ static int read_eeprom(void)
return 0;
}
-/* UART Defines */
#ifdef CONFIG_SPL_BUILD
+/* UART Defines */
#define UART_RESET (0x1 << 1)
#define UART_CLK_RUNNING_MASK 0x1
#define UART_SMART_IDLE_EN (0x1 << 0x3)
+
+static void rtc32k_enable(void)
+{
+ struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE;
+
+ /*
+ * Unlock the RTC's registers. For more details please see the
+ * RTC_SS section of the TRM. In order to unlock we need to
+ * write these specific values (keys) in this order.
+ */
+ writel(0x83e70b13, &rtc->kick0r);
+ writel(0x95a4f1e0, &rtc->kick1r);
+
+ /* Enable the RTC 32K OSC by setting bits 3 and 6. */
+ writel((1 << 3) | (1 << 6), &rtc->osc);
+}
#endif
/*
@@ -154,6 +170,9 @@ void s_init(void)
/* Setup the PLLs and the clocks for the peripherals */
pll_init();
+ /* Enable RTC32K clock */
+ rtc32k_enable();
+
/* UART softreset */
u32 regVal;
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c
index 2b19506a3..f87085941 100644
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -44,6 +44,7 @@
const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
+const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC;
static void enable_interface_clocks(void)
{
@@ -153,6 +154,11 @@ static void enable_per_clocks(void)
writel(PRCM_MOD_EN, &cmper->spi0clkctrl);
while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN)
;
+
+ /* RTC */
+ writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl);
+ while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN)
+ ;
}
static void mpu_pll_config(void)
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index 6cfbef76a..819fd2f02 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -169,6 +169,12 @@ struct cm_dpll {
unsigned int clktimer2clk; /* offset 0x08 */
};
+/* Control Module RTC registers */
+struct cm_rtc {
+ unsigned int rtcclkctrl; /* offset 0x0 */
+ unsigned int clkstctrl; /* offset 0x4 */
+};
+
/* Watchdog timer registers */
struct wd_timer {
unsigned int resv1[4];
@@ -218,6 +224,15 @@ struct gptimer {
unsigned int tcar2; /* offset 0x58 */
};
+/* RTC Registers */
+struct rtc_regs {
+ unsigned int res[21];
+ unsigned int osc; /* offset 0x54 */
+ unsigned int res2[5];
+ unsigned int kick0r; /* offset 0x6c */
+ unsigned int kick1r; /* offset 0x70 */
+};
+
/* UART Registers */
struct uart_sys {
unsigned int resv1[21];
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h
index 62332f2de..5bd4bc872 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -61,6 +61,7 @@
#define CM_WKUP 0x44E00400
#define CM_DPLL 0x44E00500
#define CM_DEVICE 0x44E00700
+#define CM_RTC 0x44E00800
#define CM_CEFUSE 0x44E00A00
#define PRM_DEVICE 0x44E00F00
@@ -83,4 +84,7 @@
#define AM335X_CPSW_BASE 0x4A100000
#define AM335X_CPSW_MDIO_BASE 0x4A101000
+/* RTC base address */
+#define AM335X_RTC_BASE 0x44E3E000
+
#endif /* __AM33XX_HARDWARE_H */