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authorWolfgang Denk <wd@denx.de>2012-07-09 23:59:00 +0200
committerWolfgang Denk <wd@denx.de>2012-07-09 23:59:00 +0200
commitba662f8998f67b31d88bf3a78970ad8375e5644a (patch)
treec57438e4ed2f2ffbae4776152cac03d658c1ef35 /arch/arm
parent18277f7057c8e9b895aa4f8590969a57c4bce888 (diff)
parenta4dae631bfa848d8a0d1933583ed7e2f6a96cab3 (diff)
downloadu-boot-linaro-stable-ba662f8998f67b31d88bf3a78970ad8375e5644a.tar.gz
Merge branch 'master' of git://git.denx.de/u-boot-usb
* 'master' of git://git.denx.de/u-boot-usb: CONFIG: EXYNOS5: USB: Enable USB 2.0 on smdk5250 EXYNOS5: USB: Fix incorrect USB base addresses EXYNOS: Add power Enable/Disable for USB-EHCI USB: EXYNOS: Set USB 2.0 HOST Link mode EXYNOS5: Add structure for PMU registers EXYNOS5: Fix system register structure USB: EXYNOS: Incorporate EHCI review comments Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/cpu/armv7/exynos/power.c22
-rw-r--r--arch/arm/cpu/armv7/exynos/system.c22
-rw-r--r--arch/arm/include/asm/arch-exynos/cpu.h7
-rw-r--r--arch/arm/include/asm/arch-exynos/ehci.h (renamed from arch/arm/include/asm/arch-exynos/ehci-s5p.h)10
-rw-r--r--arch/arm/include/asm/arch-exynos/power.h626
-rw-r--r--arch/arm/include/asm/arch-exynos/system.h4
6 files changed, 684 insertions, 7 deletions
diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c
index c765304fd..4116781a3 100644
--- a/arch/arm/cpu/armv7/exynos/power.c
+++ b/arch/arm/cpu/armv7/exynos/power.c
@@ -52,3 +52,25 @@ void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable)
if (cpu_is_exynos4())
exynos4_mipi_phy_control(dev_index, enable);
}
+
+void exynos5_set_usbhost_phy_ctrl(unsigned int enable)
+{
+ struct exynos5_power *power =
+ (struct exynos5_power *)samsung_get_base_power();
+
+ if (enable) {
+ /* Enabling USBHOST_PHY */
+ setbits_le32(&power->usbhost_phy_control,
+ POWER_USB_HOST_PHY_CTRL_EN);
+ } else {
+ /* Disabling USBHOST_PHY */
+ clrbits_le32(&power->usbhost_phy_control,
+ POWER_USB_HOST_PHY_CTRL_EN);
+ }
+}
+
+void set_usbhost_phy_ctrl(unsigned int enable)
+{
+ if (cpu_is_exynos5())
+ exynos5_set_usbhost_phy_ctrl(enable);
+}
diff --git a/arch/arm/cpu/armv7/exynos/system.c b/arch/arm/cpu/armv7/exynos/system.c
index 6c34730b9..cc6ee031c 100644
--- a/arch/arm/cpu/armv7/exynos/system.c
+++ b/arch/arm/cpu/armv7/exynos/system.c
@@ -25,6 +25,28 @@
#include <asm/io.h>
#include <asm/arch/system.h>
+static void exynos5_set_usbhost_mode(unsigned int mode)
+{
+ struct exynos5_sysreg *sysreg =
+ (struct exynos5_sysreg *)samsung_get_base_sysreg();
+ unsigned int phy_cfg;
+
+ /* Setting USB20PHY_CONFIG register to USB 2.0 HOST link */
+ if (mode == USB20_PHY_CFG_HOST_LINK_EN) {
+ setbits_le32(&sysreg->usb20phy_cfg,
+ USB20_PHY_CFG_HOST_LINK_EN);
+ } else {
+ clrbits_le32(&sysreg->usb20phy_cfg,
+ USB20_PHY_CFG_HOST_LINK_EN);
+ }
+}
+
+void set_usbhost_mode(unsigned int mode)
+{
+ if (cpu_is_exynos5())
+ exynos5_set_usbhost_mode(mode);
+}
+
static void exynos4_set_system_display(void)
{
struct exynos4_sysreg *sysreg =
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index b1e22f2c1..0c341d431 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -46,6 +46,7 @@
#define EXYNOS4_USBOTG_BASE 0x12480000
#define EXYNOS4_MMC_BASE 0x12510000
#define EXYNOS4_SROMC_BASE 0x12570000
+#define EXYNOS4_USB_HOST_EHCI_BASE 0x12580000
#define EXYNOS4_USBPHY_BASE 0x125B0000
#define EXYNOS4_UART_BASE 0x13800000
#define EXYNOS4_ADC_BASE 0x13910000
@@ -69,10 +70,11 @@
#define EXYNOS5_DMC_CTRL_BASE 0x10DD0000
#define EXYNOS5_GPIO_PART1_BASE 0x11400000
#define EXYNOS5_MIPI_DSIM_BASE 0x11D00000
+#define EXYNOS5_USB_HOST_EHCI_BASE 0x12110000
+#define EXYNOS5_USBPHY_BASE 0x12130000
+#define EXYNOS5_USBOTG_BASE 0x12140000
#define EXYNOS5_MMC_BASE 0x12200000
#define EXYNOS5_SROMC_BASE 0x12250000
-#define EXYNOS5_USBOTG_BASE 0x12480000
-#define EXYNOS5_USBPHY_BASE 0x12480000
#define EXYNOS5_UART_BASE 0x12C00000
#define EXYNOS5_PWMTIMER_BASE 0x12DD0000
#define EXYNOS5_GPIO_PART2_BASE 0x13400000
@@ -159,6 +161,7 @@ SAMSUNG_BASE(swreset, SWRESET)
SAMSUNG_BASE(timer, PWMTIMER_BASE)
SAMSUNG_BASE(uart, UART_BASE)
SAMSUNG_BASE(usb_phy, USBPHY_BASE)
+SAMSUNG_BASE(usb_ehci, USB_HOST_EHCI_BASE)
SAMSUNG_BASE(usb_otg, USBOTG_BASE)
SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
SAMSUNG_BASE(power, POWER_BASE)
diff --git a/arch/arm/include/asm/arch-exynos/ehci-s5p.h b/arch/arm/include/asm/arch-exynos/ehci.h
index 68feb85ed..8aeff8ab2 100644
--- a/arch/arm/include/asm/arch-exynos/ehci-s5p.h
+++ b/arch/arm/include/asm/arch-exynos/ehci.h
@@ -1,5 +1,5 @@
/*
- * SAMSUNG S5P USB HOST EHCI Controller
+ * SAMSUNG EXYNOS USB HOST EHCI Controller
*
* Copyright (C) 2012 Samsung Electronics Co.Ltd
* Vivek Gautam <gautam.vivek@samsung.com>
@@ -20,8 +20,8 @@
* MA 02110-1301 USA
*/
-#ifndef __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__
-#define __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__
+#ifndef __ASM_ARM_ARCH_EHCI_H__
+#define __ASM_ARM_ARCH_EHCI_H__
#define CLK_24MHZ 5
@@ -43,7 +43,7 @@
#define EHCICTRL_ENAINCR16 (1 << 26)
/* Register map for PHY control */
-struct s5p_usb_phy {
+struct exynos_usb_phy {
unsigned int usbphyctrl0;
unsigned int usbphytune0;
unsigned int reserved1[2];
@@ -63,4 +63,4 @@ struct s5p_usb_phy {
/* Switch on the VBUS power. */
int board_usb_vbus_init(void);
-#endif /* __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__ */
+#endif /* __ASM_ARM_ARCH_EHCI_H__ */
diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h
index 6444fd04e..e5467e242 100644
--- a/arch/arm/include/asm/arch-exynos/power.h
+++ b/arch/arm/include/asm/arch-exynos/power.h
@@ -225,6 +225,628 @@ struct exynos4_power {
unsigned int gps_alive_status;
unsigned int gps_alive_option;
};
+
+struct exynos5_power {
+ unsigned int om_stat;
+ unsigned char res1[0x18];
+ unsigned int rtc_clko_sel;
+ unsigned int gnss_rtc_out_ctrl;
+ unsigned char res2[0x1dc];
+ unsigned int central_seq_configuration;
+ unsigned int central_seq_status;
+ unsigned int central_seq_option;
+ unsigned char res3[0x14];
+ unsigned int seq_transition0;
+ unsigned int seq_transition1;
+ unsigned int seq_transition2;
+ unsigned int seq_transition3;
+ unsigned int seq_transition4;
+ unsigned int seq_transition5;
+ unsigned int seq_transition6;
+ unsigned int seq_transition7;
+ unsigned int central_seq_dmc_configuration;
+ unsigned int central_seq_dmc_status;
+ unsigned int central_seq_dmc_option;
+ unsigned char res4[0x14];
+ unsigned int seq_dmc_transition0;
+ unsigned int seq_dmc_transition1;
+ unsigned int seq_dmc_transition2;
+ unsigned int seq_dmc_transition3;
+ unsigned int seq_dmc_transition4;
+ unsigned int seq_dmc_transition5;
+ unsigned int seq_dmc_transition6;
+ unsigned int seq_dmc_transition7;
+ unsigned char res5[0x180];
+ unsigned int swreset;
+ unsigned int rst_stat;
+ unsigned int automatic_wdt_reset_disable;
+ unsigned int mask_wdt_reset_request;
+ unsigned int mask_wreset_request;
+ unsigned char res6[0xec];
+ unsigned int reset_sequencer_configuration;
+ unsigned int reset_sequencer_status;
+ unsigned int reset_sequencer_option;
+ unsigned char res7[0xf4];
+ unsigned int wakeup_stat;
+ unsigned int eint_wakeup_mask;
+ unsigned int wakeup_mask;
+ unsigned int wakeup_interrupt;
+ unsigned char res8[0x10];
+ unsigned int wakeup_stat_dmc;
+ unsigned int eint_wakeup_mask_dmc;
+ unsigned int wakeup_mask_dmc;
+ unsigned int wakeup_interrupt_dmc;
+ unsigned char res9[0xd0];
+ unsigned int hdmi_phy_control;
+ unsigned int usbdrd_phy_control;
+ unsigned int usbhost_phy_control;
+ unsigned int efnand_phy_control;
+ unsigned int mipi_phy0_control;
+ unsigned int mipi_phy1_control;
+ unsigned int adc_phy_control;
+ unsigned int mtcadc_phy_control;
+ unsigned int dptx_phy_control;
+ unsigned int sata_phy_control;
+ unsigned char res10[0xd8];
+ unsigned int inform0;
+ unsigned int inform1;
+ unsigned int inform2;
+ unsigned int inform3;
+ unsigned int sysip_dat0;
+ unsigned int sysip_dat1;
+ unsigned int sysip_dat2;
+ unsigned int sysip_dat3;
+ unsigned char res11[0xe0];
+ unsigned int pmu_spare0;
+ unsigned int pmu_spare1;
+ unsigned int pmu_spare2;
+ unsigned int pmu_spare3;
+ unsigned char res12[0x70];
+ unsigned int irom_data_reg0;
+ unsigned int irom_data_reg1;
+ unsigned int irom_data_reg2;
+ unsigned int irom_data_reg3;
+ unsigned char res13[0x70];
+ unsigned int pmu_debug;
+ unsigned char res14[0x5fc];
+ unsigned int arm_core0_sys_pwr_reg;
+ unsigned int dis_irq_arm_core0_local_sys_pwr_reg;
+ unsigned int dis_irq_arm_core0_central_sys_pwr_reg;
+ unsigned char res15[0x4];
+ unsigned int arm_core1_sys_pwr_reg;
+ unsigned int dis_irq_arm_core1_local_sys_pwr_reg;
+ unsigned int dis_irq_arm_core1_central_sys_pwr_reg;
+ unsigned char res16[0x24];
+ unsigned int fsys_arm_sys_pwr_reg;
+ unsigned int dis_irq_fsys_arm_local_sys_pwr_reg;
+ unsigned int dis_irq_fsys_arm_central_sys_pwr_reg;
+ unsigned char res17[0x4];
+ unsigned int isp_arm_sys_pwr_reg;
+ unsigned int dis_irq_isp_arm_local_sys_pwr_reg;
+ unsigned int dis_irq_isp_arm_central_sys_pwr_reg;
+ unsigned char res18[0x24];
+ unsigned int arm_common_sys_pwr_reg;
+ unsigned char res19[0x3c];
+ unsigned int arm_l2_sys_pwr_reg;
+ unsigned char res20[0x3c];
+ unsigned int cmu_aclkstop_sys_pwr_reg;
+ unsigned int cmu_sclkstop_sys_pwr_reg;
+ unsigned char res21[0x4];
+ unsigned int cmu_reset_sys_pwr_reg;
+ unsigned char res22[0x10];
+ unsigned int cmu_aclkstop_dmc_sys_pwr_reg;
+ unsigned int cmu_sclkstop_dmc_sys_pwr_reg;
+ unsigned char res23[0x4];
+ unsigned int cmu_reset_dmc_sys_pwr_reg;
+ unsigned char res24[0x8];
+ unsigned int ddrphy_dlllock_sys_pwr_reg;
+ unsigned char res25[0x4];
+ unsigned int apll_sysclk_sys_pwr_reg;
+ unsigned int mpll_sysclk_sys_pwr_reg;
+ unsigned int vpll_sysclk_sys_pwr_reg;
+ unsigned int epll_sysclk_sys_pwr_reg;
+ unsigned int bpll_sysclk_sys_pwr_reg;
+ unsigned int cpll_sysclk_sys_pwr_reg;
+ unsigned int gpll_sysclk_sys_pwr_reg;
+ unsigned char res26[0x8];
+ unsigned int mplluser_sysclk_sys_pwr_reg;
+ unsigned char res27[0x8];
+ unsigned int bplluser_sysclk_sys_pwr_reg;
+ unsigned char res28[0xc];
+ unsigned int top_bus_sys_pwr_reg;
+ unsigned int top_retention_sys_pwr_reg;
+ unsigned int top_pwr_sys_pwr_reg;
+ unsigned char res29[0x4];
+ unsigned int top_bus_dmc_sys_pwr_reg;
+ unsigned int top_retention_dmc_sys_pwr_reg;
+ unsigned int top_pwr_dmc_sys_pwr_reg;
+ unsigned char res30[0x4];
+ unsigned int logic_reset_sys_pwr_reg;
+ unsigned int oscclk_gate_sys_pwr_reg;
+ unsigned char res31[0x8];
+ unsigned int logic_reset_dmc_sys_pwr_reg;
+ unsigned int oscclk_gate_dmc_sys_pwr_reg;
+ unsigned char res32[0x8];
+ unsigned int usbotg_mem_sys_pwr_reg;
+ unsigned char res33[0x4];
+ unsigned int g2d_mem_sys_pwr_reg;
+ unsigned int usbdrd_mem_sys_pwr_reg;
+ unsigned int efnand_mem_sys_pwr_reg;
+ unsigned int cssys_mem_sys_pwr_reg;
+ unsigned int secss_mem_sys_pwr_reg;
+ unsigned int rotator_mem_sys_pwr_reg;
+ unsigned int intram_mem_sys_pwr_reg;
+ unsigned int introm_mem_sys_pwr_reg;
+ unsigned int jpeg_mem_sys_pwr_reg;
+ unsigned int hsi_mem_sys_pwr_reg;
+ unsigned char res34[0x4];
+ unsigned int mcuiop_mem_sys_pwr_reg;
+ unsigned char res35[0x4];
+ unsigned int sata_mem_sys_pwr_reg;
+ unsigned int pad_retention_dram_sys_pwr_reg;
+ unsigned int pad_retention_mau_sys_pwr_reg;
+ unsigned int pad_retention_jtag_sys_pwr_reg;
+ unsigned char res36[0xc];
+ unsigned int pad_retention_mmc2_sys_pwr_reg;
+ unsigned int pad_retention_mmc3_sys_pwr_reg;
+ unsigned int pad_retention_gpio_sys_pwr_reg;
+ unsigned int pad_retention_uart_sys_pwr_reg;
+ unsigned int pad_retention_mmc0_sys_pwr_reg;
+ unsigned int pad_retention_mmc1_sys_pwr_reg;
+ unsigned int pad_retention_ebia_sys_pwr_reg;
+ unsigned int pad_retention_ebib_sys_pwr_reg;
+ unsigned int pad_retention_spi_sys_pwr_reg;
+ unsigned int pad_retention_gpio_dmc_sys_pwr_reg;
+ unsigned int pad_isolation_sys_pwr_reg;
+ unsigned char res37[0xc];
+ unsigned int pad_isolation_dmc_sys_pwr_reg;
+ unsigned char res38[0xc];
+ unsigned int pad_alv_sel_sys_pwr_reg;
+ unsigned char res39[0x20];
+ unsigned int xxti_sys_pwr_reg;
+ unsigned char res40[0x38];
+ unsigned int ext_regulator_sys_pwr_reg;
+ unsigned char res41[0x3c];
+ unsigned int gpio_mode_sys_pwr_reg;
+ unsigned char res42[0x1c];
+ unsigned int gpio_mode_dmc_sys_pwr_reg;
+ unsigned char res43[0x1c];
+ unsigned int gpio_mode_mau_sys_pwr_reg;
+ unsigned int top_asb_reset_sys_pwr_reg;
+ unsigned int top_asb_isolation_sys_pwr_reg;
+ unsigned char res44[0xb4];
+ unsigned int gscl_sys_pwr_reg;
+ unsigned int isp_sys_pwr_reg;
+ unsigned int mfc_sys_pwr_reg;
+ unsigned int g3d_sys_pwr_reg;
+ unsigned char res45[0x4];
+ unsigned int disp1_sys_pwr_reg;
+ unsigned int mau_sys_pwr_reg;
+ unsigned char res46[0x64];
+ unsigned int cmu_clkstop_gscl_sys_pwr_reg;
+ unsigned int cmu_clkstop_isp_sys_pwr_reg;
+ unsigned int cmu_clkstop_mfc_sys_pwr_reg;
+ unsigned int cmu_clkstop_g3d_sys_pwr_reg;
+ unsigned char res47[0x4];
+ unsigned int cmu_clkstop_disp1_sys_pwr_reg;
+ unsigned int cmu_clkstop_mau_sys_pwr_reg;
+ unsigned char res48[0x24];
+ unsigned int cmu_sysclk_gscl_sys_pwr_reg;
+ unsigned int cmu_sysclk_isp_sys_pwr_reg;
+ unsigned int cmu_sysclk_mfc_sys_pwr_reg;
+ unsigned int cmu_sysclk_g3d_sys_pwr_reg;
+ unsigned char res49[0x4];
+ unsigned int cmu_sysclk_disp1_sys_pwr_reg;
+ unsigned int cmu_sysclk_mau_sys_pwr_reg;
+ unsigned char res50[0xa4];
+ unsigned int cmu_reset_gscl_sys_pwr_reg;
+ unsigned int cmu_reset_isp_sys_pwr_reg;
+ unsigned int cmu_reset_mfc_sys_pwr_reg;
+ unsigned int cmu_reset_g3d_sys_pwr_reg;
+ unsigned char res51[0x4];
+ unsigned int cmu_reset_disp1_sys_pwr_reg;
+ unsigned int cmu_reset_mau_sys_pwr_reg;
+ unsigned char res52[0xa64];
+ unsigned int arm_core0_configuration;
+ unsigned int arm_core0_status;
+ unsigned int arm_core0_option;
+ unsigned char res53[0x14];
+ unsigned int dis_irq_arm_core0_local_configuration;
+ unsigned int dis_irq_arm_core0_local_status;
+ unsigned int dis_irq_arm_core0_local_option;
+ unsigned char res54[0x14];
+ unsigned int dis_irq_arm_core0_central_configuration;
+ unsigned int dis_irq_arm_core0_central_status;
+ unsigned int dis_irq_arm_core0_central_option;
+ unsigned char res55[0x34];
+ unsigned int arm_core1_configuration;
+ unsigned int arm_core1_status;
+ unsigned int arm_core1_option;
+ unsigned char res56[0x14];
+ unsigned int dis_irq_arm_core1_local_configuration;
+ unsigned int dis_irq_arm_core1_local_status;
+ unsigned int dis_irq_arm_core1_local_option;
+ unsigned char res57[0x14];
+ unsigned int dis_irq_arm_core1_central_configuration;
+ unsigned int dis_irq_arm_core1_central_status;
+ unsigned int dis_irq_arm_core1_central_option;
+ unsigned char res58[0x134];
+ unsigned int fsys_arm_configuration;
+ unsigned int fsys_arm_status;
+ unsigned int fsys_arm_option;
+ unsigned char res59[0x14];
+ unsigned int dis_irq_fsys_arm_local_configuration;
+ unsigned int dis_irq_fsys_arm_local_status;
+ unsigned int dis_irq_fsys_arm_local_option;
+ unsigned char res60[0x14];
+ unsigned int dis_irq_fsys_arm_central_configuration;
+ unsigned int dis_irq_fsys_arm_central_status;
+ unsigned int dis_irq_fsys_arm_central_option;
+ unsigned char res61[0x34];
+ unsigned int isp_arm_configuration;
+ unsigned int isp_arm_status;
+ unsigned int isp_arm_option;
+ unsigned char res62[0x14];
+ unsigned int dis_irq_isp_arm_local_configuration;
+ unsigned int dis_irq_isp_arm_local_status;
+ unsigned int dis_irq_isp_arm_local_option;
+ unsigned char res63[0x14];
+ unsigned int dis_irq_isp_arm_central_configuration;
+ unsigned int dis_irq_isp_arm_central_status;
+ unsigned int dis_irq_isp_arm_central_option;
+ unsigned char res64[0x134];
+ unsigned int arm_common_configuration;
+ unsigned int arm_common_status;
+ unsigned int arm_common_option;
+ unsigned char res65[0x1f4];
+ unsigned int arm_l2_configuration;
+ unsigned int arm_l2_status;
+ unsigned int arm_l2_option;
+ unsigned char res66[0x1f4];
+ unsigned int cmu_aclkstop_configuration;
+ unsigned int cmu_aclkstop_status;
+ unsigned int cmu_aclkstop_option;
+ unsigned char res67[0x14];
+ unsigned int cmu_sclkstop_configuration;
+ unsigned int cmu_sclkstop_status;
+ unsigned int cmu_sclkstop_option;
+ unsigned char res68[0x34];
+ unsigned int cmu_reset_configuration;
+ unsigned int cmu_reset_status;
+ unsigned int cmu_reset_option;
+ unsigned char res69[0x94];
+ unsigned int cmu_aclkstop_dmc_configuration;
+ unsigned int cmu_aclkstop_dmc_status;
+ unsigned int cmu_aclkstop_dmc_option;
+ unsigned char res70[0x14];
+ unsigned int cmu_sclkstop_dmc_configuration;
+ unsigned int cmu_sclkstop_dmc_status;
+ unsigned int cmu_sclkstop_dmc_option;
+ unsigned char res71[0x34];
+ unsigned int cmu_reset_dmc_configuration;
+ unsigned int cmu_reset_dmc_status;
+ unsigned int cmu_reset_dmc_option;
+ unsigned char res72[0x54];
+ unsigned int ddrphy_dlllock_configuration;
+ unsigned int ddrphy_dlllock_status;
+ unsigned int ddrphy_dlllock_option;
+ unsigned char res73[0x34];
+ unsigned int apll_sysclk_configuration;
+ unsigned int apll_sysclk_status;
+ unsigned int apll_sysclk_option;
+ unsigned char res74[0x18];
+ unsigned int mpll_sysclk_status;
+ unsigned int mpll_sysclk_option;
+ unsigned char res75[0x14];
+ unsigned int vpll_sysclk_configuration;
+ unsigned int vpll_sysclk_status;
+ unsigned int vpll_sysclk_option;
+ unsigned char res76[0x14];
+ unsigned int epll_sysclk_configuration;
+ unsigned int epll_sysclk_status;
+ unsigned int epll_sysclk_option;
+ unsigned char res77[0x14];
+ unsigned int bpll_sysclk_configuration;
+ unsigned int bpll_sysclk_status;
+ unsigned int bpll_sysclk_option;
+ unsigned char res78[0x14];
+ unsigned int cpll_sysclk_configuration;
+ unsigned int cpll_sysclk_status;
+ unsigned int cpll_sysclk_option;
+ unsigned char res79[0x14];
+ unsigned int gpll_sysclk_configuration;
+ unsigned int gpll_sysclk_status;
+ unsigned int gpll_sysclk_option;
+ unsigned char res80[0x54];
+ unsigned int mplluser_sysclk_configuration;
+ unsigned int mplluser_sysclk_status;
+ unsigned int mplluser_sysclk_option;
+ unsigned char res81[0x54];
+ unsigned int bplluser_sysclk_configuration;
+ unsigned int bplluser_sysclk_status;
+ unsigned int bplluser_sysclk_option;
+ unsigned char res82[0x74];
+ unsigned int top_bus_configuration;
+ unsigned int top_bus_status;
+ unsigned int top_bus_option;
+ unsigned char res83[0x14];
+ unsigned int top_retention_configuration;
+ unsigned int top_retention_status;
+ unsigned int top_retention_option;
+ unsigned char res84[0x14];
+ unsigned int top_pwr_configuration;
+ unsigned int top_pwr_status;
+ unsigned int top_pwr_option;
+ unsigned char res85[0x34];
+ unsigned int top_bus_dmc_configuration;
+ unsigned int top_bus_dmc_status;
+ unsigned int top_bus_dmc_option;
+ unsigned char res86[0x14];
+ unsigned int top_retention_dmc_configuration;
+ unsigned int top_retention_dmc_status;
+ unsigned int top_retention_dmc_option;
+ unsigned char res87[0x14];
+ unsigned int top_pwr_dmc_configuration;
+ unsigned int top_pwr_dmc_status;
+ unsigned int top_pwr_dmc_option;
+ unsigned char res88[0x34];
+ unsigned int logic_reset_configuration;
+ unsigned int logic_reset_status;
+ unsigned int logic_reset_option;
+ unsigned char res89[0x14];
+ unsigned int oscclk_gate_configuration;
+ unsigned int oscclk_gate_status;
+ unsigned int oscclk_gate_option;
+ unsigned char res90[0x54];
+ unsigned int logic_reset_dmc_configuration;
+ unsigned int logic_reset_dmc_status;
+ unsigned int logic_reset_dmc_option;
+ unsigned char res91[0x14];
+ unsigned int oscclk_gate_dmc_configuration;
+ unsigned int oscclk_gate_dmc_status;
+ unsigned int oscclk_gate_dmc_option;
+ unsigned char res92[0x54];
+ unsigned int usbotg_mem_configuration;
+ unsigned int usbotg_mem_status;
+ unsigned int usbotg_mem_option;
+ unsigned char res93[0x34];
+ unsigned int g2d_mem_configuration;
+ unsigned int g2d_mem_status;
+ unsigned int g2d_mem_option;
+ unsigned char res94[0x14];
+ unsigned int usbdrd_mem_configuration;
+ unsigned int usbdrd_mem_status;
+ unsigned int usbdrd_mem_option;
+ unsigned char res95[0x14];
+ unsigned int efnand_mem_configuration;
+ unsigned int efnand_mem_status;
+ unsigned int efnand_mem_option;
+ unsigned char res96[0x14];
+ unsigned int cssys_mem_configuration;
+ unsigned int cssys_mem_status;
+ unsigned int cssys_mem_option;
+ unsigned char res97[0x14];
+ unsigned int secss_mem_configuration;
+ unsigned int secss_mem_status;
+ unsigned int secss_mem_option;
+ unsigned char res98[0x14];
+ unsigned int rotator_mem_configuration;
+ unsigned int rotator_mem_status;
+ unsigned int rotator_mem_option;
+ unsigned char res99[0x14];
+ unsigned int intram_mem_configuration;
+ unsigned int intram_mem_status;
+ unsigned int intram_mem_option;
+ unsigned char res100[0x14];
+ unsigned int introm_mem_configuration;
+ unsigned int introm_mem_status;
+ unsigned int introm_mem_option;
+ unsigned char res101[0x14];
+ unsigned int jpeg_mem_configuration;
+ unsigned int jpeg_mem_status;
+ unsigned int jpeg_mem_option;
+ unsigned char res102[0x14];
+ unsigned int hsi_mem_configuration;
+ unsigned int hsi_mem_status;
+ unsigned int hsi_mem_option;
+ unsigned char res103[0x34];
+ unsigned int mcuiop_mem_configuration;
+ unsigned int mcuiop_mem_status;
+ unsigned int mcuiop_mem_option;
+ unsigned char res104[0x14];
+ unsigned int sata_mem_configuration;
+ unsigned int sata_mem_status;
+ unsigned int sata_mem_option;
+ unsigned char res105[0x34];
+ unsigned int pad_retention_dram_configuration;
+ unsigned int pad_retention_dram_status;
+ unsigned int pad_retention_dram_option;
+ unsigned char res106[0x14];
+ unsigned int pad_retention_mau_configuration;
+ unsigned int pad_retention_mau_status;
+ unsigned int pad_retention_mau_option;
+ unsigned char res107[0x14];
+ unsigned int pad_retention_jtag_configuration;
+ unsigned int pad_retention_jtag_status;
+ unsigned int pad_retention_jtag_option;
+ unsigned char res108[0x74];
+ unsigned int pad_retention_mmc2_configuration;
+ unsigned int pad_retention_mmc2_status;
+ unsigned int pad_retention_mmc2_option;
+ unsigned char res109[0x14];
+ unsigned int pad_retention_mmc3_configuration;
+ unsigned int pad_retention_mmc3_status;
+ unsigned int pad_retention_mmc3_option;
+ unsigned char res110[0x14];
+ unsigned int pad_retention_gpio_configuration;
+ unsigned int pad_retention_gpio_status;
+ unsigned int pad_retention_gpio_option;
+ unsigned char res111[0x14];
+ unsigned int pad_retention_uart_configuration;
+ unsigned int pad_retention_uart_status;
+ unsigned int pad_retention_uart_option;
+ unsigned char res112[0x14];
+ unsigned int pad_retention_mmc0_configuration;
+ unsigned int pad_retention_mmc0_status;
+ unsigned int pad_retention_mmc0_option;
+ unsigned char res113[0x14];
+ unsigned int pad_retention_mmc1_configuration;
+ unsigned int pad_retention_mmc1_status;
+ unsigned int pad_retention_mmc1_option;
+ unsigned char res114[0x14];
+ unsigned int pad_retention_ebia_configuration;
+ unsigned int pad_retention_ebia_status;
+ unsigned int pad_retention_ebia_option;
+ unsigned char res115[0x14];
+ unsigned int pad_retention_ebib_configuration;
+ unsigned int pad_retention_ebib_status;
+ unsigned int pad_retention_ebib_option;
+ unsigned char res116[0x14];
+ unsigned int pad_retention_spi_configuration;
+ unsigned int pad_retention_spi_status;
+ unsigned int pad_retention_spi_option;
+ unsigned char res117[0x14];
+ unsigned int pad_retention_gpio_dmc_configuration;
+ unsigned int pad_retention_gpio_dmc_status;
+ unsigned int pad_retention_gpio_dmc_option;
+ unsigned char res118[0x14];
+ unsigned int pad_isolation_configuration;
+ unsigned int pad_isolation_status;
+ unsigned int pad_isolation_option;
+ unsigned char res119[0x74];
+ unsigned int pad_isolation_dmc_configuration;
+ unsigned int pad_isolation_dmc_status;
+ unsigned int pad_isolation_dmc_option;
+ unsigned char res120[0x74];
+ unsigned int pad_alv_sel_configuration;
+ unsigned int pad_alv_sel_status;
+ unsigned int pad_alv_sel_option0;
+ unsigned int ps_hold_control;
+ unsigned char res130[0x110];
+ unsigned int xxti_configuration;
+ unsigned int xxti_status;
+ unsigned int xxti_option;
+ unsigned char res131[0x10];
+ unsigned int xxti_duration3;
+ unsigned char res132[0x1c0];
+ unsigned int ext_regulator_configuration;
+ unsigned int ext_regulator_status;
+ unsigned int ext_regulator_option;
+ unsigned char res133[0x10];
+ unsigned int ext_regulator_duration3;
+ unsigned char res134[0x1e0];
+ unsigned int gpio_mode_configuration;
+ unsigned int gpio_mode_status;
+ unsigned int gpio_mode_option;
+ unsigned char res135[0xf4];
+ unsigned int gpio_mode_dmc_configuration;
+ unsigned int gpio_mode_dmc_status;
+ unsigned int gpio_mode_dmc_option;
+ unsigned char res136[0xd4];
+ unsigned int gpio_mode_mau_configuration;
+ unsigned int gpio_mode_mau_status;
+ unsigned int gpio_mode_mau_option;
+ unsigned char res137[0x14];
+ unsigned int top_asb_reset_configuration;
+ unsigned int top_asb_reset_status;
+ unsigned int top_asb_reset_option;
+ unsigned char res138[0x14];
+ unsigned int top_asb_isolation_configuration;
+ unsigned int top_asb_isolation_status;
+ unsigned int top_asb_isolation_option;
+ unsigned char res139[0x5d4];
+ unsigned int gscl_configuration;
+ unsigned int gscl_status;
+ unsigned int gscl_option;
+ unsigned char res140[0x14];
+ unsigned int isp_configuration;
+ unsigned int isp_status;
+ unsigned int isp_option;
+ unsigned char res141[0x14];
+ unsigned int mfc_configuration;
+ unsigned int mfc_status;
+ unsigned int mfc_option;
+ unsigned char res142[0x14];
+ unsigned int g3d_configuration;
+ unsigned int g3d_status;
+ unsigned int g3d_option;
+ unsigned char res143[0x34];
+ unsigned int disp1_configuration;
+ unsigned int disp1_status;
+ unsigned int disp1_option;
+ unsigned char res144[0x14];
+ unsigned int mau_configuration;
+ unsigned int mau_status;
+ unsigned int mau_option;
+ unsigned char res145[0x334];
+ unsigned int cmu_clkstop_gscl_configuration;
+ unsigned int cmu_clkstop_gscl_status;
+ unsigned int cmu_clkstop_gscl_option;
+ unsigned char res146[0x14];
+ unsigned int cmu_clkstop_isp_configuration;
+ unsigned int cmu_clkstop_isp_status;
+ unsigned int cmu_clkstop_isp_option;
+ unsigned char res147[0x14];
+ unsigned int cmu_clkstop_mfc_configuration;
+ unsigned int cmu_clkstop_mfc_status;
+ unsigned int cmu_clkstop_mfc_option;
+ unsigned char res148[0x14];
+ unsigned int cmu_clkstop_g3d_configuration;
+ unsigned int cmu_clkstop_g3d_status;
+ unsigned int cmu_clkstop_g3d_option;
+ unsigned char res149[0x34];
+ unsigned int cmu_clkstop_disp1_configuration;
+ unsigned int cmu_clkstop_disp1_status;
+ unsigned int cmu_clkstop_disp1_option;
+ unsigned char res150[0x14];
+ unsigned int cmu_clkstop_mau_configuration;
+ unsigned int cmu_clkstop_mau_status;
+ unsigned int cmu_clkstop_mau_option;
+ unsigned char res151[0x134];
+ unsigned int cmu_sysclk_gscl_configuration;
+ unsigned int cmu_sysclk_gscl_status;
+ unsigned int cmu_sysclk_gscl_option;
+ unsigned char res152[0x18];
+ unsigned int cmu_sysclk_isp_status;
+ unsigned int cmu_sysclk_isp_option;
+ unsigned char res153[0x18];
+ unsigned int cmu_sysclk_mfc_status;
+ unsigned int cmu_sysclk_mfc_option;
+ unsigned char res154[0x18];
+ unsigned int cmu_sysclk_g3d_status;
+ unsigned int cmu_sysclk_g3d_option;
+ unsigned char res155[0x38];
+ unsigned int cmu_sysclk_disp1_status;
+ unsigned int cmu_sysclk_disp1_option;
+ unsigned char res156[0x18];
+ unsigned int cmu_sysclk_mau_status;
+ unsigned int cmu_sysclk_mau_option;
+ unsigned char res157[0x534];
+ unsigned int cmu_reset_gscl_configuration;
+ unsigned int cmu_reset_gscl_status;
+ unsigned int cmu_reset_gscl_option;
+ unsigned char res158[0x14];
+ unsigned int cmu_reset_isp_configuration;
+ unsigned int cmu_reset_isp_status;
+ unsigned int cmu_reset_isp_option;
+ unsigned char res159[0x14];
+ unsigned int cmu_reset_mfc_configuration;
+ unsigned int cmu_reset_mfc_status;
+ unsigned int cmu_reset_mfc_option;
+ unsigned char res160[0x14];
+ unsigned int cmu_reset_g3d_configuration;
+ unsigned int cmu_reset_g3d_status;
+ unsigned int cmu_reset_g3d_option;
+ unsigned char res161[0x34];
+ unsigned int cmu_reset_disp1_configuration;
+ unsigned int cmu_reset_disp1_status;
+ unsigned int cmu_reset_disp1_option;
+ unsigned char res162[0x14];
+ unsigned int cmu_reset_mau_configuration;
+ unsigned int cmu_reset_mau_status;
+ unsigned int cmu_reset_mau_option;
+ unsigned char res163[0x24];
+};
#endif /* __ASSEMBLY__ */
void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable);
@@ -233,4 +855,8 @@ void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable);
#define EXYNOS_MIPI_PHY_SRESETN (1 << 1)
#define EXYNOS_MIPI_PHY_MRESETN (1 << 2)
+void set_usbhost_phy_ctrl(unsigned int enable);
+
+#define POWER_USB_HOST_PHY_CTRL_EN (1 << 0)
+#define POWER_USB_HOST_PHY_CTRL_DISABLE (0 << 0)
#endif
diff --git a/arch/arm/include/asm/arch-exynos/system.h b/arch/arm/include/asm/arch-exynos/system.h
index c85f949da..42e1d21e5 100644
--- a/arch/arm/include/asm/arch-exynos/system.h
+++ b/arch/arm/include/asm/arch-exynos/system.h
@@ -42,12 +42,16 @@ struct exynos5_sysreg {
unsigned int reserved;
unsigned int ispblk_cfg;
unsigned int usb20phy_cfg;
+ unsigned char res2[0x29c];
unsigned int mipi_dphy;
unsigned int dptx_dphy;
unsigned int phyclk_sel;
};
#endif
+#define USB20_PHY_CFG_HOST_LINK_EN (1 << 0)
+
+void set_usbhost_mode(unsigned int mode);
void set_system_display_ctrl(void);
#endif /* _EXYNOS4_SYSTEM_H */