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authorSteve Sakoman <steve@sakoman.com>2012-05-30 07:46:00 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-07-07 14:07:35 +0200
commitf2b37a6533cfc45af53cdd1f5c721a6f64c0d7da (patch)
treed81603e16d16d6edb8174fe1396da37f62b8b1ad /arch/arm/include
parentad0878a7492928696a93245c1f9190d51eebe549 (diff)
downloadu-boot-linaro-stable-f2b37a6533cfc45af53cdd1f5c721a6f64c0d7da.tar.gz
omap: am33xx: accomodate input clocks other than 24 Mhz
The PLL setup values currently assume a 24 Mhz input clock. This patch uses V_OSCK from the board config file to support boards with different input clock rates. Signed-off-by: Steve Sakoman <steve@sakoman.com>
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/arch-am33xx/clocks_am33xx.h10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
index abc5b6b41..d748dd278 100644
--- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
@@ -19,16 +19,16 @@
#ifndef _CLOCKS_AM33XX_H_
#define _CLOCKS_AM33XX_H_
-#define OSC 24
+#define OSC (V_OSCK/1000000)
/* MAIN PLL Fdll = 550 MHZ, */
#define MPUPLL_M 550
-#define MPUPLL_N 23
+#define MPUPLL_N (OSC-1)
#define MPUPLL_M2 1
/* Core PLL Fdll = 1 GHZ, */
#define COREPLL_M 1000
-#define COREPLL_N 23
+#define COREPLL_N (OSC-1)
#define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */
#define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */
@@ -40,13 +40,13 @@
* For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
*/
#define PERPLL_M 960
-#define PERPLL_N 23
+#define PERPLL_N (OSC-1)
#define PERPLL_M2 5
/* DDR Freq is 266 MHZ for now */
/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
#define DDRPLL_M 266
-#define DDRPLL_N 23
+#define DDRPLL_N (OSC-1)
#define DDRPLL_M2 1
extern void pll_init(void);