diff options
| author | Stefano Babic <sbabic@denx.de> | 2010-11-11 15:38:02 +0100 |
|---|---|---|
| committer | Sandeep Paulraj <s-paulraj@ti.com> | 2010-11-28 20:17:35 -0500 |
| commit | d73a8a1b8ce831f9b869960de682ca7d48d49f9d (patch) | |
| tree | 2e7193e79e02d572190a099c2d8684c7b911f367 /arch/arm/include | |
| parent | a131148efe21e92528a146f600613a9b89abdfdc (diff) | |
da850: Enable SPI Flash
The patch was already posted to the arago project,
but not yet to mainline. It allows to save environment into
the spi flash. Tested on LogiPD tmdxl138.
Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Detlev Zundev <dzu@denx.de>
CC: Ben Gardiner <bengardiner@nanometrics.ca>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-davinci/hardware.h | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index 2a460b55d..21b20763a 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -133,7 +133,8 @@ typedef volatile unsigned int * dv_reg_p; #define DAVINCI_PSC1_BASE 0x01e27000 #define DAVINCI_SPI0_BASE 0x01c41000 #define DAVINCI_USB_OTG_BASE 0x01e00000 -#define DAVINCI_SPI1_BASE 0x01e12000 +#define DAVINCI_SPI1_BASE (cpu_is_da830() ? \ + 0x01e12000 : 0x01f0e000) #define DAVINCI_GPIO_BASE 0x01e26000 #define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01e23000 #define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000 @@ -364,6 +365,9 @@ struct davinci_pllc_regs { #define davinci_pllc_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE) #define DAVINCI_PLLC_DIV_MASK 0x1f +#define ASYNC3 get_async3_src() +#define PLL1_SYSCLK2 ((1 << 16) | 0x2) +#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? 2 : ASYNC3) /* Clock IDs */ enum davinci_clk_ids { DAVINCI_SPI0_CLKID = 2, @@ -458,6 +462,12 @@ static inline int cpu_is_da850(void) return ((part_no == 0xb7d1) ? 1 : 0); } +static inline int get_async3_src(void) +{ + return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ? + PLL1_SYSCLK2 : 2; +} + #endif /* CONFIG_SOC_DA8XX */ #endif /* __ASM_ARCH_HARDWARE_H */ |