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authorMathieu J. Poirier <mathieu.poirier@linaro.org>2012-07-31 08:59:27 +0000
committerJohn Rigby <john.rigby@linaro.org>2012-08-16 08:50:32 -0600
commit3b241b1d664cea07cf8f2508e7d712723ef8eb8c (patch)
treeb31889142632fd5b4b7be73cd6f9cc13f07ac5e1 /arch/arm/include
parent371a06a65157ee5c55c19a5d2413f9d60d00a762 (diff)
downloadu-boot-linaro-stable-3b241b1d664cea07cf8f2508e7d712723ef8eb8c.tar.gz
snowball: Moving to ux500.v2 addess scheme for PRCMU access
Addresses between ux500.v1 and ux500.v2 have changed slightly, hence mandating a review of the PRCMU access methods. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/arch-u8500/hardware.h2
-rw-r--r--arch/arm/include/asm/arch-u8500/prcmu.h10
2 files changed, 8 insertions, 4 deletions
diff --git a/arch/arm/include/asm/arch-u8500/hardware.h b/arch/arm/include/asm/arch-u8500/hardware.h
index 6bb95ec07..920888052 100644
--- a/arch/arm/include/asm/arch-u8500/hardware.h
+++ b/arch/arm/include/asm/arch-u8500/hardware.h
@@ -62,7 +62,7 @@
/* Per4 */
#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000)
-#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x0f000)
+#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x06800)
/* Per3 */
#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000)
diff --git a/arch/arm/include/asm/arch-u8500/prcmu.h b/arch/arm/include/asm/arch-u8500/prcmu.h
index 1fd4d2a56..9862eb3dd 100644
--- a/arch/arm/include/asm/arch-u8500/prcmu.h
+++ b/arch/arm/include/asm/arch-u8500/prcmu.h
@@ -28,6 +28,7 @@
#define I2CWRITE 0
#define PRCMU_BASE U8500_PRCMU_BASE
+#define PRCMU_BASE_TCDM U8500_PRCMU_TCDM_BASE
#define PRCM_UARTCLK_MGT_REG (PRCMU_BASE + 0x018)
#define PRCM_MSPCLK_MGT_REG (PRCMU_BASE + 0x01C)
#define PRCM_I2CCLK_MGT_REG (PRCMU_BASE + 0x020)
@@ -38,12 +39,15 @@
#define PRCM_PER5CLK_MGT_REG (PRCMU_BASE + 0x038)
#define PRCM_PER6CLK_MGT_REG (PRCMU_BASE + 0x03C)
#define PRCM_PER7CLK_MGT_REG (PRCMU_BASE + 0x040)
+#define PRCM_MBOX_CPU_VAL (PRCMU_BASE + 0x0FC)
+#define PRCM_MBOX_CPU_SET (PRCMU_BASE + 0x100)
#define PRCM_ARM_IT1_CLEAR (PRCMU_BASE + 0x48C)
+#define PRCM_ARM_IT1_VAL (PRCMU_BASE + 0x494)
#define PRCM_TCR (PRCMU_BASE + 0x1C8)
-#define PRCM_REQ_MB5 (PRCMU_BASE + 0xE44)
-#define PRCM_ACK_MB5 (PRCMU_BASE + 0xDF4)
-#define PRCM_XP70_CUR_PWR_STATE (PRCMU_BASE + 0xFFC)
+#define PRCM_REQ_MB5 (PRCMU_BASE_TCDM + 0xE44)
+#define PRCM_ACK_MB5 (PRCMU_BASE_TCDM + 0xDF4)
+#define PRCM_XP70_CUR_PWR_STATE (PRCMU_BASE_TCDM + 0xFFC)
/* Mailbox 5 Requests */
#define PRCM_REQ_MB5_I2COPTYPE_REG (PRCM_REQ_MB5 + 0x0)
#define PRCM_REQ_MB5_BIT_FIELDS (PRCM_REQ_MB5 + 0x1)