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authorMathieu J. Poirier <mathieu.poirier@linaro.org>2012-07-31 08:59:25 +0000
committerJohn Rigby <john.rigby@linaro.org>2012-08-16 08:50:31 -0600
commit26121839a8042d1f10b768d0b143d6bdd77b23ba (patch)
tree72fdb11116380acef525aa0cbf940e296910a456 /arch/arm/include
parentea02abc40559b4f7aa512f2a9a6c9bc2d5a684b3 (diff)
downloadu-boot-linaro-stable-26121839a8042d1f10b768d0b143d6bdd77b23ba.tar.gz
snowball: Adding architecture dependent initialisation
Enabling timers and clocks in PRCMU and cleaning up mailbox. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/arch-u8500/prcmu.h24
1 files changed, 19 insertions, 5 deletions
diff --git a/arch/arm/include/asm/arch-u8500/prcmu.h b/arch/arm/include/asm/arch-u8500/prcmu.h
index 0836983fa..1fd4d2a56 100644
--- a/arch/arm/include/asm/arch-u8500/prcmu.h
+++ b/arch/arm/include/asm/arch-u8500/prcmu.h
@@ -27,12 +27,23 @@
#define I2C_RD_OK 2
#define I2CWRITE 0
-#define _PRCMU_TCDM_BASE U8500_PRCMU_TCDM_BASE
-#define PRCM_XP70_CUR_PWR_STATE (_PRCMU_TCDM_BASE + 0xFFC) /* 4 BYTES */
-
-#define PRCM_REQ_MB5 (_PRCMU_TCDM_BASE + 0xE44) /* 4 bytes */
-#define PRCM_ACK_MB5 (_PRCMU_TCDM_BASE + 0xDF4) /* 4 bytes */
+#define PRCMU_BASE U8500_PRCMU_BASE
+#define PRCM_UARTCLK_MGT_REG (PRCMU_BASE + 0x018)
+#define PRCM_MSPCLK_MGT_REG (PRCMU_BASE + 0x01C)
+#define PRCM_I2CCLK_MGT_REG (PRCMU_BASE + 0x020)
+#define PRCM_SDMMCCLK_MGT_REG (PRCMU_BASE + 0x024)
+#define PRCM_PER1CLK_MGT_REG (PRCMU_BASE + 0x02C)
+#define PRCM_PER2CLK_MGT_REG (PRCMU_BASE + 0x030)
+#define PRCM_PER3CLK_MGT_REG (PRCMU_BASE + 0x034)
+#define PRCM_PER5CLK_MGT_REG (PRCMU_BASE + 0x038)
+#define PRCM_PER6CLK_MGT_REG (PRCMU_BASE + 0x03C)
+#define PRCM_PER7CLK_MGT_REG (PRCMU_BASE + 0x040)
+#define PRCM_ARM_IT1_CLEAR (PRCMU_BASE + 0x48C)
+#define PRCM_TCR (PRCMU_BASE + 0x1C8)
+#define PRCM_REQ_MB5 (PRCMU_BASE + 0xE44)
+#define PRCM_ACK_MB5 (PRCMU_BASE + 0xDF4)
+#define PRCM_XP70_CUR_PWR_STATE (PRCMU_BASE + 0xFFC)
/* Mailbox 5 Requests */
#define PRCM_REQ_MB5_I2COPTYPE_REG (PRCM_REQ_MB5 + 0x0)
#define PRCM_REQ_MB5_BIT_FIELDS (PRCM_REQ_MB5 + 0x1)
@@ -52,4 +63,7 @@
extern int prcmu_i2c_read(u8 reg, u16 slave);
extern int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data);
+void u8500_prcmu_enable(u32 *reg);
+void db8500_prcmu_init(void);
+
#endif /* __MACH_PRCMU_FW_V1_H */