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authorJeong-Hyeon Kim <jhkim@insignal.co.kr>2012-08-29 12:28:26 +0900
committerJohn Rigby <john.rigby@linaro.org>2012-12-06 13:51:42 -0700
commit4a703be87762dfd8753ad77af235f2db252592e3 (patch)
treef5eae01e95873ac50c9c41b03738b137a0dec5e8 /arch/arm/include/asm
parentcd191553c40ab35703847ea2bb1f4c360fc3a49e (diff)
downloadu-boot-linaro-stable-4a703be87762dfd8753ad77af235f2db252592e3.tar.gz
EXYNOS: additional Exynos4 SoC series support
- Fixed MPLL register address It's different between Exynos4210 and Exynos4412. - Added pinmux functions for Exynos4 - Added extended gpios for Exynos4412 Exynos4412 has more gpios than Exynos4210. Signed-off-by: Jeong-Hyeon Kim <jhkim@insignal.co.kr>
Diffstat (limited to 'arch/arm/include/asm')
-rw-r--r--arch/arm/include/asm/arch-exynos/clock.h240
-rw-r--r--arch/arm/include/asm/arch-exynos/cpu.h14
-rw-r--r--arch/arm/include/asm/arch-exynos/gpio.h21
3 files changed, 270 insertions, 5 deletions
diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h
index fce38efbb..77760f25b 100644
--- a/arch/arm/include/asm/arch-exynos/clock.h
+++ b/arch/arm/include/asm/arch-exynos/clock.h
@@ -251,6 +251,246 @@ struct exynos4_clock {
unsigned int div_iem_l1;
};
+struct exynos4412_clock {
+ unsigned char res1[0x4200];
+ unsigned int src_leftbus;
+ unsigned char res2[0x1fc];
+ unsigned int mux_stat_leftbus;
+ unsigned char res3[0xfc];
+ unsigned int div_leftbus;
+ unsigned char res4[0xfc];
+ unsigned int div_stat_leftbus;
+ unsigned char res5[0x1fc];
+ unsigned int gate_ip_leftbus;
+ unsigned char res6[0x12c];
+ unsigned int gate_ip_image;
+ unsigned char res7[0xcc];
+ unsigned int clkout_cmu_leftbus;
+ unsigned int clkout_cmu_leftbus_div_stat;
+ unsigned char res8[0x37f8];
+ unsigned int src_rightbus;
+ unsigned char res9[0x1fc];
+ unsigned int mux_stat_rightbus;
+ unsigned char res10[0xfc];
+ unsigned int div_rightbus;
+ unsigned char res11[0xfc];
+ unsigned int div_stat_rightbus;
+ unsigned char res12[0x1fc];
+ unsigned int gate_ip_rightbus;
+ unsigned char res13[0x15c];
+ unsigned int gate_ip_perir;
+ unsigned char res14[0x9c];
+ unsigned int clkout_cmu_rightbus;
+ unsigned int clkout_cmu_rightbus_div_stat;
+ unsigned char res15[0x3608];
+ unsigned int epll_lock;
+ unsigned char res16[0xc];
+ unsigned int vpll_lock;
+ unsigned char res17[0xec];
+ unsigned int epll_con0;
+ unsigned int epll_con1;
+ unsigned int epll_con2;
+ unsigned char res18[0x4];
+ unsigned int vpll_con0;
+ unsigned int vpll_con1;
+ unsigned int vpll_con2;
+ unsigned char res19[0xe4];
+ unsigned int src_top0;
+ unsigned int src_top1;
+ unsigned char res20[0x8];
+ unsigned int src_cam0;
+ unsigned int src_tv;
+ unsigned int src_mfc;
+ unsigned int src_g3d;
+ unsigned char res21[0x4];
+ unsigned int src_lcd0;
+ unsigned int src_isp;
+ unsigned int src_maudio;
+ unsigned int src_fsys;
+ unsigned char res22[0xc];
+ unsigned int src_peril0;
+ unsigned int src_peril1;
+ unsigned int src_cam1;
+ unsigned char res23[0xc4];
+ unsigned int src_mask_cam0;
+ unsigned int src_mask_tv;
+ unsigned char res24[0xc];
+ unsigned int src_mask_lcd;
+ unsigned int src_mask_isp;
+ unsigned int src_mask_maudio;
+ unsigned int src_mask_fsys;
+ unsigned char res25[0xc];
+ unsigned int src_mask_peril0;
+ unsigned int src_mask_peril1;
+ unsigned char res26[0xb8];
+ unsigned int mux_stat_top;
+ unsigned int mux_stat_top1;
+ unsigned char res27[0x10];
+ unsigned int mux_stat_mfc;
+ unsigned int mux_stat_g3d;
+ unsigned char res28[0x28];
+ unsigned int mux_stat_cam1;
+ unsigned char res29[0xb4];
+ unsigned int div_top;
+ unsigned char res30[0xc];
+ unsigned int div_cam0;
+ unsigned int div_tv;
+ unsigned int div_mfc;
+ unsigned int div_g3d;
+ unsigned char res31[0x4];
+ unsigned int div_lcd;
+ unsigned int div_isp;
+ unsigned int div_maudio;
+ unsigned int div_fsys0;
+ unsigned int div_fsys1;
+ unsigned int div_fsys2;
+ unsigned int div_fsys3;
+ unsigned int div_peril0;
+ unsigned int div_peril1;
+ unsigned int div_peril2;
+ unsigned int div_peril3;
+ unsigned int div_peril4;
+ unsigned int div_peril5;
+ unsigned int div_cam1;
+ unsigned char res32[0x14];
+ unsigned int div2_ratio;
+ unsigned char res33[0x8c];
+ unsigned int div_stat_top;
+ unsigned char res34[0xc];
+ unsigned int div_stat_cam0;
+ unsigned int div_stat_tv;
+ unsigned int div_stat_mfc;
+ unsigned int div_stat_g3d;
+ unsigned char res35[0x4];
+ unsigned int div_stat_lcd;
+ unsigned int div_stat_isp;
+ unsigned int div_stat_maudio;
+ unsigned int div_stat_fsys0;
+ unsigned int div_stat_fsys1;
+ unsigned int div_stat_fsys2;
+ unsigned int div_stat_fsys3;
+ unsigned int div_stat_peril0;
+ unsigned int div_stat_peril1;
+ unsigned int div_stat_peril2;
+ unsigned int div_stat_peril3;
+ unsigned int div_stat_peril4;
+ unsigned int div_stat_peril5;
+ unsigned int div_stat_cam1;
+ unsigned char res36[0x14];
+ unsigned int div2_stat;
+ unsigned char res37[0xc0];
+ unsigned int gate_bus_fsys1;
+ unsigned char res38[0x1d8];
+ unsigned int gate_ip_cam;
+ unsigned int gate_ip_tv;
+ unsigned int gate_ip_mfc;
+ unsigned int gate_ip_g3d;
+ unsigned char res39[0x4];
+ unsigned int gate_ip_lcd;
+ unsigned int gate_ip_isp;
+ unsigned char res40[0x4];
+ unsigned int gate_ip_fsys;
+ unsigned char res41[0x8];
+ unsigned int gate_ip_gps;
+ unsigned int gate_ip_peril;
+ unsigned char res42[0x1c];
+ unsigned int gate_block;
+ unsigned char res43[0x8c];
+ unsigned int clkout_cmu_top;
+ unsigned int clkout_cmu_top_div_stat;
+ unsigned char res44[0x3600];
+ unsigned int mpll_lock;
+ unsigned char res45[0xfc];
+ unsigned int mpll_con0;
+ unsigned int mpll_con1;
+ unsigned char res46[0xf0];
+ unsigned int src_dmc;
+ unsigned char res47[0xfc];
+ unsigned int src_mask_dmc;
+ unsigned char res48[0xfc];
+ unsigned int mux_stat_dmc;
+ unsigned char res49[0xfc];
+ unsigned int div_dmc0;
+ unsigned int div_dmc1;
+ unsigned char res50[0xf8];
+ unsigned int div_stat_dmc0;
+ unsigned int div_stat_dmc1;
+ unsigned char res51[0x2f8];
+ unsigned int gate_ip_dmc;
+ unsigned int gate_ip_dmc1;
+ unsigned char res52[0xf8];
+ unsigned int clkout_cmu_dmc;
+ unsigned int clkout_cmu_dmc_div_stat;
+ unsigned char res53[0x5f8];
+ unsigned int dcgidx_map0;
+ unsigned int dcgidx_map1;
+ unsigned int dcgidx_map2;
+ unsigned char res54[0x14];
+ unsigned int dcgperf_map0;
+ unsigned int dcgperf_map1;
+ unsigned char res55[0x18];
+ unsigned int dvcidx_map;
+ unsigned char res56[0x1c];
+ unsigned int freq_cpu;
+ unsigned int freq_dpm;
+ unsigned char res57[0x18];
+ unsigned int dvsemclk_en;
+ unsigned int maxperf;
+ unsigned char res58[0xc];
+ unsigned int dmc_puause_ctrl;
+ unsigned int ddrphy_lock_ctrl;
+ unsigned int c2c_state;
+ unsigned char res59[0x2f60];
+ unsigned int apll_lock;
+ unsigned char res60[0xfc];
+ unsigned int apll_con0;
+ unsigned int apll_con1;
+ unsigned char res61[0xf8];
+ unsigned int src_cpu;
+ unsigned char res62[0x1fc];
+ unsigned int mux_stat_cpu;
+ unsigned char res63[0xfc];
+ unsigned int div_cpu0;
+ unsigned int div_cpu1;
+ unsigned char res64[0xf8];
+ unsigned int div_stat_cpu0;
+ unsigned int div_stat_cpu1;
+ unsigned char res65[0x2f8];
+ unsigned int gate_ip_cpu;
+ unsigned char res66[0xfc];
+ unsigned int clkout_cmu_cpu;
+ unsigned int clkout_cmu_cpu_div_stat;
+ unsigned char res67[0x5f8];
+ unsigned int armclk_stopctrl;
+ unsigned int atclk_stopctrl;
+ unsigned char res68[0x18];
+ unsigned int pwr_ctrl;
+ unsigned int pwr_ctrl2;
+ unsigned char res69[0x3d8];
+ unsigned int l2_status;
+ unsigned char res70[0xc];
+ unsigned int cpu_status;
+ unsigned char res71[0xc];
+ unsigned int ptm_status;
+ unsigned char res72[0x2edc];
+ unsigned int clk_div_isp0;
+ unsigned int clk_div_isp1;
+ unsigned char res73[0xf8];
+ unsigned int clk_div_stat_isp0;
+ unsigned int clk_div_stat_isp1;
+ unsigned char res74[0x3f8];
+ unsigned int gate_ip_isp0;
+ unsigned int gate_ip_isp1;
+ unsigned char res75[0x1f8];
+ unsigned int clkout_cmu_isp;
+ unsigned int clkout_cmu_isp_stat;
+ unsigned char res76[0xf8];
+ unsigned int clkout_cmu_spare0;
+ unsigned int clkout_cmu_spare1;
+ unsigned int clkout_cmu_spare2;
+ unsigned int clkout_cmu_spare3;
+};
+
struct exynos5_clock {
unsigned int apll_lock;
unsigned char res1[0xfc];
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index 2cd4ae152..58c7de60b 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -58,6 +58,10 @@
#define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4412_DMC0_BASE 0x10600000
+#define EXYNOS4412_DMC1_BASE 0x10610000
+#define EXYNOS4412_GPIO_PART4_BASE 0x106E0000
+
/* EXYNOS5 */
#define EXYNOS5_I2C_SPACING 0x10000
@@ -130,14 +134,16 @@ static inline char *s5p_get_cpu_name(void)
return EXYNOS_CPU_NAME;
}
-#define IS_SAMSUNG_TYPE(type, id) \
+#define IS_SAMSUNG_TYPE(type, id, shift) \
static inline int cpu_is_##type(void) \
{ \
- return (s5p_cpu_id >> 12) == id; \
+ return (s5p_cpu_id >> shift) == id; \
}
-IS_SAMSUNG_TYPE(exynos4, 0x4)
-IS_SAMSUNG_TYPE(exynos5, 0x5)
+IS_SAMSUNG_TYPE(exynos4, 0x4, 12)
+IS_SAMSUNG_TYPE(exynos4210, 0x4210, 0)
+IS_SAMSUNG_TYPE(exynos4412, 0x4412, 0)
+IS_SAMSUNG_TYPE(exynos5, 0x5, 12)
#define SAMSUNG_BASE(device, base) \
static inline unsigned int samsung_get_base_##device(void) \
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h
index 4db8fd640..09286451f 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -49,6 +49,9 @@ struct exynos4_gpio_part1 {
struct s5p_gpio_bank f1;
struct s5p_gpio_bank f2;
struct s5p_gpio_bank f3;
+ struct s5p_gpio_bank res1[2];
+ struct s5p_gpio_bank j0;
+ struct s5p_gpio_bank j1;
};
struct exynos4_gpio_part2 {
@@ -68,7 +71,13 @@ struct exynos4_gpio_part2 {
struct s5p_gpio_bank y4;
struct s5p_gpio_bank y5;
struct s5p_gpio_bank y6;
- struct s5p_gpio_bank res1[80];
+ struct s5p_gpio_bank res1[3];
+ struct s5p_gpio_bank m0;
+ struct s5p_gpio_bank m1;
+ struct s5p_gpio_bank m2;
+ struct s5p_gpio_bank m3;
+ struct s5p_gpio_bank m4;
+ struct s5p_gpio_bank res2[72];
struct s5p_gpio_bank x0;
struct s5p_gpio_bank x1;
struct s5p_gpio_bank x2;
@@ -79,6 +88,16 @@ struct exynos4_gpio_part3 {
struct s5p_gpio_bank z;
};
+struct exynos4_gpio_part4 {
+ struct s5p_gpio_bank v0;
+ struct s5p_gpio_bank v1;
+ struct s5p_gpio_bank res1[1];
+ struct s5p_gpio_bank v2;
+ struct s5p_gpio_bank v3;
+ struct s5p_gpio_bank res2[1];
+ struct s5p_gpio_bank v4;
+};
+
struct exynos5_gpio_part1 {
struct s5p_gpio_bank a0;
struct s5p_gpio_bank a1;