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authorJason Liu <jason.hui@linaro.org>2011-04-12 16:13:27 +0800
committerJohn Rigby <john.rigby@linaro.org>2011-06-28 16:05:59 +0100
commit446af2d3bf2c7c9af5a4a1731b93ad5a044ab9ca (patch)
tree14927d3eb6f09e63586940b38b63c9cd80c9eecf /arch/arm/include/asm/arch-mx5/imx-regs.h
parent94f13400c6c93a09b79cd3f38cdea766e8a0c01f (diff)
mx5: Add clock config interface
Add clock config interface support, so that we can configure CPU or DDR clock in the later init Signed-off-by: Jason Liu <jason.hui@linaro.org> Signed-off-by: Eric Miao <eric.miao@linaro.org>
Diffstat (limited to 'arch/arm/include/asm/arch-mx5/imx-regs.h')
-rw-r--r--arch/arm/include/asm/arch-mx5/imx-regs.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index a1849f8c0..896a22913 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -98,6 +98,7 @@
#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000)
+#define PLL4_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008c000)
#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)