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authorWolfgang Denk <wd@denx.de>2010-10-28 20:35:36 +0200
committerWolfgang Denk <wd@denx.de>2010-10-29 21:39:59 +0200
commita9aa3926295df759306258e5e24cace414f53b67 (patch)
treeb63739471ef3aaebad27fd610f8394fee35120b5 /arch/arm/cpu/armv7
parent2e5167ccad93ca9cfa6a2acfab5e4785418e477e (diff)
downloadu-boot-linaro-stable-a9aa3926295df759306258e5e24cace414f53b67.tar.gz
Drop support for CONFIG_SYS_ARM_WITHOUT_RELOC
When this define was introduced, the idea was to provide a soft migration path for ARM boards to get adapted to the new relocation support. However, other recent changes led to a different implementation (ELF relocation), where this no longer works. By now CONFIG_SYS_ARM_WITHOUT_RELOC does not only not help any more, but it actually hurts because it obfuscates the actual code by sprinkling it with lots of dead and non-working debris. So let's make a clean cut and drop CONFIG_SYS_ARM_WITHOUT_RELOC. Signed-off-by: Wolfgang Denk <wd@denx.de> Tested-by: Heiko Schocher <hs@denx.de> Tested-by: Reinhard Meyer <u-boot@emk-elektronik.de>
Diffstat (limited to 'arch/arm/cpu/armv7')
-rw-r--r--arch/arm/cpu/armv7/omap3/emif4.c24
-rw-r--r--arch/arm/cpu/armv7/omap3/sdrc.c28
-rw-r--r--arch/arm/cpu/armv7/omap4/board.c5
-rw-r--r--arch/arm/cpu/armv7/start.S113
4 files changed, 0 insertions, 170 deletions
diff --git a/arch/arm/cpu/armv7/omap3/emif4.c b/arch/arm/cpu/armv7/omap3/emif4.c
index da2cd9001..0870857ed 100644
--- a/arch/arm/cpu/armv7/omap3/emif4.c
+++ b/arch/arm/cpu/armv7/omap3/emif4.c
@@ -136,29 +136,6 @@ void do_emif4_init(void)
* dram_init -
* - Sets uboots idea of sdram size
*/
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-int dram_init(void)
-{
- DECLARE_GLOBAL_DATA_PTR;
- unsigned int size0 = 0, size1 = 0;
-
- size0 = get_sdr_cs_size(CS0);
- /*
- * If a second bank of DDR is attached to CS1 this is
- * where it can be started. Early init code will init
- * memory on CS0.
- */
- if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED))
- size1 = get_sdr_cs_size(CS1);
-
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = size0;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
- gd->bd->bi_dram[1].size = size1;
-
- return 0;
-}
-#else
int dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
@@ -190,7 +167,6 @@ void dram_init_banksize (void)
gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
gd->bd->bi_dram[1].size = size1;
}
-#endif
/*
* mem_init() -
diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c
index 6c419f5b9..c75aa1d11 100644
--- a/arch/arm/cpu/armv7/omap3/sdrc.c
+++ b/arch/arm/cpu/armv7/omap3/sdrc.c
@@ -163,33 +163,6 @@ void do_sdrc_init(u32 cs, u32 early)
* dram_init -
* - Sets uboots idea of sdram size
*/
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-int dram_init(void)
-{
- DECLARE_GLOBAL_DATA_PTR;
- unsigned int size0 = 0, size1 = 0;
-
- size0 = get_sdr_cs_size(CS0);
- /*
- * If a second bank of DDR is attached to CS1 this is
- * where it can be started. Early init code will init
- * memory on CS0.
- */
- if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
- do_sdrc_init(CS1, NOT_EARLY);
- make_cs1_contiguous();
-
- size1 = get_sdr_cs_size(CS1);
- }
-
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = size0;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
- gd->bd->bi_dram[1].size = size1;
-
- return 0;
-}
-#else
int dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
@@ -225,7 +198,6 @@ void dram_init_banksize (void)
gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
gd->bd->bi_dram[1].size = size1;
}
-#endif
/*
* mem_init -
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 24a66f5b9..e7651d2dd 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -102,12 +102,7 @@ int dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
- gd->bd->bi_dram[0].start = 0x80000000;
- gd->bd->bi_dram[0].size = sdram_size();
-#else
gd->ram_size = sdram_size();
-#endif
return 0;
}
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index bdf2fad38..4a0710c96 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -70,12 +70,6 @@ _end_vect:
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-.globl _armboot_start
-_armboot_start:
- .word _start
-#endif
-
/*
* These are defined in the board-specific linker script.
*/
@@ -99,7 +93,6 @@ FIQ_STACK_START:
.word 0x0badc0de
#endif
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
@@ -295,94 +288,6 @@ _rel_dyn_end_ofs:
_dynsym_start_ofs:
.word __dynsym_start - _start
-#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-/*
- * the actual reset code
- */
-
-reset:
- /*
- * set the cpu to SVC32 mode
- */
- mrs r0, cpsr
- bic r0, r0, #0x1f
- orr r0, r0, #0xd3
- msr cpsr,r0
-
-#if (CONFIG_OMAP34XX)
- /* Copy vectors to mask ROM indirect addr */
- adr r0, _start @ r0 <- current position of code
- add r0, r0, #4 @ skip reset vector
- mov r2, #64 @ r2 <- size to copy
- add r2, r0, r2 @ r2 <- source end address
- mov r1, #SRAM_OFFSET0 @ build vect addr
- mov r3, #SRAM_OFFSET1
- add r1, r1, r3
- mov r3, #SRAM_OFFSET2
- add r1, r1, r3
-next:
- ldmia r0!, {r3 - r10} @ copy from source address [r0]
- stmia r1!, {r3 - r10} @ copy to target address [r1]
- cmp r0, r2 @ until source end address [r2]
- bne next @ loop until equal */
-#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
- /* No need to copy/exec the clock code - DPLL adjust already done
- * in NAND/oneNAND Boot.
- */
- bl cpy_clk_code @ put dpll adjust code behind vectors
-#endif /* NAND Boot */
-#endif
- /* the mask ROM code should have PLL and others stable */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- bl cpu_init_crit
-#endif
-
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
-relocate: @ relocate U-Boot to RAM
- adr r0, _start @ r0 <- current position of code
- ldr r1, _TEXT_BASE @ test if we run from flash or RAM
- cmp r0, r1 @ don't reloc during debug
- beq stack_setup
-
- ldr r2, _armboot_start
- ldr r3, _bss_start
- sub r2, r3, r2 @ r2 <- size of armboot
- add r2, r0, r2 @ r2 <- source end address
-
-copy_loop: @ copy 32 bytes at a time
- ldmia r0!, {r3 - r10} @ copy from source address [r0]
- stmia r1!, {r3 - r10} @ copy to target address [r1]
- cmp r0, r2 @ until source end address [r2]
- blo copy_loop
-#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
-
- /* Set up the stack */
-stack_setup:
- ldr r0, _TEXT_BASE @ upper 128 KiB: relocated uboot
- sub r0, r0, #CONFIG_SYS_MALLOC_LEN @ malloc area
- sub r0, r0, #GENERATED_GBL_DATA_SIZE @ bdinfo
-#ifdef CONFIG_USE_IRQ
- sub r0, r0, #(CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ)
-#endif
- sub sp, r0, #12 @ leave 3 words for abort-stack
- bic sp, sp, #7 @ 8-byte alignment for ABI compliance
-
- /* Clear BSS (if any). Is below tx (watch load addr - need space) */
-clear_bss:
- ldr r0, _bss_start @ find start of bss segment
- ldr r1, _bss_end @ stop here
- mov r2, #0x00000000 @ clear value
-clbss_l:
- str r2, [r0] @ clear BSS location
- cmp r0, r1 @ are we at the end yet
- add r0, r0, #4 @ increment clear index pointer
- bne clbss_l @ keep clearing till at end
-
- ldr pc, _start_armboot @ jump to C code
-
-_start_armboot: .word start_armboot
-#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-
/*************************************************************************
*
* CPU_init_critical registers
@@ -464,14 +369,8 @@ cpu_init_crit:
@ user stack
stmia sp, {r0 - r12} @ Save user registers (now in
@ svc mode) r0-r12
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
- ldr r2, _armboot_start
- sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
- sub r2, r2, #(GENERATED_GBL_DATA_SIZE + 8) @ set base 2 words into abort
-#else
ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort
@ stack
-#endif
ldmia r2, {r2 - r3} @ get values for "aborted" pc
@ and cpsr (into parm regs)
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
@@ -507,14 +406,8 @@ cpu_init_crit:
.endm
.macro get_bad_stack
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
- ldr r13, _armboot_start @ setup our mode stack (enter
- sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
- sub r13, r13, #(GENERATED_GBL_DATA_SIZE + 8) @ move to reserved a couple
-#else
ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter
@ in banked mode)
-#endif
str lr, [r13] @ save caller lr in position 0
@ of saved stack
@@ -535,14 +428,8 @@ cpu_init_crit:
sub r13, r13, #4 @ space on current stack for
@ scratch reg.
str r0, [r13] @ save R0's value.
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
- ldr r0, _armboot_start @ get data regions start
- sub r0, r0, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
- sub r0, r0, #(GENERATED_GBL_DATA_SIZE + 8) @ move past gbl and a couple
-#else
ldr r0, IRQ_STACK_START_IN @ get data regions start
@ spots for abort stack
-#endif
str lr, [r0] @ save caller lr in position 0
@ of saved stack
mrs r0, spsr @ get the spsr