diff options
| author | SRICHARAN R <r.sricharan@ti.com> | 2012-03-12 02:25:38 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-05-15 08:31:23 +0200 |
| commit | 8de17f4617816919c4b73a3a1a377d5507596293 (patch) | |
| tree | 12028f37ec71e9211ac08471395211d037f2e669 /arch/arm/cpu/armv7/omap4 | |
| parent | f40107345cbcd6e0d1747eda45e76c4e2a6df0db (diff) | |
OMAP5: palmas: Configure nominal opp vdd values
The nominal opp vdd values as recommended for
ES1.0 silicon is set for mpu, core, mm domains using palmas.
Also used the right sequence to enable the vcores as per
a previous patch from Nishant Menon, which can be dropped now.
http://lists.denx.de/pipermail/u-boot/2012-March/119151.html
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/omap4')
| -rw-r--r-- | arch/arm/cpu/armv7/omap4/clocks.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c index b6b3f7e19..dd694c409 100644 --- a/arch/arm/cpu/armv7/omap4/clocks.c +++ b/arch/arm/cpu/armv7/omap4/clocks.c @@ -326,6 +326,21 @@ void scale_vcores(void) } } +u32 get_offset_code(u32 offset) +{ + u32 offset_code, step = 12660; /* 12.66 mV represented in uV */ + + if (omap_revision() == OMAP4430_ES1_0) + offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV; + else + offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV; + + offset_code = (offset + step - 1) / step; + + /* The code starts at 1 not 0 */ + return ++offset_code; +} + /* * Enable essential clock domains, modules and * do some additional special settings needed |