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authorTom Rini <trini@ti.com>2011-11-18 12:48:06 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2011-12-06 23:59:38 +0100
commit9ae0d550741db45e933dc73e7135d1861e3a9b62 (patch)
treeb640b1a6600c6b7716ac922037e8f908e2126937 /arch/arm/cpu/armv7/omap3/sdrc.c
parentfc41ba1e2b4271bef197bfbf89d49458368319ce (diff)
OMAP3 SPL: Rework memory initalization and devkit8000 support
This changes to making the board be responsible for providing the memory initialization timings in SPL and converts the devkit8000 to this framework. In SPL we try and initialize both CS0 and CS1. Cc: Frederik Kriewitz <frederik@kriewitz.eu> Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/omap3/sdrc.c')
-rw-r--r--arch/arm/cpu/armv7/omap3/sdrc.c28
1 files changed, 15 insertions, 13 deletions
diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c
index 2756024ca..a27b4b124 100644
--- a/arch/arm/cpu/armv7/omap3/sdrc.c
+++ b/arch/arm/cpu/armv7/omap3/sdrc.c
@@ -148,6 +148,18 @@ void do_sdrc_init(u32 cs, u32 early)
sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
+ /*
+ * When called in the early context this may be SPL and we will
+ * need to set all of the timings. This ends up being board
+ * specific so we call a helper function to take care of this
+ * for us. Otherwise, to be safe, we need to copy the settings
+ * from the first bank to the second. We will setup CS0,
+ * then set cs_cfg to the appropriate value then try and
+ * setup CS1.
+ */
+#ifdef CONFIG_SPL_BUILD
+ get_board_mem_timings(&mcfg, &ctrla, &ctrlb, &rfr_ctrl, &mr);
+#endif
if (early) {
/* reset sdrc controller */
writel(SOFTRESET, &sdrc_base->sysconfig);
@@ -164,22 +176,12 @@ void do_sdrc_init(u32 cs, u32 early)
writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
sdelay(0x20000);
-/* As long as V_MCFG and V_RFR_CTRL is not defined for all OMAP3 boards we need
- * to prevent this to be build in non-SPL build */
#ifdef CONFIG_SPL_BUILD
- /*
- * If we use a SPL there is no x-loader nor config header so
- * we have to do the job ourselfs
- */
-
- mcfg = V_MCFG;
- ctrla = V_ACTIMA_165;
- ctrlb = V_ACTIMB_165;
- rfr_ctrl = V_RFR_CTRL;
- mr = V_MR;
-
write_sdrc_timings(CS0, sdrc_actim_base0, mcfg, ctrla, ctrlb,
rfr_ctrl, mr);
+ make_cs1_contiguous();
+ write_sdrc_timings(CS0, sdrc_actim_base1, mcfg, ctrla, ctrlb,
+ rfr_ctrl, mr);
#endif
}