diff options
| author | Fabio Estevam <festevam@gmail.com> | 2011-04-11 16:18:12 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-04-27 19:38:05 +0200 |
| commit | 4adaf9bf097b57af12f9a598759f8c9990e3502e (patch) | |
| tree | 9eda09c8de62724cbefee35ba40922459528b369 /arch/arm/cpu/arm1136 | |
| parent | 862711154339be2af723adcbde217743de781e81 (diff) | |
ARM: mx31: Print the silicon version
Use the same method of the Linux kernel to print the MX31 silicon version on
boot.
Tested on a MX31PDK with a 2.0 silicon, where it shows:
CPU: Freescale i.MX31 rev 2.0 at 531 MHz
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'arch/arm/cpu/arm1136')
| -rw-r--r-- | arch/arm/cpu/arm1136/mx31/generic.c | 30 |
1 files changed, 28 insertions, 2 deletions
diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c index fa07fec60..9b7a7a24c 100644 --- a/arch/arm/cpu/arm1136/mx31/generic.c +++ b/arch/arm/cpu/arm1136/mx31/generic.c @@ -106,11 +106,37 @@ void mx31_set_pad(enum iomux_pins pin, u32 config) } +struct mx3_cpu_type mx31_cpu_type[] = { + { .srev = 0x00, .v = "1.0" }, + { .srev = 0x10, .v = "1.1" }, + { .srev = 0x11, .v = "1.1" }, + { .srev = 0x12, .v = "1.15" }, + { .srev = 0x13, .v = "1.15" }, + { .srev = 0x14, .v = "1.2" }, + { .srev = 0x15, .v = "1.2" }, + { .srev = 0x28, .v = "2.0" }, + { .srev = 0x29, .v = "2.0" }, +}; + +char *get_cpu_rev(void) +{ + u32 i, srev; + + /* read SREV register from IIM module */ + struct iim_regs *iim = (struct iim_regs *)MX31_IIM_BASE_ADDR; + srev = readl(&iim->iim_srev); + + for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++) + if (srev == mx31_cpu_type[i].srev) + return mx31_cpu_type[i].v; + return "unknown"; +} + #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo (void) { - printf("CPU: Freescale i.MX31 at %d MHz\n", - mx31_get_mcu_main_clk() / 1000000); + printf("CPU: Freescale i.MX31 rev %s at %d MHz\n", + get_cpu_rev(), mx31_get_mcu_main_clk() / 1000000); return 0; } #endif |