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authorGeorge G. Davis <gdavis@mvista.com>2010-05-11 10:15:36 -0400
committerTom <Tom@bumblecow.com>2010-06-01 06:44:09 -0500
commit409a07c9d72b0d833c1cce264bdb4bb2628fe28e (patch)
tree77e1391844b37c13d8a4f114f421e1eee91b8d3d /arch/arm/cpu/arm1136/start.S
parent39c209546ab5b11ca6410c5cc57dcbf457e50800 (diff)
downloadu-boot-linaro-stable-409a07c9d72b0d833c1cce264bdb4bb2628fe28e.tar.gz
ARM1136: Fix cache_flush() error and correct cpu_init_crit() comments
The ARM1136 cache_flush() function uses the "mcr p15, 0, rn, c7, c7, 0" instruction which means "Invalidate Both Caches" when in fact the intent is to clean and invalidate all caches. So add an "mcr p15, 0, %0, c7, c10, 0" instruction to "Clean Entire Data Cache" prior to the "Invalidate Both Caches" instruction to insure that memory is consistent with any dirty cache lines. Also fix a couple of "flush v*" comments in ARM1136 cpu_init_crit() so that they correctly describe the actual ARM1136 CP15 C7 Cache Operations used. Signed-off-by: George G. Davis <gdavis@mvista.com>
Diffstat (limited to 'arch/arm/cpu/arm1136/start.S')
-rw-r--r--arch/arm/cpu/arm1136/start.S4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S
index 957f4389b..922d01cb7 100644
--- a/arch/arm/cpu/arm1136/start.S
+++ b/arch/arm/cpu/arm1136/start.S
@@ -226,8 +226,8 @@ cpu_init_crit:
* flush v4 I/D caches
*/
mov r0, #0
- mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
- mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
+ mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
+ mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
/*
* disable MMU stuff and caches