diff options
| author | Graeme Russ <graeme.russ@gmail.com> | 2011-11-08 02:33:17 +0000 |
|---|---|---|
| committer | Graeme Russ <graeme.russ@gmail.com> | 2011-11-29 21:04:06 +1100 |
| commit | facc9e7bf42e3578d7e7cecf1727f31badeee6bd (patch) | |
| tree | a90fa30610a3e35463648384949af2edac5cd8fb | |
| parent | 63a90bfb7e2794489acc708835958e1e4a6ea1d6 (diff) | |
x86: Punt cold- and warm-boot flags
Nobody uses them anyway
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
| -rw-r--r-- | arch/x86/cpu/start.S | 2 | ||||
| -rw-r--r-- | arch/x86/cpu/start16.S | 3 | ||||
| -rw-r--r-- | arch/x86/include/asm/global_data.h | 2 |
3 files changed, 0 insertions, 7 deletions
diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 306fb4961..1634eb11c 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -53,8 +53,6 @@ _x86boot_start: movl %eax, %cr0 wbinvd - /* Tell 32-bit code it is being entered from an in-RAM copy */ - movw $GD_FLG_WARM_BOOT, %bx _start: /* This is the 32-bit cold-reset entry point */ diff --git a/arch/x86/cpu/start16.S b/arch/x86/cpu/start16.S index 9dabff2b9..33e53cdb3 100644 --- a/arch/x86/cpu/start16.S +++ b/arch/x86/cpu/start16.S @@ -37,9 +37,6 @@ .code16 .globl start16 start16: - /* Set the Cold Boot / Hard Reset flag */ - movl $GD_FLG_COLD_BOOT, %ebx - /* * First we let the BSP do some early initialization * this code have to map the flash to its final position diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index f177a4fa3..c7365496a 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -91,8 +91,6 @@ extern gd_t *gd; #define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ #define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ #define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */ -#define GD_FLG_COLD_BOOT 0x00100 /* Cold Boot */ -#define GD_FLG_WARM_BOOT 0x00200 /* Warm Boot */ #if 0 #define DECLARE_GLOBAL_DATA_PTR |