aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorKim Phillips <kim.phillips@freescale.com>2010-07-14 19:47:29 -0500
committerKumar Gala <galak@kernel.crashing.org>2010-08-01 11:18:45 -0500
commita37c36f4e70bada297f281b0e542539ad43e50f6 (patch)
tree437c988485c0302ebaccd5509e928e88dc03fc7a
parent5be58f5fc818b429ae5c1c461d540a5d380d9853 (diff)
downloadu-boot-linaro-stable-a37c36f4e70bada297f281b0e542539ad43e50f6.tar.gz
powerpc/8xxx: query feature reporting register for num cores on unknown cpus
doing so helps avant garde users, such as those using simulators that allow users to configure the number of cores, so as to not have to manually adjust u-boot sources. h/w should also be reliably setting FRR NCPU in the future. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
-rw-r--r--arch/powerpc/cpu/mpc8xxx/cpu.c10
-rw-r--r--arch/powerpc/include/asm/immap_85xx.h2
2 files changed, 10 insertions, 2 deletions
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index dc3da1689..97a94f4cd 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -110,8 +110,14 @@ struct cpu_type *identify_cpu(u32 ver)
}
int cpu_numcores() {
- struct cpu_type *cpu;
- cpu = gd->cpu;
+ ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC85xx_PIC_ADDR;
+ struct cpu_type *cpu = gd->cpu;
+
+ /* better to query feature reporting register than just assume 1 */
+ if (cpu == &cpu_type_unknown)
+ return ((in_be32(&pic->frr) & MPC85xx_PICFRR_NCPU_MASK) >>
+ MPC85xx_PICFRR_NCPU_SHIFT) + 1;
+
return cpu->num_cores;
}
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index f109e8c5c..c1382c8c5 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -760,6 +760,8 @@ typedef struct ccsr_pic {
u32 eoi; /* End Of IRQ */
u8 res9[3916];
u32 frr; /* Feature Reporting */
+#define MPC85xx_PICFRR_NCPU_MASK 0x00001f00
+#define MPC85xx_PICFRR_NCPU_SHIFT 8
u8 res10[28];
u32 gcr; /* Global Configuration */
#define MPC85xx_PICGCR_RST 0x80000000