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authorWolfgang Denk <wd@denx.de>2007-06-22 23:59:00 +0200
committerWolfgang Denk <wd@denx.de>2007-06-22 23:59:00 +0200
commit1636d1c8529c006d106287cfbc20cd0a246fe1cb (patch)
treecd39e784361c2bcef43cfc38d39b1670ce22d539
parent2dc64451b4c08ffd619372abfdc2506a2e2363b9 (diff)
downloadu-boot-linaro-stable-1636d1c8529c006d106287cfbc20cd0a246fe1cb.tar.gz
Coding stylke cleanup; rebuild CHANGELOG
-rw-r--r--CHANGELOG39
-rw-r--r--board/amcc/acadia/acadia.c14
-rw-r--r--board/bf537-stamp/ether_bf537.c2
-rw-r--r--board/bf537-stamp/flash-defines.h6
-rw-r--r--board/bf537-stamp/stm_m25p64.c2
-rw-r--r--board/bf537-stamp/u-boot.lds.S12
-rw-r--r--board/smdk2400/lowlevel_init.S2
-rw-r--r--common/cmd_log.c4
-rw-r--r--common/main.c2
-rw-r--r--cpu/mpc5xx/start.S2
-rw-r--r--cpu/mpc8260/start.S4
-rw-r--r--cpu/ppc4xx/44x_spd_ddr.c4
-rw-r--r--cpu/ppc4xx/44x_spd_ddr2.c4
-rw-r--r--cpu/ppc4xx/cpu_init.c2
-rw-r--r--include/asm-ppc/processor.h46
-rw-r--r--include/configs/TQM5200.h4
-rw-r--r--include/configs/alpr.h4
-rw-r--r--include/configs/bamboo.h14
-rw-r--r--include/configs/ebony.h2
-rw-r--r--include/configs/lwmon5.h4
-rw-r--r--include/configs/ocotea.h2
-rw-r--r--include/configs/p3p440.h2
-rw-r--r--include/configs/pcs440ep.h2
-rw-r--r--include/configs/sequoia.h2
-rw-r--r--include/configs/taishan.h4
-rw-r--r--include/configs/yosemite.h2
-rw-r--r--include/mpc5xx.h42
-rw-r--r--include/mpc824x.h6
-rw-r--r--include/mpc8260.h16
-rw-r--r--include/mpc83xx.h10
-rw-r--r--include/mpc8xx.h12
-rw-r--r--include/ppc405.h14
-rw-r--r--include/ppc440.h8
33 files changed, 167 insertions, 128 deletions
diff --git a/CHANGELOG b/CHANGELOG
index 08f625af0..e3c21f9bd 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,3 +1,42 @@
+commit 2dc64451b4c08ffd619372abfdc2506a2e2363b9
+Author: Igor Lisitsin <igor@emcraft.com>
+Date: Wed Apr 18 14:55:19 2007 +0400
+
+ Adapt log buffer code to support Linux 2.6
+
+ A new environment variable, "logversion", selects the log buffer
+ behaviour. If it is not set or set to a value other than 2, then the
+ old, Linux 2.4.4, behaviour is selected.
+
+ Signed-off-by: Igor Lisitsin <igor@emcraft.com>
+ --
+
+commit a11e06965ec91270c51853407ff1261d3c740386
+Author: Igor Lisitsin <igor@emcraft.com>
+Date: Wed Mar 28 19:06:19 2007 +0400
+
+ Extend POST support for PPC440
+
+ Added memory, CPU, UART, I2C and SPR POST tests for PPC440.
+
+ Signed-off-by: Igor Lisitsin <igor@emcraft.com>
+ --
+
+commit 02032e8f14751a1a751b09240a4f1cf9f8a2077f
+Author: Rafal Jaworowski <raj@semihalf.com>
+Date: Fri Jun 22 14:58:04 2007 +0200
+
+ [ppc] Fix build breakage for all non-4xx PowerPC variants.
+
+ - adapt to the more generic EXCEPTION_PROLOG and CRIT_EXCEPTION macros
+ - minor 4xx cleanup
+
+commit 83b4cfa3d629dff0264366263c5e94d9a50ad80b
+Author: Wolfgang Denk <wd@denx.de>
+Date: Wed Jun 20 18:14:24 2007 +0200
+
+ Coding style cleanup. Refresh CHANGELOG.
+
commit b3f9ec86e388207fd03dcdf7b145b9ed080bf024
Author: Stefan Roese <sr@denx.de>
Date: Tue Jun 19 17:22:44 2007 +0200
diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c
index 0f54025fb..8b82ea40e 100644
--- a/board/amcc/acadia/acadia.c
+++ b/board/amcc/acadia/acadia.c
@@ -31,13 +31,13 @@ static void acadia_gpio_init(void)
/*
* GPIO0 setup (select GPIO or alternate function)
*/
- out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
- out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
- out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
- out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
- out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
- out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
- out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
+ out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
+ out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
+ out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
+ out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
+ out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
+ out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
+ out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
/*
* Ultra (405EZ) was nice enough to add another GPIO controller
diff --git a/board/bf537-stamp/ether_bf537.c b/board/bf537-stamp/ether_bf537.c
index f00837aad..807b9e839 100644
--- a/board/bf537-stamp/ether_bf537.c
+++ b/board/bf537-stamp/ether_bf537.c
@@ -48,7 +48,7 @@
#define TXBUF_BASE_ADDR 0xFF800000
#define TX_BUF_CNT 1
-#define TOUT_LOOP 1000000
+#define TOUT_LOOP 1000000
ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
diff --git a/board/bf537-stamp/flash-defines.h b/board/bf537-stamp/flash-defines.h
index acc1e8638..1fa7a10bd 100644
--- a/board/bf537-stamp/flash-defines.h
+++ b/board/bf537-stamp/flash-defines.h
@@ -44,9 +44,9 @@
#define ERASE_SECT 6
#define READ 7
#define GET_SECTNUM 8
-#define FLASH_START_L 0x0000
-#define FLASH_START_H 0x2000
-#define FLASH_MAN_ST 2
+#define FLASH_START_L 0x0000
+#define FLASH_START_H 0x2000
+#define FLASH_MAN_ST 2
#define RESET_VAL 0xF0
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
diff --git a/board/bf537-stamp/stm_m25p64.c b/board/bf537-stamp/stm_m25p64.c
index 7077e85f4..d9c08ee8e 100644
--- a/board/bf537-stamp/stm_m25p64.c
+++ b/board/bf537-stamp/stm_m25p64.c
@@ -9,7 +9,7 @@
/* Application definitions */
-#define NUM_SECTORS 128 /* number of sectors */
+#define NUM_SECTORS 128 /* number of sectors */
#define SECTOR_SIZE 0x10000
#define NOP_NUM 1000
diff --git a/board/bf537-stamp/u-boot.lds.S b/board/bf537-stamp/u-boot.lds.S
index 3fb2d0cc6..8632097b6 100644
--- a/board/bf537-stamp/u-boot.lds.S
+++ b/board/bf537-stamp/u-boot.lds.S
@@ -33,7 +33,7 @@ SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
__DYNAMIC = 0; */
MEMORY
{
- ram : ORIGIN = (CFG_MONITOR_BASE), LENGTH = (256 * 1024)
+ ram : ORIGIN = (CFG_MONITOR_BASE), LENGTH = (256 * 1024)
l1_code : ORIGIN = 0xFFA00000, LENGTH = 0xC000
l1_data : ORIGIN = 0xFF900000, LENGTH = 0x4000
}
@@ -47,11 +47,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
+ .rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
@@ -68,7 +68,7 @@ SECTIONS
.text :
{
/* WARNING - the following is hand-optimized to fit within */
- /* the sector before the environment sector. If it throws */
+ /* the sector before the environment sector. If it throws */
/* an error during compilation remove an object here to get */
/* it linked after the configuration sector. */
diff --git a/board/smdk2400/lowlevel_init.S b/board/smdk2400/lowlevel_init.S
index a5de806af..a7959f391 100644
--- a/board/smdk2400/lowlevel_init.S
+++ b/board/smdk2400/lowlevel_init.S
@@ -117,7 +117,7 @@
#define TREFMD 0x0 /* CBR(CAS before RAS)/auto refresh */
#define Trp 0x0 /* 2 clk */
#define Trc 0x3 /* 7 clk */
-#define Tchr 0x2 /* 3 clk */
+#define Tchr 0x2 /* 3 clk */
#define REFCNT 1113 /* period=15.6 us, HCLK=60Mhz, (2048+1-15.6*66) */
diff --git a/common/cmd_log.c b/common/cmd_log.c
index 5bf811e75..fba8bd8bf 100644
--- a/common/cmd_log.c
+++ b/common/cmd_log.c
@@ -83,13 +83,13 @@ void logbuff_init_ptrs (void)
/* The post routines have setup the word so we can simply test it */
if (tag != LOGBUFF_MAGIC || (post_word & POST_COLDBOOT)) {
logbuff_reset ();
- }
+ }
#else
/* No post routines, so we do our own checking */
if (tag != LOGBUFF_MAGIC || post_word != LOGBUFF_MAGIC) {
logbuff_reset ();
post_word_store (LOGBUFF_MAGIC);
- }
+ }
#endif
if (log_version == 2 && (long)log->v2.start > (long)log->v2.con)
log->v2.start = log->v2.con;
diff --git a/common/main.c b/common/main.c
index 553ac357d..d8123a7ce 100644
--- a/common/main.c
+++ b/common/main.c
@@ -962,7 +962,7 @@ int readline (const char *const prompt)
n = 0;
continue;
- case 0x17: /* ^W - erase word */
+ case 0x17: /* ^W - erase word */
p=delete_char(console_buffer, p, &col, &n, plen);
while ((n > 0) && (*p != ' ')) {
p=delete_char(console_buffer, p, &col, &n, plen);
diff --git a/cpu/mpc5xx/start.S b/cpu/mpc5xx/start.S
index 95728373f..0637003ce 100644
--- a/cpu/mpc5xx/start.S
+++ b/cpu/mpc5xx/start.S
@@ -155,7 +155,7 @@ in_flash:
/* Initialize some SPRs that are hard to access from C */
/*----------------------------------------------------------------------*/
- lis r3, CFG_IMMR@h /* Pass IMMR as arg1 to C routine */
+ lis r3, CFG_IMMR@h /* Pass IMMR as arg1 to C routine */
lis r2, CFG_INIT_SP_ADDR@h
ori r1, r2, CFG_INIT_SP_ADDR@l /* Set up the stack in internal SRAM */
/* Note: R0 is still 0 here */
diff --git a/cpu/mpc8260/start.S b/cpu/mpc8260/start.S
index bc55b58ad..7f5dc819c 100644
--- a/cpu/mpc8260/start.S
+++ b/cpu/mpc8260/start.S
@@ -676,13 +676,13 @@ init_debug:
bdnz 1b
/* Load the Instruction Address Breakpoint Register (IABR). */
- /* */
+ /* */
/* The address to load is stored in the first word of dual port */
/* ram and should be preserved while the power is on, so you */
/* can plug addresses into that location then reset the cpu and */
/* this code will load that address into the IABR after the */
/* reset. */
- /* */
+ /* */
/* When the program counter matches the contents of the IABR, */
/* an exception is generated (before the instruction at that */
/* location completes). The vector for this exception is 0x1300 */
diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c
index fe7bbabd5..e24cd81b7 100644
--- a/cpu/ppc4xx/44x_spd_ddr.c
+++ b/cpu/ppc4xx/44x_spd_ddr.c
@@ -1340,14 +1340,14 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
*/
cr |= SDRAM_BXCR_SDBE;
- for (i = 0; i < num_banks; i++) {
+ for (i = 0; i < num_banks; i++) {
bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes =
(4 << 20) * bank_size_id;
bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr;
debug("DIMM%d-bank %d (SDRAM0_B%dCR): bank_size_bytes=%d\n",
dimm_num, i, ctrl_bank_num[dimm_num]+i,
bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes);
- }
+ }
}
}
diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index 874cec07e..b5c0f53d2 100644
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -58,8 +58,8 @@
#define SDRAM_DDR2 2
#define SDRAM_NONE 0
-#define MAXDIMMS 2
-#define MAXRANKS 4
+#define MAXDIMMS 2
+#define MAXRANKS 4
#define MAXBXCF 4
#define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */
diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
index bc1ae0e4e..351da36e8 100644
--- a/cpu/ppc4xx/cpu_init.c
+++ b/cpu/ppc4xx/cpu_init.c
@@ -153,7 +153,7 @@ cpu_init_f (void)
*/
asm volatile(" bl 0f" ::: "lr");
asm volatile("0: mflr 3" ::: "r3");
- asm volatile(" addi 4, 0, 14" ::: "r4");
+ asm volatile(" addi 4, 0, 14" ::: "r4");
asm volatile(" mtctr 4" ::: "ctr");
asm volatile("1: icbt 0, 3");
asm volatile(" addi 3, 3, 32" ::: "r3");
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 29e6101a1..9780fe15c 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -35,18 +35,18 @@
#define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */
#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */
#define MSR_BE (1<<9) /* Branch Trace */
-#define MSR_DE (1<<9) /* Debug Exception Enable */
+#define MSR_DE (1<<9) /* Debug Exception Enable */
#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
-#define MSR_IR (1<<5) /* Instruction Relocate */
+#define MSR_IR (1<<5) /* Instruction Relocate */
#define MSR_IS (1<<5) /* Book E Instruction space */
-#define MSR_DR (1<<4) /* Data Relocate */
+#define MSR_DR (1<<4) /* Data Relocate */
#define MSR_DS (1<<4) /* Book E Data space */
#define MSR_PE (1<<3) /* Protection Enable */
#define MSR_PX (1<<2) /* Protection Exclusive Mode */
#define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */
#define MSR_RI (1<<1) /* Recoverable Exception */
-#define MSR_LE (1<<0) /* Little Endian */
+#define MSR_LE (1<<0) /* Little Endian */
#ifdef CONFIG_APUS_FAST_EXCEPT
#define MSR_ MSR_ME|MSR_IP|MSR_RI
@@ -123,9 +123,9 @@
#define DBCR_EDM 0x80000000
#define DBCR_IDM 0x40000000
#define DBCR_RST(x) (((x) & 0x3) << 28)
-#define DBCR_RST_NONE 0
-#define DBCR_RST_CORE 1
-#define DBCR_RST_CHIP 2
+#define DBCR_RST_NONE 0
+#define DBCR_RST_CORE 1
+#define DBCR_RST_CHIP 2
#define DBCR_RST_SYSTEM 3
#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */
#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */
@@ -266,7 +266,7 @@
#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
-#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
+#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */
#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
#define SPRN_LR 0x008 /* Link Register */
@@ -495,17 +495,17 @@
#define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */
#define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */
#define DBSR SPRN_DBSR /* Debug Status Register */
-#define DCMP SPRN_DCMP /* Data TLB Compare Register */
-#define DEC SPRN_DEC /* Decrement Register */
-#define DMISS SPRN_DMISS /* Data TLB Miss Register */
+#define DCMP SPRN_DCMP /* Data TLB Compare Register */
+#define DEC SPRN_DEC /* Decrement Register */
+#define DMISS SPRN_DMISS /* Data TLB Miss Register */
#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */
-#define EAR SPRN_EAR /* External Address Register */
+#define EAR SPRN_EAR /* External Address Register */
#define ESR SPRN_ESR /* Exception Syndrome Register */
#define HASH1 SPRN_HASH1 /* Primary Hash Address Register */
#define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */
#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */
#define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */
-#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
+#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
#define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */
#define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */
#define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */
@@ -522,13 +522,13 @@
#define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */
#define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */
#define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */
-#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */
+#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */
#define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */
#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */
#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */
-#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
+#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */
-#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
+#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
#define LR SPRN_LR
#define MBAR SPRN_MBAR /* System memory base address */
#if defined(CONFIG_MPC86xx)
@@ -540,7 +540,7 @@
#define SVR SPRN_SVR /* System-On-Chip Version Register */
#define PVR SPRN_PVR /* Processor Version */
#define RPA SPRN_RPA /* Required Physical Address Register */
-#define SDR1 SPRN_SDR1 /* MMU hash base register */
+#define SDR1 SPRN_SDR1 /* MMU hash base register */
#define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */
#define SPR1 SPRN_SPRG1
#define SPR2 SPRN_SPRG2
@@ -611,7 +611,7 @@
#define IVOR35 SPRN_IVOR35
#define MCSRR0 SPRN_MCSRR0
#define MCSRR1 SPRN_MCSRR1
-#define L1CSR0 SPRN_L1CSR0
+#define L1CSR0 SPRN_L1CSR0
#define L1CSR1 SPRN_L1CSR1
#define MCSR SPRN_MCSR
#define MMUCSR0 SPRN_MMUCSR0
@@ -620,7 +620,7 @@
#define PID1 SPRN_PID1
#define PID2 SPRN_PID2
#define MAS0 SPRN_MAS0
-#define MAS1 SPRN_MAS1
+#define MAS1 SPRN_MAS1
#define MAS2 SPRN_MAS2
#define MAS3 SPRN_MAS3
#define MAS4 SPRN_MAS4
@@ -632,7 +632,7 @@
#define DCRN_BEAR 0x090 /* Bus Error Address Register */
#define DCRN_BESR 0x091 /* Bus Error Syndrome Register */
-#define BESR_DSES 0x80000000 /* Data-Side Error Status */
+#define BESR_DSES 0x80000000 /* Data-Side Error Status */
#define BESR_DMES 0x40000000 /* DMA Error Status */
#define BESR_RWS 0x20000000 /* Read/Write Status */
#define BESR_ETMASK 0x1C000000 /* Error Type */
@@ -689,8 +689,8 @@
#define IOCR_E3LP 0x01000000
#define IOCR_E4TE 0x00800000
#define IOCR_E4LP 0x00400000
-#define IOCR_EDT 0x00080000
-#define IOCR_SOR 0x00040000
+#define IOCR_EDT 0x00080000
+#define IOCR_SOR 0x00040000
#define IOCR_EDO 0x00008000
#define IOCR_2XC 0x00004000
#define IOCR_ATC 0x00002000
@@ -815,7 +815,7 @@
#define PVR_823 PVR_821
#define PVR_850 PVR_821
#define PVR_860 PVR_821
-#define PVR_7400 0x000C0000
+#define PVR_7400 0x000C0000
#define PVR_8240 0x00810100
/*
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index 9da1d884b..aa3627b4d 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -44,7 +44,7 @@
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
@@ -238,7 +238,7 @@
"fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0" \
"u-boot=/tftpboot/tqm5200/u-boot.bin\0"
#else
-#define CUSTOM_ENV_SETTINGS \
+#define CUSTOM_ENV_SETTINGS \
"bootfile=cam5200/uImage\0" \
"u-boot=cam5200/u-boot.bin\0" \
"setup=tftp 200000 cam5200/setup.img; autoscr 200000\0"
diff --git a/include/configs/alpr.h b/include/configs/alpr.h
index 47893e824..3e571db0e 100644
--- a/include/configs/alpr.h
+++ b/include/configs/alpr.h
@@ -95,7 +95,7 @@
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
@@ -257,7 +257,7 @@
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h
index af337eee8..cd5844363 100644
--- a/include/configs/bamboo.h
+++ b/include/configs/bamboo.h
@@ -74,9 +74,9 @@
* Initial RAM & stack pointer (placed in SDRAM)
*----------------------------------------------------------------------*/
#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */
-#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
+#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
#define CFG_INIT_RAM_END (4 << 10)
-#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
@@ -115,8 +115,8 @@
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
-#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
-#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
+#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
+#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
@@ -126,11 +126,11 @@
#define CFG_FLASH_ADDR1 0x2aa
#define CFG_FLASH_WORD_SIZE unsigned char
-#define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */
-#define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */
+#define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */
+#define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */
#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
diff --git a/include/configs/ebony.h b/include/configs/ebony.h
index 5bd326b9a..09efe1d40 100644
--- a/include/configs/ebony.h
+++ b/include/configs/ebony.h
@@ -122,7 +122,7 @@
#define CFG_FLASH_WORD_SIZE unsigned char
#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index 675df7626..ab42b5962 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -117,7 +117,7 @@
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
-#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
@@ -360,7 +360,7 @@
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \
diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h
index 31f8bb3fd..931fb820d 100644
--- a/include/configs/ocotea.h
+++ b/include/configs/ocotea.h
@@ -137,7 +137,7 @@
#define CFG_FLASH_WORD_SIZE unsigned char
#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h
index cae5bd56f..f67c51354 100644
--- a/include/configs/p3p440.h
+++ b/include/configs/p3p440.h
@@ -286,7 +286,7 @@
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h
index 040e58959..333b4a2b7 100644
--- a/include/configs/pcs440ep.h
+++ b/include/configs/pcs440ep.h
@@ -104,7 +104,7 @@
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index ae1c12910..7b7fb9eb4 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -127,7 +127,7 @@
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
diff --git a/include/configs/taishan.h b/include/configs/taishan.h
index cbbb0066e..b45c51dc9 100644
--- a/include/configs/taishan.h
+++ b/include/configs/taishan.h
@@ -218,8 +218,8 @@
#define CONFIG_EMAC_NR_START 2 /* start with EMAC 2 (skip 0&1) */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_NET_MULTI 1
-#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
-#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
+#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
+#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
#define CONFIG_PHY2_ADDR 0x1
#define CONFIG_PHY3_ADDR 0x3
#define CONFIG_ET1011C_PHY 1
diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h
index c96b14e83..b036d444d 100644
--- a/include/configs/yosemite.h
+++ b/include/configs/yosemite.h
@@ -123,7 +123,7 @@
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
diff --git a/include/mpc5xx.h b/include/mpc5xx.h
index e9b08a0dc..414651fa0 100644
--- a/include/mpc5xx.h
+++ b/include/mpc5xx.h
@@ -76,10 +76,10 @@
#define SIUMCR_DBPC01 0x00080000 /* - " - */
#define SIUMCR_DBPC10 0x00100000 /* - " - */
#define SIUMCR_DBPC11 0x00180000 /* - " - */
-#define SIUMCR_GPC00 0x00000000 /* General Pins Config */
-#define SIUMCR_GPC01 0x00020000 /* General Pins Config */
-#define SIUMCR_GPC10 0x00040000 /* General Pins Config */
-#define SIUMCR_GPC11 0x00060000 /* General Pins Config */
+#define SIUMCR_GPC00 0x00000000 /* General Pins Config */
+#define SIUMCR_GPC01 0x00020000 /* General Pins Config */
+#define SIUMCR_GPC10 0x00040000 /* General Pins Config */
+#define SIUMCR_GPC11 0x00060000 /* General Pins Config */
#define SIUMCR_DLK 0x00010000 /* Debug Register Lock */
#define SIUMCR_SC00 0x00000000 /* Multi Chip 32 bit */
#define SIUMCR_SC01 0x00004000 /* Muilt Chip 16 bit */
@@ -90,7 +90,7 @@
#define SIUMCR_MLRC01 0x00000400 /* - " - */
#define SIUMCR_MLRC10 0x00000800 /* - " - */
#define SIUMCR_MLRC11 0x00000c00 /* - " - */
-#define SIUMCR_MTSC 0x00000100 /* Memory transfer */
+#define SIUMCR_MTSC 0x00000100 /* Memory transfer */
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control Register
@@ -123,13 +123,13 @@
* SCCR - System Clock and reset Control Register
*/
#define SCCR_DFNL_MSK 0x00000070 /* DFNL mask */
-#define SCCR_DFNH_MSK 0x00000007 /* DFNH mask */
+#define SCCR_DFNH_MSK 0x00000007 /* DFNH mask */
#define SCCR_DFNL_SHIFT 0x0000004 /* DFNL shift value */
#define SCCR_RTSEL 0x00100000 /* RTC circuit input source select */
#define SCCR_EBDF00 0x00000000 /* Division factor 1. CLKOUT is GCLK2 */
#define SCCR_EBDF11 0x00060000 /* reserved */
#define SCCR_TBS 0x02000000 /* Time Base Source */
-#define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */
+#define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */
#define SCCR_COM00 0x00000000 /* full strength CLKOUT output buffer */
#define SCCR_COM01 0x20000000 /* half strength CLKOUT output buffer */
#define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */
@@ -138,11 +138,11 @@
/*-----------------------------------------------------------------------
* MC - Memory Controller
*/
-#define BR_V 0x00000001 /* Bank valid */
-#define BR_BI 0x00000002 /* Burst inhibit */
-#define BR_PS_8 0x00000400 /* 8 bit port size */
-#define BR_PS_16 0x00000800 /* 16 bit port size */
-#define BR_PS_32 0x00000000 /* 32 bit port size */
+#define BR_V 0x00000001 /* Bank valid */
+#define BR_BI 0x00000002 /* Burst inhibit */
+#define BR_PS_8 0x00000400 /* 8 bit port size */
+#define BR_PS_16 0x00000800 /* 16 bit port size */
+#define BR_PS_32 0x00000000 /* 32 bit port size */
#define BR_LBDIR 0x00000008 /* Late burst data in progess */
#define BR_SETA 0x00000004 /* External Data Acknowledge */
#define OR_SCY_3 0x00000030 /* 3 clock cycles wait states */
@@ -159,8 +159,8 @@
/*-----------------------------------------------------------------------
* UMCR - UIMB Module Configuration Register
*/
-#define UMCR_FSPEED 0x00000000 /* Full speed. Opposit of UMCR_HSPEED */
-#define UMCR_HSPEED 0x10000000 /* Half speed */
+#define UMCR_FSPEED 0x00000000 /* Full speed. Opposit of UMCR_HSPEED */
+#define UMCR_HSPEED 0x10000000 /* Half speed */
/*-----------------------------------------------------------------------
* ICTRL - I-Bus Support Control Register
@@ -174,16 +174,16 @@
* SCI - Serial communication interface
*/
-#define SCI_TDRE 0x0100 /* Transmit data register empty */
-#define SCI_TE 0x0008 /* Transmitter enabled */
+#define SCI_TDRE 0x0100 /* Transmit data register empty */
+#define SCI_TE 0x0008 /* Transmitter enabled */
#define SCI_RE 0x0004 /* Receiver enabled */
-#define SCI_RDRF 0x0040 /* Receive data register full */
-#define SCI_PE 0x0400 /* Parity enable */
-#define SCI_SCXBR_MK 0x1fff /* Baudrate mask */
-#define SCI_SCXDR_MK 0x00ff /* Data register mask */
+#define SCI_RDRF 0x0040 /* Receive data register full */
+#define SCI_PE 0x0400 /* Parity enable */
+#define SCI_SCXBR_MK 0x1fff /* Baudrate mask */
+#define SCI_SCXDR_MK 0x00ff /* Data register mask */
#define SCI_M_11 0x0200 /* Frame size is 11 bit */
#define SCI_M_10 0x0000 /* Frame size is 10 bit */
-#define SCI_PORT_1 ((int)1) /* Place this later somewhere better */
+#define SCI_PORT_1 ((int)1) /* Place this later somewhere better */
#define SCI_PORT_2 ((int)2)
#endif /* __MPC5XX_H__ */
diff --git a/include/mpc824x.h b/include/mpc824x.h
index 4bd886348..30f01d5aa 100644
--- a/include/mpc824x.h
+++ b/include/mpc824x.h
@@ -88,7 +88,7 @@
#define PREP_PCI_MEMORY_BUS 0x80000000
#define PREP_PCI_MEMORY_SIZE 0x80000000
#define MPC107_PCI_CMD 0x80000004 /* MPC107 PCI cmd reg */
-#define MPC107_PCI_STAT 0x80000006 /* MPC107 PCI status reg */
+#define MPC107_PCI_STAT 0x80000006 /* MPC107 PCI status reg */
#define PROC_INT1_ADR 0x800000a8 /* MPC107 Processor i/f cfg1 */
#define PROC_INT2_ADR 0x800000ac /* MPC107 Processor i/f cfg2 */
#define MEM_CONT1_ADR 0x800000f0 /* MPC107 Memory control config. 1 */
@@ -98,8 +98,8 @@
#define MEM_ERREN1_ADR 0x800000c0 /* MPC107 Memory error enable 1 */
#define MEM_START1_ADR 0x80000080 /* MPC107 Memory starting addr */
#define MEM_START2_ADR 0x80000084 /* MPC107 Memory starting addr-lo */
-#define XMEM_START1_ADR 0x80000088 /* MPC107 Extended mem. start addr-hi*/
-#define XMEM_START2_ADR 0x8000008c /* MPC107 Extended mem. start addr-lo*/
+#define XMEM_START1_ADR 0x80000088 /* MPC107 Extended mem. start addr-hi*/
+#define XMEM_START2_ADR 0x8000008c /* MPC107 Extended mem. start addr-lo*/
#define MEM_END1_ADR 0x80000090 /* MPC107 Memory ending address */
#define MEM_END2_ADR 0x80000094 /* MPC107 Memory ending addr-lo */
#define XMEM_END1_ADR 0x80000098 /* MPC107 Extended mem. end addrs-hi */
diff --git a/include/mpc8260.h b/include/mpc8260.h
index b61218ccc..052529409 100644
--- a/include/mpc8260.h
+++ b/include/mpc8260.h
@@ -664,7 +664,7 @@
#define PSDMR_CL_3 0x00000003 /* CAS Latency = 3 */
/*-----------------------------------------------------------------------
- * LSDMR - Local Bus SDRAM Mode Register 10-24
+ * LSDMR - Local Bus SDRAM Mode Register 10-24
*/
/*
@@ -707,23 +707,23 @@
/*-----------------------------------------------------------------------
* TMR1-TMR4 - Timer Mode Registers 17-6
*/
-#define TMRx_PS_MSK 0xff00 /* Prescaler Value */
+#define TMRx_PS_MSK 0xff00 /* Prescaler Value */
#define TMRx_CE_MSK 0x00c0 /* Capture Edge and Enable Interrupt*/
-#define TMRx_OM 0x0020 /* Output Mode */
+#define TMRx_OM 0x0020 /* Output Mode */
#define TMRx_ORI 0x0010 /* Output Reference Interrupt Enable*/
-#define TMRx_FRR 0x0008 /* Free Run/Restart */
+#define TMRx_FRR 0x0008 /* Free Run/Restart */
#define TMRx_ICLK_MSK 0x0006 /* Timer Input Clock Source mask */
-#define TMRx_GE 0x0001 /* Gate Enable */
+#define TMRx_GE 0x0001 /* Gate Enable */
#define TMRx_CE_INTR_DIS 0x0000 /* Disable Interrupt on capture event*/
#define TMRx_CE_RISING 0x0040 /* Capture on Rising TINx edge only */
#define TMRx_CE_FALLING 0x0080 /* Capture on Falling TINx edge only */
-#define TMRx_CE_ANY 0x00c0 /* Capture on any TINx edge */
+#define TMRx_CE_ANY 0x00c0 /* Capture on any TINx edge */
-#define TMRx_ICLK_IN_CAS 0x0000 /* Internally cascaded input */
+#define TMRx_ICLK_IN_CAS 0x0000 /* Internally cascaded input */
#define TMRx_ICLK_IN_GEN 0x0002 /* Internal General system clock*/
#define TMRx_ICLK_IN_GEN_DIV16 0x0004 /* Internal General system clk div 16*/
-#define TMRx_ICLK_TIN_PIN 0x0006 /* TINx pin */
+#define TMRx_ICLK_TIN_PIN 0x0006 /* TINx pin */
/*-----------------------------------------------------------------------
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index cbf41c3a9..336c0ac4f 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -439,9 +439,9 @@
#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
#if defined(CONFIG_MPC831X)
-#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000
+#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000
#define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000
-#define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000
+#define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000
#define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000
#define HRCWH_RL_EXT_LEGACY 0x00000000
@@ -1218,7 +1218,7 @@
#define FCR_CMD1 0x00FF0000
#define FCR_CMD1_SHIFT 16
#define FCR_CMD2 0x0000FF00
-#define FCR_CMD2_SHIFT 8
+#define FCR_CMD2_SHIFT 8
#define FCR_CMD3 0x000000FF
#define FCR_CMD3_SHIFT 0
@@ -1242,8 +1242,8 @@
/* LTESR - Transfer Error Status Register
*/
#define LTESR_BM 0x80000000
-#define LTESR_FCT 0x40000000
-#define LTESR_PAR 0x20000000
+#define LTESR_FCT 0x40000000
+#define LTESR_PAR 0x20000000
#define LTESR_WP 0x04000000
#define LTESR_ATMW 0x00800000
#define LTESR_ATMR 0x00400000
diff --git a/include/mpc8xx.h b/include/mpc8xx.h
index 11305987f..bef748f90 100644
--- a/include/mpc8xx.h
+++ b/include/mpc8xx.h
@@ -208,12 +208,12 @@
#define SCCR_DFBRG10 0x00001000 /* BRGCLK division by 16 */
#define SCCR_DFBRG11 0x00001800 /* BRGCLK division by 64 */
#define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */
-#define SCCR_DFNL001 0x00000100 /* Division by 4 */
-#define SCCR_DFNL010 0x00000200 /* Division by 8 */
-#define SCCR_DFNL011 0x00000300 /* Division by 16 */
-#define SCCR_DFNL100 0x00000400 /* Division by 32 */
-#define SCCR_DFNL101 0x00000500 /* Division by 64 */
-#define SCCR_DFNL110 0x00000600 /* Division by 128 */
+#define SCCR_DFNL001 0x00000100 /* Division by 4 */
+#define SCCR_DFNL010 0x00000200 /* Division by 8 */
+#define SCCR_DFNL011 0x00000300 /* Division by 16 */
+#define SCCR_DFNL100 0x00000400 /* Division by 32 */
+#define SCCR_DFNL101 0x00000500 /* Division by 64 */
+#define SCCR_DFNL110 0x00000600 /* Division by 128 */
#define SCCR_DFNL111 0x00000700 /* Division by 256 (maximum) */
#define SCCR_DFNH000 0x00000000 /* Division by 1 (default = minimum) */
#define SCCR_DFNH110 0x000000D0 /* Division by 64 (maximum) */
diff --git a/include/ppc405.h b/include/ppc405.h
index 6be2a50db..8e6473192 100644
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -143,12 +143,12 @@
#define UIC_USBH1 0x00040000 /* USB Host 1 */
#define UIC_USBH2 0x00020000 /* USB Host 2 */
#define UIC_USBDEV 0x00010000 /* USB Device */
-#define UIC_ENET 0x00008000 /* Ethernet interrupt status */
-#define UIC_ENET1 0x00008000 /* dummy define */
+#define UIC_ENET 0x00008000 /* Ethernet interrupt status */
+#define UIC_ENET1 0x00008000 /* dummy define */
#define UIC_EMAC_WAKE 0x00004000 /* EMAC wake up */
#define UIC_MADMAL 0x00002000 /* Logical OR of following MadMAL int */
-#define UIC_MAL_SERR 0x00002000 /* MAL SERR */
+#define UIC_MAL_SERR 0x00002000 /* MAL SERR */
#define UIC_MAL_TXDE 0x00002000 /* MAL TXDE */
#define UIC_MAL_RXDE 0x00002000 /* MAL RXDE */
@@ -886,7 +886,7 @@
#define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */
#define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */
#define reset (CNTRL_DCR_BASE+0x3) /* reset register */
-#define strap (CNTRL_DCR_BASE+0x4) /* strap register */
+#define strap (CNTRL_DCR_BASE+0x4) /* strap register */
#define ecr (0xaa) /* edge conditioner register (405gpr) */
@@ -1119,13 +1119,13 @@
| UART Register Offsets
'----------------------------------------------------------------------------*/
#define DATA_REG 0x00
-#define DL_LSB 0x00
-#define DL_MSB 0x01
+#define DL_LSB 0x00
+#define DL_MSB 0x01
#define INT_ENABLE 0x01
#define FIFO_CONTROL 0x02
#define LINE_CONTROL 0x03
#define MODEM_CONTROL 0x04
-#define LINE_STATUS 0x05
+#define LINE_STATUS 0x05
#define MODEM_STATUS 0x06
#define SCRATCH 0x07
diff --git a/include/ppc440.h b/include/ppc440.h
index 9ba47a53c..76330f16a 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -112,7 +112,7 @@
#define icdbtrh 0x39f /* instruction cache debug tag register high */
#define mmucr 0x3b2 /* mmu control register */
#define ccr0 0x3b3 /* core configuration register 0 */
-#define ccr1 0x378 /* core configuration for 440x5 only */
+#define ccr1 0x378 /* core configuration for 440x5 only */
#define icdbdr 0x3d3 /* instruction cache debug data register */
#define dbdr 0x3f3 /* debug data register */
@@ -136,7 +136,7 @@
#define clk_opbd 0x00c0
#define clk_perd 0x00e0
#define clk_mald 0x0100
-#define clk_spcid 0x0120
+#define clk_spcid 0x0120
#define clk_icfg 0x0140
/* 440gx sdr register definations */
@@ -686,8 +686,8 @@
#define SDRAM_CODT_CKSE_SINGLE_END 0x00000008
#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004
#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002
-#define SDRAM_CODT_IO_HIZ 0x00000000
-#define SDRAM_CODT_IO_NMODE 0x00000001
+#define SDRAM_CODT_IO_HIZ 0x00000000
+#define SDRAM_CODT_IO_NMODE 0x00000001
/*-----------------------------------------------------------------------------+
| SDRAM Mode Register