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authorAjay Kumar <ajaykumar.rs@samsung.com>2013-01-08 20:42:23 +0000
committerMinkyu Kang <mk7.kang@samsung.com>2013-01-10 10:19:47 +0900
commit1673f199d917e0649098e0cb7ef5b375b96bd6cb (patch)
tree827f9a574affebaab94e75ee1f909585f4c2357b
parent9b572852c0547365b186651d27b3df5dcbe82be2 (diff)
downloadu-boot-linaro-stable-1673f199d917e0649098e0cb7ef5b375b96bd6cb.tar.gz
EXYNOS5: Change parent clock of FIMD to MPLL
With VPLL as source clock to FIMD, Exynos DP Initializaton was failing sometimes with unstable clock. Changing FIMD source to MPLL resolves this issue. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
-rw-r--r--arch/arm/cpu/armv7/exynos/clock.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index ae6d7fe0d..abc327262 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -741,7 +741,7 @@ void exynos5_set_lcd_clk(void)
*/
cfg = readl(&clk->src_disp1_0);
cfg &= ~(0xf);
- cfg |= 0x8;
+ cfg |= 0x6;
writel(cfg, &clk->src_disp1_0);
/*