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authorStefan Roese <sr@denx.de>2011-09-16 12:54:58 +0200
committerStefan Roese <sr@denx.de>2011-09-19 11:51:21 +0200
commit226502e01bc7ffa79dde28604075949f8f816cfc (patch)
treea786456a3bbf3c4cc35d211e6a7f5b82ffc72bb0
parent25fb02abdf7af37b3b9f83891115ee94e9073708 (diff)
downloadu-boot-linaro-stable-226502e01bc7ffa79dde28604075949f8f816cfc.tar.gz
ppc4xx: Flush dcache after DDR2 autocalibration with caches on
Flush the dcache before removing the TLB with caches enabled. Otherwise this might lead to problems later on, e.g. while booting Linux (as seen on ICON-440SPe). Signed-off-by: Stefan Roese <sr@denx.de>
-rw-r--r--arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
index 95df1d94c..4a2f33744 100644
--- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
@@ -657,6 +657,13 @@ phys_size_t initdram(int board_type)
#endif
/*
+ * Flush the dcache before removing the TLB with caches
+ * enabled. Otherwise this might lead to problems later on,
+ * e.g. while booting Linux (as seen on ICON-440SPe).
+ */
+ flush_dcache();
+
+ /*
* Now after initialization (auto-calibration and ECC generation)
* remove the TLB entries with caches enabled and program again with
* desired cache functionality