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authorPaul Gortmaker <paul.gortmaker@windriver.com>2009-08-21 16:21:58 -0500
committerKim Phillips <kim.phillips@freescale.com>2009-08-21 17:09:21 -0500
commitc0d660fbbede322648ec79d3e39389e48f5fab24 (patch)
treee41040f048252a48c91a4645f7d88dc52910678b
parent1aada9cd643567d351667138851e9231ccfa245a (diff)
downloadu-boot-linaro-stable-c0d660fbbede322648ec79d3e39389e48f5fab24.tar.gz
mpc83xx: sbc8349 - make enabling PCI more user friendly
Prior to this commit, to enable PCI, you had to go manually edit the board config header, which isn't really user friendly. This adds the typical PCI make targets to the toplevel Makefile in accordance with what is being done with other boards. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
-rw-r--r--Makefile19
-rw-r--r--doc/README.sbc834950
-rw-r--r--include/configs/sbc8349.h22
3 files changed, 64 insertions, 27 deletions
diff --git a/Makefile b/Makefile
index 2636ac055..96cca232b 100644
--- a/Makefile
+++ b/Makefile
@@ -2380,8 +2380,23 @@ MPC837XERDB_config: unconfig
MVBLM7_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc83xx mvblm7 matrix_vision
-sbc8349_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349
+sbc8349_config \
+sbc8349_PCI_33_config \
+sbc8349_PCI_66_config: unconfig
+ @mkdir -p $(obj)include
+ @if [ "$(findstring _PCI_,$@)" ] ; then \
+ $(XECHO) -n "... PCI HOST at " ; \
+ echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \
+ fi ; \
+ if [ "$(findstring _33_,$@)" ] ; then \
+ $(XECHO) -n "33MHz... " ; \
+ echo "#define PCI_33M" >>$(obj)include/config.h ; \
+ fi ; \
+ if [ "$(findstring _66_,$@)" ] ; then \
+ $(XECHO) -n "66MHz... " ; \
+ echo "#define PCI_66M" >>$(obj)include/config.h ; \
+ fi ;
+ @$(MKCONFIG) -a sbc8349 ppc mpc83xx sbc8349
SIMPC8313_LP_config \
SIMPC8313_SP_config: unconfig
diff --git a/doc/README.sbc8349 b/doc/README.sbc8349
index 908e7680a..2c35919f2 100644
--- a/doc/README.sbc8349
+++ b/doc/README.sbc8349
@@ -91,19 +91,37 @@ safety check before resetting the board upon completion of the reflash.
PCI:
====
-This board and U-Boot have been tested with PCI built in, on a SBC8349
-and confirmed that the "pci" command showed the intel e1000 that was
-present in the PCI slot. Note that if a 33MHz 32bit card is inserted
-in the slot, then the whole board will clock down to a 33MHz base
-clock instead of the default 66MHz. This will change the baud clocks
-and mess up your serial console output. If you want to use a 33MHz PCI
-card, then you should build a U-Boot with #undef PCI_66M in the
-include/configs/sbc8349.h and store this to flash prior to powering down
-the board and inserting the 33MHz PCI card.
-
-By default PCI support is disabled to better support very early
-revision MPC834x chips with possible PCI issues. Also PCI support is
-untested on the sbc8347 variants at this point in time.
-
-
- Paul Gortmaker, 01/2007
+There are three configuration choices:
+ sbc8349_config
+ sbc8349_PCI_33_config
+ sbc8349_PCI_66_config
+
+The 1st does not enable CONFIG_PCI, and assumes that the PCI slot
+will be left empty (M66EN high), and so the board will operate with
+a base clock of 66MHz. Note that you need both PCI enabled in u-boot
+and linux in order to have functional PCI under linux. The only
+reason for choosing to not enable PCI would be if you had a very
+early (rev 1.0) CPU with possible PCI issues.
+
+The second enables PCI support and builds for a 33MHz clock rate. Note
+that if a 33MHz 32bit card is inserted in the slot, then the whole board
+will clock down to a 33MHz base clock instead of the default 66MHz. This
+will change the baud clocks and mess up your serial console output if you
+were previously running at 66MHz. If you want to use a 33MHz PCI card,
+then you should build a U-Boot with sbc8349_PCI_33_config and store this
+to flash prior to powering down the board and inserting the 33MHz PCI
+card.
+
+The third option builds PCI support in, and leaves the clocking at the
+default 66MHz. This has been tested with an intel PCI-X e1000 card.
+This is also the appropriate choice for people with a recent (non 1.0)
+CPU who currently have the PCI slot physically empty, but intend to
+possibly add a PCI-X card at a later date.
+
+ => pci
+ Scanning PCI devices on bus 0
+ BusDevFun VendorId DeviceId Device Class Sub-Class
+ _____________________________________________________________
+ 00.00.00 0x1957 0x0080 Processor 0x20
+ 00.11.00 0x8086 0x1026 Network controller 0x00
+ =>
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 868bd54a6..088b28356 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -40,24 +40,28 @@
#define CONFIG_MPC8349 1 /* MPC8349 specific */
#define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */
-#undef CONFIG_PCI
/* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
-#define PCI_66M
-#ifdef PCI_66M
-#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
-#else
+/*
+ * The default if PCI isn't enabled, or if no PCI clk setting is given
+ * is 66MHz; this is what the board defaults to when the PCI slot is
+ * physically empty. The board will automatically (i.e w/o jumpers)
+ * clock down to 33MHz if you insert a 33MHz PCI card.
+ */
+#ifdef PCI_33M
#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
+#else /* 66M */
+#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
#endif
#ifndef CONFIG_SYS_CLK_FREQ
-#ifdef PCI_66M
-#define CONFIG_SYS_CLK_FREQ 66000000
-#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
-#else
+#ifdef PCI_33M
#define CONFIG_SYS_CLK_FREQ 33000000
#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
+#else /* 66M */
+#define CONFIG_SYS_CLK_FREQ 66000000
+#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
#endif
#endif