diff options
| author | Fabio Estevam <fabio.estevam@freescale.com> | 2011-09-02 05:38:55 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-09-30 22:00:59 +0200 |
| commit | 957dc024742829870e0489ad81e587b3f16cbc66 (patch) | |
| tree | d5922c6338725154cbdf0a46f480b246de4d7230 | |
| parent | 986d0d1bc53e95aac988c1d4737f35ce94a593ca (diff) | |
ARM: mx25: Print the source of reset
Print the source of reset during boot.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| -rw-r--r-- | arch/arm/cpu/arm926ejs/mx25/generic.c | 25 |
1 files changed, 24 insertions, 1 deletions
diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c index 21fe44f18..126164020 100644 --- a/arch/arm/cpu/arm926ejs/mx25/generic.c +++ b/arch/arm/cpu/arm926ejs/mx25/generic.c @@ -105,6 +105,28 @@ ulong imx_get_perclk (int clk) return lldiv (fref, div); } +static char *get_reset_cause(void) +{ + /* read RCSR register from CCM module */ + struct ccm_regs *ccm = + (struct ccm_regs *)IMX_CCM_BASE; + + u32 cause = readl(&ccm->rcsr) & 0x0f; + + if (cause == 0) + return "POR"; + else if (cause == 1) + return "RST"; + else if ((cause & 2) == 2) + return "WDOG"; + else if ((cause & 4) == 4) + return "SW RESET"; + else if ((cause & 8) == 8) + return "JTAG"; + else + return "unknown reset"; + +} u32 get_cpu_rev(void) { @@ -136,10 +158,11 @@ int print_cpuinfo (void) char buf[32]; u32 cpurev = get_cpu_rev(); - printf("CPU: Freescale i.MX25 rev%d.%d%s at %s MHz\n\n", + printf("CPU: Freescale i.MX25 rev%d.%d%s at %s MHz\n", (cpurev & 0xF0) >> 4, (cpurev & 0x0F), ((cpurev & 0x8000) ? " unknown" : ""), strmhz (buf, imx_get_armclk ())); + printf("Reset cause: %s\n\n", get_reset_cause()); return 0; } #endif |