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authorWolfgang Denk <wd@denx.de>2011-05-15 23:20:10 +0200
committerWolfgang Denk <wd@denx.de>2011-05-15 23:20:10 +0200
commit77467e25600825d2777acec81fd5c12d9b6f6390 (patch)
treee9624193509e0608d4f5b4192cd496bfb0f9a641
parent91081e01b10d64e99dc485e477e6ae3b1171e8ce (diff)
parentd49f8e04dba056803a80388798b735814b893bbf (diff)
downloadu-boot-linaro-stable-77467e25600825d2777acec81fd5c12d9b6f6390.tar.gz
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
-rw-r--r--arch/powerpc/cpu/mpc85xx/fdt.c29
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c6
2 files changed, 22 insertions, 13 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 6e909b52d..97d3928e1 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -165,7 +165,6 @@ static inline void ft_fixup_l2cache(void *blob)
int len, off;
u32 *ph;
struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
- char compat_buf[38];
const u32 line_size = 32;
const u32 num_ways = 8;
@@ -192,22 +191,32 @@ static inline void ft_fixup_l2cache(void *blob)
}
if (cpu) {
- if (isdigit(cpu->name[0]))
- len = sprintf(compat_buf,
- "fsl,mpc%s-l2-cache-controller", cpu->name);
- else
- len = sprintf(compat_buf,
- "fsl,%c%s-l2-cache-controller",
- tolower(cpu->name[0]), cpu->name + 1);
+ char buf[40];
+
+ if (isdigit(cpu->name[0])) {
+ /* MPCxxxx, where xxxx == 4-digit number */
+ len = sprintf(buf, "fsl,mpc%s-l2-cache-controller",
+ cpu->name) + 1;
+ } else {
+ /* Pxxxx or Txxxx, where xxxx == 4-digit number */
+ len = sprintf(buf, "fsl,%c%s-l2-cache-controller",
+ tolower(cpu->name[0]), cpu->name + 1) + 1;
+ }
+
+ /*
+ * append "cache" after the NULL character that the previous
+ * sprintf wrote. This is how a device tree stores multiple
+ * strings in a property.
+ */
+ len += sprintf(buf + len, "cache") + 1;
- sprintf(&compat_buf[len + 1], "cache");
+ fdt_setprop(blob, off, "compatible", buf, len);
}
fdt_setprop(blob, off, "cache-unified", NULL, 0);
fdt_setprop_cell(blob, off, "cache-block-size", line_size);
fdt_setprop_cell(blob, off, "cache-size", size);
fdt_setprop_cell(blob, off, "cache-sets", num_sets);
fdt_setprop_cell(blob, off, "cache-level", 2);
- fdt_setprop(blob, off, "compatible", compat_buf, sizeof(compat_buf));
/* we dont bother w/L3 since no platform of this type has one */
}
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
index 00f3d6c60..8132e68d9 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
@@ -38,9 +38,9 @@ compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
}
/* validate if the memory clk is in the range of dimms */
if (mclk_ps < tCKmin_X_ps) {
- printf("The DIMM max tCKmin is %d ps,"
- "doesn't support the MCLK cycle %d ps\n",
- tCKmin_X_ps, mclk_ps);
+ printf("DDR clock (MCLK cycle %u ps) is faster than "
+ "the slowest DIMM(s) (tCKmin %u ps) can support.\n",
+ mclk_ps, tCKmin_X_ps);
return 1;
}
/* determine the acutal cas latency */