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authorIra W. Snyder <iws@ovro.caltech.edu>2011-12-24 08:06:19 +0100
committerJohn Rigby <john.rigby@linaro.org>2012-01-19 17:08:51 -0700
commitd655720cd66251e82d8cc77cdcb7e7d44089e7c0 (patch)
tree09dd50e00035ea500bc0c81635a5a20738d2665b
parentba5ee185ad76cb41f028e5816f7f1d0e4e5ef724 (diff)
fsl_esdhc: fix PIO mode transfers
The pointer to the registers used to control the Freescale ESDHC MMC controller is not initialized correctly when using PIO mode. This is fixed by initializing the pointer in the same way as all other sites within the driver. Examining the commit history shows that this was broken at introduction due to a code change in upstream U-Boot to support the mx51 processor family. Reported-by: Jim Lentz <JLentz@zhone.com> Cc: Andy Fleming <afleming@freescale.com> Cc: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
-rw-r--r--drivers/mmc/fsl_esdhc.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index ddd1b4c6f..30db030b7 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -114,7 +114,8 @@ uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
static void
esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
{
- struct fsl_esdhc *regs = mmc->priv;
+ struct fsl_esdhc_cfg *cfg = mmc->priv;
+ struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
uint blocks;
char *buffer;
uint databuf;