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authorRyan Harkin <ryan.harkin@linaro.org>2013-06-14 13:50:38 +0100
committerRyan Harkin <ryan.harkin@linaro.org>2013-06-14 13:50:38 +0100
commitaa495330fac68d9e2220510cc25040ab92500f6d (patch)
tree24ac3b8c02458d09983e3ab32a23b12ed367063a /readme.txt
parent75bef16f29442eda1f3de3e268fd17f992d253a0 (diff)
parent4b09e17342c99b7bf8f9f3dbe3abf362c3008de8 (diff)
downloadvexpress-firmware-aa495330fac68d9e2220510cc25040ab92500f6d.tar.gz
Merge branch 'arm-releases'
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+This patch to Versatile Express DVD version 5.0 provides
+an updated Boot Monitor as well as updated DCC firmware
+for the CoreTile Express A15x2 A7x3 (V2P-CA15-A7) processor
+board.
+
+The updates are mandatory to be able to use the unified power
+management support for the big.LITTLE MP & CPU migration mode
+of operation in the Linaro Linux kernel. These changes will be
+introduced in version 13.01 of the kernel.
+
+The patch contains the following files:
+
+bm_v519r.axf - Boot Monitor
+dbb_v110.ebf - DCC firmware
+readme.txt - the text file you are reading now
+
+------------
+DCC Firmware
+------------
+
+This release of the DCC firmware is not compatible with pre-13.01
+kernels (i.e. existing releases of the Linaro Linux kernel).
+However, the previous version of the DCC firmware (dbb_v107.ebf)
+and pre-13.01 releases of the kernel may be used with this release
+of the Boot Monitor as mentioned below.
+
+------------
+Boot Monitor
+------------
+
+1. Compatibility with Linaro Linux kernel releases.
+
+ Power management support for the TC2 coretile has been reworked for the
+ 13.01 kernel release. Broadly, this means that per-cpu mailbox registers
+ are used to a) bringup secondary cpus during smp bringup & b) implement
+ warm resets. Linux kernel releases prior to 13.01 used the sys_flags
+ registers (part of the versatile express motherboard memory map) to do
+ the same.
+
+ The Bootmon firmware is compatible with both 13.01 and the releases
+ preceding it. Comptability with pre 13.01 Linaro Linux kernels is
+ referred to as 'backward compatibility'. The mode of operation of
+ bootmon can be configured by manipulating bit[12] in the SCC register
+ offset 0x700 (SCC System Information Register) in the board.txt file.
+
+ a. bit[12]=1: Bootmon is compatible with the 13.01 release of the
+ Linaro linux kernel. It uses per-cpu mailboxes to
+ implement warm resets & for secondary cpu bringup.
+
+ b. bit[12]=0: Bootmon is compatible with pre 13.01 releases of the
+ Linaro linux kernel. It uses sys_flags register to
+ implement warm resets for secondary cpu bringup.
+
+ This bit should be set to 0 if power management support
+ has been disabled in the Linux kernel configuration.
+
+ To summarize, the following combinations of the firmware and the
+ linux kernel are expected to be compatible:
+
+ a. dbb_v107.ebf (dcc fw) + bm_v519r.axf (bootmon fw) + pre-13.01
+ release of the Linaro linux kernel + board.txt which has bit[12]
+ of SCC register offset 0x700 unset.
+
+ b. dbb_v110.ebf (dcc fw) + bm_v519r.axf (bootmon fw) + 13.01 release
+ of the Linaro linux kernel + board.txt which has bit[12] of SCC
+ register offset 0x700 set.
+
+2. Support for TC2 coretile event propagation errata
+
+ The TC2 coretile has a bug in the implementation of the logic
+ that's responsible for delivering events (e.g. generated by the
+ 'sev' instruction) across the A15 and A7 clusters. Inter-cluster
+ events can be lost if the two clusters are operating at certain
+ OPP (operating point) combinations. This can cause a CPU to wait
+ for an event ('wfe' instruction) indefinitely e.g. while trying to
+ acquire a spin lock in the linux kernel.
+
+ Bootmon can be configured to work around this issue. This is done
+ by generating a periodic event stream (every 32K cycles) on each CPU
+ to make up for any lost events. Configuration is done by manipulating
+ the following bits of the SCC register offset 0x700 (SCC System
+ information register) in the board.txt as follows:
+
+ a. bit[14]=1: Each A15 cpu generates an event stream every 32K cycles.
+
+ b. bit[14]=0: Event stream generation is not configured on the A15 cpus.
+
+ c. bit[15]=1: Each A7 cpu generates an event stream every 32K cycles.
+
+ f. bit[15]=0: Event stream generation is not configured on the A7 cpus.
+
+ Setting both the bits in the SCC register is expected to provide a reliable
+ workaround of the errata.
+
+3. Support for powering down the non-boot cluster.
+
+ To save power it might be desirable to keep the non-boot cluster powered
+ down till the operating system (Linux) does not explicitly bringup cpus
+ in that cluster either as a part of smp bringup or through a hotplug request.
+
+ Bootmon can be configured to power down the non-boot cluster by manipulating
+ the SCC register offset 0x700 (SCC System information register) in the
+ board.txt as follows:
+
+ a. bit[13]=1: Bootmon powers down the non-boot cluster.
+
+ b. bit[13]=0: Bootmon does not power down the non-boot cluster.
+
+
+------------
+Installation
+------------
+
+There is no automatic installation method for this patch.
+To install the patch you must manually copy the files on
+to the Micro-SD card of your Versatile Express motherboard,
+and then update the relevant image.txt and board.txt files
+so that they point to the updated firmware and Boot Monitor.
+
+Proceed as follows:
+
+1) copy bm_v519r.axf to the motherboard in this location:
+
+ \SOFTWARE\bm_v519r.axf
+
+
+2) copy dbb_v110.ebf to the motherboard in this location:
+
+ \SITE1\HBI0249A\dbb_v110.ebf
+
+
+3) edit the file on the motherboard:
+
+ \SITE1\HBI0249A\board.txt
+
+ to change the line:
+
+ M0FILE: dbb_v107.ebf ;DCC0 Filename
+
+ so that it becomes:
+
+ M0FILE: dbb_v110.ebf ;DCC0 Filename
+
+
+4) edit the file on the motherboard:
+
+ \SITE1\HBI0249A\images.txt
+
+ to change the line:
+
+ NOR0FILE: \SOFTWARE\bm_v517r.axf ;Image File Name
+
+ so that it becomes:
+
+ NOR0FILE: \SOFTWARE\bm_v519r.axf ;Image File Name
+
+
+It is possible that additional changes to these text
+files will be needed - please see the instructions that
+come with the Linaro kernel for details of any further
+changes that are necessary.