summaryrefslogtreecommitdiff
path: root/SITE2/HBI0247B/AN307/a307r0p0.txt
diff options
context:
space:
mode:
authorRyan Harkin <ryan.harkin@linaro.org>2013-06-14 13:50:38 +0100
committerRyan Harkin <ryan.harkin@linaro.org>2013-06-14 13:50:38 +0100
commitaa495330fac68d9e2220510cc25040ab92500f6d (patch)
tree24ac3b8c02458d09983e3ab32a23b12ed367063a /SITE2/HBI0247B/AN307/a307r0p0.txt
parent75bef16f29442eda1f3de3e268fd17f992d253a0 (diff)
parent4b09e17342c99b7bf8f9f3dbe3abf362c3008de8 (diff)
downloadvexpress-firmware-aa495330fac68d9e2220510cc25040ab92500f6d.tar.gz
Merge branch 'arm-releases'
Diffstat (limited to 'SITE2/HBI0247B/AN307/a307r0p0.txt')
-rw-r--r--SITE2/HBI0247B/AN307/a307r0p0.txt27
1 files changed, 27 insertions, 0 deletions
diff --git a/SITE2/HBI0247B/AN307/a307r0p0.txt b/SITE2/HBI0247B/AN307/a307r0p0.txt
new file mode 100644
index 0000000..356838e
--- /dev/null
+++ b/SITE2/HBI0247B/AN307/a307r0p0.txt
@@ -0,0 +1,27 @@
+BOARD: HBI0247
+TITLE: AN307
+
+[FPGAS]
+TOTALFPGAS: 1 ;Total Number of FPGAS (Max:8)
+F0FILE: a307r0p0.bit ;FPGA0 Filename
+;F0MODE: FPGA_STREAM ;FPGA0 Programming Mode
+F0MODE: FPGA ;FPGA0 Programming Mode
+
+[VOLTAGES]
+TOTALVOLTAGES: 1 ;Total Number of VOLTAGES to set (Max:4)
+VOLT0: 1.8 ;VIO_UP maximum voltage (0.8 to 2.5)
+
+[OSCCLKS]
+TOTALOSCCLKS: 7 ;Total Number of OSCCLKS (Max:8)
+OSC0: 80.0 ;OSC0 Frequency in MHz (ACLK, MCLK, MCLK_90)
+OSC1: 23.75 ;OSC1 Frequency in MHz (CLCD)
+OSC2: 24.0 ;OSC2 Frequency in MHz (for 1Hz clk)
+OSC3: 30.0 ;OSC3 Frequency in MHz (ExtS ACLK)
+OSC4: 50.0 ;OSC4 Frequency in MHz (SMB)
+OSC5: 70.0 ;OSC5 Frequency in MHz (Not used)
+OSC6: 100.0 ;OSC6 Frequency in MHz (DDR) must be 100.0 or 200.0
+
+[SCC REGISTERS]
+TOTALSCCS: 2 ;Total Number of SCC registers defined
+SCC: 0x000 0x01234567 ;SCC gereral read/write regsiter address/value
+SCC: 0x004 0x89ABCDEF ;SCC gereral read/write register address/value