diff options
| author | Ryan Harkin <ryan.harkin@linaro.org> | 2013-06-14 13:41:50 +0100 |
|---|---|---|
| committer | Ryan Harkin <ryan.harkin@linaro.org> | 2013-06-14 13:50:47 +0100 |
| commit | 5f1cbf99eee5cca9535bdd869bcff1d7eac93afe (patch) | |
| tree | f08ed0b5ce8dfe46cd72982766a0aab30e61989c /SITE1 | |
| parent | bcf2914ff036a2505f41cd0014340cf8feff5c5a (diff) | |
Linaro Firmware for 13.02 release
These files were used in the Linaro Firmware overlay for the 13.02
release:
https://wiki.linaro.org/ARM/VersatileExpress?action=AttachFile&do=get&target=vemsd-armlt-20130225-001.zip
The release can be found here:
http://releases.linaro.org/13.02/ubuntu/vexpress/
http://releases.linaro.org/13.02/android/vexpress/
The changes will configure u-boot on A5 and TC1, UEFI on A9 and Boot
Monitor on TC2.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Diffstat (limited to 'SITE1')
| -rw-r--r-- | SITE1/HBI0249A/board.txt | 13 | ||||
| -rw-r--r-- | SITE1/HBI0249A/images.txt | 20 |
2 files changed, 31 insertions, 2 deletions
diff --git a/SITE1/HBI0249A/board.txt b/SITE1/HBI0249A/board.txt index 3a0f7ee..baa7dca 100644 --- a/SITE1/HBI0249A/board.txt +++ b/SITE1/HBI0249A/board.txt @@ -34,7 +34,8 @@ OSC7: 50.0 ;SYSREFCLK (20:1 - 1.0GHz, ACLK - 500MHz) OSC8: 50.0 ;DDR2 (8:1 - 400MHz)
[SCC REGISTERS]
-TOTALSCCS: 31 ;Total Number of SCC registers
+TOTALSCCS: 32 ;Total Number of SCC registers
+
SCC: 0x01C 0xFF00FF00 ;CFGRW3 - SMC CS6/7 N/U
SCC: 0x118 0x01CD1011 ;CFGRW17 - HDLCD PLL external bypass
;SCC: 0x700 0x00320003 ;CFGRW48 - [25:24]Boot CPU [28]Boot Cluster (default CA7_0)
@@ -46,6 +47,16 @@ SCC: 0x700 0x0032F003 ;CFGRW48 - [25:24]Boot CPU [28]Boot Cluster (def ; [12]: Use per-cpu mailboxes for power management (default: disabled)
; [11]: A15 executes WFEs as nops (default: disabled)
+SCC: 0x400 0x33330c00 ;CFGREG41 - A15 configuration register 0 (Default 0x33330c80)
+ ; [29:28] SPNIDEN
+ ; [25:24] SPIDEN
+ ; [21:20] NIDEN
+ ; [17:16] DBGEN
+ ; [13:12] CFGTE
+ ; [9:8] VINITHI_CORE
+ ; [7] IMINLN
+ ; [3:0] CLUSTER_ID
+
;Set the CPU clock PLLs
SCC: 0x120 0x022F1010 ;CFGRW19 - CA15_0 PLL control - 20:1 (lock OFF)
SCC: 0x124 0x0011710D ;CFGRW20 - CA15_0 PLL value
diff --git a/SITE1/HBI0249A/images.txt b/SITE1/HBI0249A/images.txt index 8b83d26..42e318f 100644 --- a/SITE1/HBI0249A/images.txt +++ b/SITE1/HBI0249A/images.txt @@ -1,7 +1,7 @@ TITLE: Versatile Express Images Configuration File
[IMAGES]
-TOTALIMAGES: 3 ;Number of Images (Max : 32)
+TOTALIMAGES: 6 ;Number of Images (Max : 32)
NOR0UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
NOR0ADDRESS: BOOT ;Image Flash Address
NOR0FILE: \SOFTWARE\bm_v519r.axf ;Image File Name
@@ -17,3 +17,21 @@ NOR2FILE: \SOFTWARE\TC2\uefi.bin ;Image File Name NOR2LOAD: 81000000 ;Image Load Address
NOR2ENTRY: 81000000 ;Image Entry Point
+NOR3UPDATE: AUTO ;IMAGE UPDATE:NONE/AUTO/FORCE
+NOR3ADDRESS: 03000000 ;Image Flash Address
+NOR3FILE: \SOFTWARE\TC2\zimage.bin ;Image File Name - master kernel
+NOR3LOAD: 80008000 ;Image Load Address
+NOR3ENTRY: 80008000 ;Image Entry Point
+
+NOR4UPDATE: AUTO ;IMAGE UPDATE:NONE/AUTO/FORCE
+NOR4ADDRESS: 00600000 ;Image Flash Address
+NOR4FILE: \SOFTWARE\TC2\dtb.bin ;Image File Name - master DTB
+NOR4LOAD: a0000000 ;Image Load Address
+NOR4ENTRY: a0000000 ;Image Load Address
+
+NOR5UPDATE: AUTO ;IMAGE UPDATE:NONE/AUTO/FORCE
+NOR5ADDRESS: 0c000000 ;Image Flash Address
+NOR5FILE: \SOFTWARE\TC2\initrd.bin ;Image File Name - master initrd
+NOR5LOAD: a0100000 ;Image Load Address
+NOR5ENTRY: a0100000 ;Image Entry Point
+
|