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authorRyan Harkin <ryan.harkin@linaro.org>2015-12-02 13:52:37 +0000
committerRyan Harkin <ryan.harkin@linaro.org>2015-12-03 11:02:12 +0000
commit901f81977c3b367a2e0bf3d6444be302822d97a3 (patch)
tree0cea6daf47c240ebdc3f9b114c687978877112ef /SITE1
parent3d94686a710c27be9ecf1b4cb99b45db40650d3b (diff)
downloadvexpress-firmware-901f81977c3b367a2e0bf3d6444be302822d97a3.tar.gz
Add 15.12-rc2 firmware from ARM
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Diffstat (limited to 'SITE1')
-rwxr-xr-xSITE1/HBI0262D/board.txt24
-rwxr-xr-xSITE1/HBI0262D/images.txt56
2 files changed, 80 insertions, 0 deletions
diff --git a/SITE1/HBI0262D/board.txt b/SITE1/HBI0262D/board.txt
new file mode 100755
index 0000000..2654ed8
--- /dev/null
+++ b/SITE1/HBI0262D/board.txt
@@ -0,0 +1,24 @@
+BOARD: HBI0262
+TITLE: V2M-Juno DevChip Configuration File
+
+[SCC REGISTERS]
+TOTALSCCS: 13 ;Total Number of SCC registers
+SCC: 0x054 0x0007FFFE ;Enable non-secure DMA operations
+SCC: 0x05C 0x00FE001E ;Enable default GPU Texture Formats
+SCC: 0x100 0x00271000 ;A72 PLL Register 0 (1000MHz)
+SCC: 0x104 0x00013100 ;A72 PLL Register 1
+SCC: 0x108 0x003F1000 ;A53 PLL Register 0 (800MHz)
+SCC: 0x10C 0x0001F300 ;A53 PLL Register 1
+SCC: 0x118 0x003F1000 ;SYS PLL Register 0 (1600MHz)
+SCC: 0x11C 0x0001F100 ;SYS PLL Register 1
+SCC: 0x0F8 0x0BEC0000 ;BL1 entry point
+SCC: 0x0FC 0xABE40000 ;BL0 entry point
+
+SCC: 0xA14 0x00000000 ;PCLKDBG_CONTROL DIV=1
+
+SCC: 0x00C 0x000000C2 ;Clock Control, TMIF2XCLK, Register 0xC1 = default
+ ;[3:0] CLKSEL : 0 Output gated, 1 AON_REF_CLK, 2 SYSCLK
+ ;[7:4] CLKDIV : Clock divider -1 (0 give a division of 1)
+SCC: 0x010 0x000000C2 ;Clock Control, TSIF2XCLK, Register 0xC1 = default
+ ;[3:0] CLKSEL : 0 Output gated, 1 AON_REF_CLK, 2 SYSCLK
+ ;[7:4] CLKDIV : Clock divider -1 (0 give a division of 1)
diff --git a/SITE1/HBI0262D/images.txt b/SITE1/HBI0262D/images.txt
new file mode 100755
index 0000000..c00a35d
--- /dev/null
+++ b/SITE1/HBI0262D/images.txt
@@ -0,0 +1,56 @@
+TITLE: Versatile Express Images Configuration File
+
+[IMAGES]
+TOTALIMAGES: 8 ;Number of Images (Max: 32)
+
+NOR0UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
+NOR0ADDRESS: 0x00000000 ;Image Flash Address
+NOR0FILE: \SOFTWARE\fip.bin ;Image File Name
+NOR0LOAD: 00000000 ;Image Load Address
+NOR0ENTRY: 00000000 ;Image Entry Point
+
+NOR1UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
+NOR1ADDRESS: 0x03EC0000 ;Image Flash Address
+NOR1FILE: \SOFTWARE\bl1.bin ;Image File Name
+NOR1LOAD: 00000000 ;Image Load Address
+NOR1ENTRY: 00000000 ;Image Entry Point
+
+NOR2UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
+NOR2ADDRESS: 0x00500000 ;Image Flash Address
+NOR2FILE: \SOFTWARE\Image ;Image File Name
+NOR2NAME: norkern ;Rename kernel to norkern
+NOR2LOAD: 00000000 ;Image Load Address
+NOR2ENTRY: 00000000 ;Image Entry Point
+
+NOR3UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
+NOR3ADDRESS: 0x02000000 ;Image Flash Address
+NOR3FILE: \SOFTWARE\juno-r2.dtb ;Image File Name
+NOR3NAME: board.dtb ;Specify target filename to preserve file extension
+NOR3LOAD: 00000000 ;Image Load Address
+NOR3ENTRY: 00000000 ;Image Entry Point
+
+NOR4UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
+
+NOR4ADDRESS: 0x01800000 ;Image Flash Address
+NOR4FILE: \SOFTWARE\ramdisk.img ;Image File Name
+NOR4NAME: ramdisk.img
+NOR4LOAD: 00000000 ;Image Load Address
+NOR4ENTRY: 00000000 ;Image Entry Point
+
+NOR5UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
+NOR5ADDRESS: 0x025C0000 ;Image Flash Address
+NOR5FILE: \SOFTWARE\hdlcdclk.dat ;Image File Name
+NOR5LOAD: 00000000 ;Image Load Address
+NOR5ENTRY: 00000000 ;Image Entry Point
+
+NOR6UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
+NOR6ADDRESS: 0x03E40000 ;Image Flash Address
+NOR6FILE: \SOFTWARE\bl0.bin ;Image File Name
+NOR6LOAD: 00000000 ;Image Load Address
+NOR6ENTRY: 00000000 ;Image Entry Point
+
+NOR7UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
+NOR7ADDRESS: 0x0BFC0000 ;Image Flash Address
+NOR7FILE: \SOFTWARE\blank.img ;Image File Name
+NOR7LOAD: 00000000 ;Image Load Address
+NOR7ENTRY: 00000000 ;Image Entry Point