summaryrefslogtreecommitdiff
path: root/SITE1/HBI0262D/board.txt
diff options
context:
space:
mode:
authorRyan Harkin <ryan.harkin@linaro.org>2015-12-02 13:52:37 +0000
committerRyan Harkin <ryan.harkin@linaro.org>2015-12-03 11:02:12 +0000
commit901f81977c3b367a2e0bf3d6444be302822d97a3 (patch)
tree0cea6daf47c240ebdc3f9b114c687978877112ef /SITE1/HBI0262D/board.txt
parent3d94686a710c27be9ecf1b4cb99b45db40650d3b (diff)
downloadvexpress-firmware-901f81977c3b367a2e0bf3d6444be302822d97a3.tar.gz
Add 15.12-rc2 firmware from ARM
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Diffstat (limited to 'SITE1/HBI0262D/board.txt')
-rwxr-xr-xSITE1/HBI0262D/board.txt24
1 files changed, 24 insertions, 0 deletions
diff --git a/SITE1/HBI0262D/board.txt b/SITE1/HBI0262D/board.txt
new file mode 100755
index 0000000..2654ed8
--- /dev/null
+++ b/SITE1/HBI0262D/board.txt
@@ -0,0 +1,24 @@
+BOARD: HBI0262
+TITLE: V2M-Juno DevChip Configuration File
+
+[SCC REGISTERS]
+TOTALSCCS: 13 ;Total Number of SCC registers
+SCC: 0x054 0x0007FFFE ;Enable non-secure DMA operations
+SCC: 0x05C 0x00FE001E ;Enable default GPU Texture Formats
+SCC: 0x100 0x00271000 ;A72 PLL Register 0 (1000MHz)
+SCC: 0x104 0x00013100 ;A72 PLL Register 1
+SCC: 0x108 0x003F1000 ;A53 PLL Register 0 (800MHz)
+SCC: 0x10C 0x0001F300 ;A53 PLL Register 1
+SCC: 0x118 0x003F1000 ;SYS PLL Register 0 (1600MHz)
+SCC: 0x11C 0x0001F100 ;SYS PLL Register 1
+SCC: 0x0F8 0x0BEC0000 ;BL1 entry point
+SCC: 0x0FC 0xABE40000 ;BL0 entry point
+
+SCC: 0xA14 0x00000000 ;PCLKDBG_CONTROL DIV=1
+
+SCC: 0x00C 0x000000C2 ;Clock Control, TMIF2XCLK, Register 0xC1 = default
+ ;[3:0] CLKSEL : 0 Output gated, 1 AON_REF_CLK, 2 SYSCLK
+ ;[7:4] CLKDIV : Clock divider -1 (0 give a division of 1)
+SCC: 0x010 0x000000C2 ;Clock Control, TSIF2XCLK, Register 0xC1 = default
+ ;[3:0] CLKSEL : 0 Output gated, 1 AON_REF_CLK, 2 SYSCLK
+ ;[7:4] CLKDIV : Clock divider -1 (0 give a division of 1)