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authorRyan Harkin <ryan.harkin@linaro.org>2015-05-11 16:55:40 +0100
committerRyan Harkin <ryan.harkin@linaro.org>2015-05-11 16:55:40 +0100
commit4b23b99bbd41c69a11b0f5eca210694ab17c99fc (patch)
treef9ccd920d96f624b03357faf50579b9d5ebdf0a6 /SITE1/HBI0262C/board.txt
parentfe8058e2f462dc0a5cc98995d39428af50a69ce2 (diff)
downloadvexpress-firmware-4b23b99bbd41c69a11b0f5eca210694ab17c99fc.tar.gz
add board_recovery_image_0.11.3.zipjuno-0.11.3
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
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+BOARD: HBI0262
+TITLE: V2M-Juno DevChip Configuration File
+
+[SCC REGISTERS]
+TOTALSCCS: 14 ;Total Number of SCC registers
+SCC: 0x054 0x0007FFFE ;Enable non-secure DMA operations
+SCC: 0x05C 0x00FE001E ;Enable default GPU Texture Formats
+SCC: 0x100 0x003F1000 ;A57 PLL Register 0 (800MHz)
+SCC: 0x104 0x0001F300 ;A57 PLL Register 1
+SCC: 0x108 0x00331000 ;A53 PLL Register 0 (650MHz)
+SCC: 0x10C 0x00019300 ;A53 PLL Register 1
+SCC: 0x118 0x003F1000 ;SYS PLL Register 0 (1600MHz)
+SCC: 0x11C 0x0001F100 ;SYS PLL Register 1
+SCC: 0x0F4 0x00004108 ;Primary CPU: A57-0
+SCC: 0x0F8 0x0BEC0000 ;BL1 entry point
+SCC: 0x0FC 0xABE40000 ;BL0 entry point
+
+SCC: 0xA14 0x00000000 ;PCLKDBG_CONTROL DIV=1
+
+SCC: 0x00C 0x000000C2 ;Clock Control, TMIF2XCLK, Register 0xC1 = default
+ ;[3:0] CLKSEL : 0 Output gated, 1 AON_REF_CLK, 2 SYSCLK
+ ;[7:4] CLKDIV : Clock divider -1 (0 give a division of 1)
+SCC: 0x010 0x000000C2 ;Clock Control, TSIF2XCLK, Register 0xC1 = default
+ ;[3:0] CLKSEL : 0 Output gated, 1 AON_REF_CLK, 2 SYSCLK
+ ;[7:4] CLKDIV : Clock divider -1 (0 give a division of 1)