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authorRyan Harkin <ryan.harkin@linaro.org>2014-06-20 15:15:28 +0100
committerRyan Harkin <ryan.harkin@linaro.org>2014-06-20 15:19:59 +0100
commite728202430ee6f1f933d4e269d3490d9ccc9142f (patch)
treea194cee7d646e635a95dd4f485edc1ea291a8189 /SITE1/HBI0262B/board.txt
parentf243582e864d9b864f76052869502a3fe205e55a (diff)
downloadvexpress-firmware-e728202430ee6f1f933d4e269d3490d9ccc9142f.tar.gz
remove previous firmware image
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Diffstat (limited to 'SITE1/HBI0262B/board.txt')
-rw-r--r--SITE1/HBI0262B/board.txt18
1 files changed, 0 insertions, 18 deletions
diff --git a/SITE1/HBI0262B/board.txt b/SITE1/HBI0262B/board.txt
deleted file mode 100644
index 6ff12ca..0000000
--- a/SITE1/HBI0262B/board.txt
+++ /dev/null
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-BOARD: HBI0262
-TITLE: V2M-Juno DevChip Configuration File
-
-[SCC REGISTERS]
-TOTALSCCS: 8 ;Total Number of SCC registers
-SCC: 0x05C 0xFFFFFFFF ;Enable all GPU Texture Formats
-SCC: 0x100 0x801F1000 ;A57 PLL Register 0 (800MHz)
-SCC: 0x104 0x0000F100 ;A57 PLL Register 1
-SCC: 0x108 0x801B1000 ;A53 PLL Register 0 (700MHz)
-SCC: 0x10C 0x0000D100 ;A53 PLL Register 1
-SCC: 0x0F8 0x0BEC0000 ;BL1 entry point
-
-SCC: 0x00C 0x000000C2 ;Clock Control, TMIF2XCLK, Register 0xC1 = default
- ;[3:0] CLKSEL : 0 Output gated, 1 AON_REF_CLK, 2 SYSCLK
- ;[7:4] CLKDIV : Clock divider -1 (0 give a division of 1)
-SCC: 0x010 0x000000C2 ;Clock Control, TSIF2XCLK, Register 0xC1 = default
- ;[3:0] CLKSEL : 0 Output gated, 1 AON_REF_CLK, 2 SYSCLK
- ;[7:4] CLKDIV : Clock divider -1 (0 give a division of 1)