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authorRyan Harkin <ryan.harkin@linaro.org>2014-06-20 15:05:27 +0100
committerRyan Harkin <ryan.harkin@linaro.org>2014-06-20 15:19:31 +0100
commitbc88b1dba90d0a5de8178582aeb67cf17291fb91 (patch)
tree1e48572cab1f318b67b07e538f64c92e9ea9d08e /SITE1/HBI0262B/board.txt
parent680d3bdfe9d6791bc946419833053bcc37a67537 (diff)
downloadvexpress-firmware-bc88b1dba90d0a5de8178582aeb67cf17291fb91.tar.gz
add board_recovery_image_0.5
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
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+BOARD: HBI0262
+TITLE: V2M-Juno DevChip Configuration File
+
+[SCC REGISTERS]
+TOTALSCCS: 7 ;Total Number of SCC registers
+SCC: 0x100 0x801F1000 ;A57 PLL Register 0 (800MHz)
+SCC: 0x104 0x0000F100 ;A57 PLL Register 1
+SCC: 0x108 0x801B1000 ;A53 PLL Register 0 (700MHz)
+SCC: 0x10C 0x0000D100 ;A53 PLL Register 1
+SCC: 0x0F8 0x0BEC0000 ;BL1 entry point
+
+SCC: 0x00C 0x000000C2 ;Clock Control, TMIF2XCLK, Register 0xC1 = default
+ ;[3:0] CLKSEL : 0 Output gated, 1 AON_REF_CLK, 2 SYSCLK
+ ;[7:4] CLKDIV : Clock divider -1 (0 give a division of 1)
+SCC: 0x010 0x000000C2 ;Clock Control, TSIF2XCLK, Register 0xC1 = default
+ ;[3:0] CLKSEL : 0 Output gated, 1 AON_REF_CLK, 2 SYSCLK
+ ;[7:4] CLKDIV : Clock divider -1 (0 give a division of 1)