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authorRyan Harkin <ryan.harkin@linaro.org>2014-12-11 11:15:58 +0000
committerRyan Harkin <ryan.harkin@linaro.org>2014-12-11 13:34:26 +0000
commit8c06a7fa70b7cacc1911876f465293e61f625ddc (patch)
treee1b9f9e5b7160bfe5abcefcc587d041c530a3afa /SITE1/HBI0262B/board.txt
parenta16a3fca33af877de444cdceab48ffa7fefa80f8 (diff)
downloadvexpress-firmware-8c06a7fa70b7cacc1911876f465293e61f625ddc.tar.gz
remove previous firmware image
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Diffstat (limited to 'SITE1/HBI0262B/board.txt')
-rwxr-xr-xSITE1/HBI0262B/board.txt21
1 files changed, 0 insertions, 21 deletions
diff --git a/SITE1/HBI0262B/board.txt b/SITE1/HBI0262B/board.txt
deleted file mode 100755
index 099680d..0000000
--- a/SITE1/HBI0262B/board.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-BOARD: HBI0262
-TITLE: V2M-Juno DevChip Configuration File
-
-[SCC REGISTERS]
-TOTALSCCS: 11 ;Total Number of SCC registers
-SCC: 0x054 0x0007FFFE ;Enable non-secure DMA operations
-SCC: 0x05C 0x00FE001E ;Enable default GPU Texture Formats
-SCC: 0x100 0x003F1000 ;A57 PLL Register 0 (800MHz)
-SCC: 0x104 0x0001F300 ;A57 PLL Register 1
-SCC: 0x108 0x00371000 ;A53 PLL Register 0 (700MHz)
-SCC: 0x10C 0x0001B300 ;A53 PLL Register 1
-SCC: 0x118 0x003F1000 ;SYS PLL Register 0 (1600MHz)
-SCC: 0x11C 0x0001F100 ;SYS PLL Register 1
-SCC: 0x0F8 0x0BEC0000 ;BL1 entry point
-
-SCC: 0x00C 0x000000C2 ;Clock Control, TMIF2XCLK, Register 0xC1 = default
- ;[3:0] CLKSEL : 0 Output gated, 1 AON_REF_CLK, 2 SYSCLK
- ;[7:4] CLKDIV : Clock divider -1 (0 give a division of 1)
-SCC: 0x010 0x000000C2 ;Clock Control, TSIF2XCLK, Register 0xC1 = default
- ;[3:0] CLKSEL : 0 Output gated, 1 AON_REF_CLK, 2 SYSCLK
- ;[7:4] CLKDIV : Clock divider -1 (0 give a division of 1)