diff options
author | Ryan Harkin <ryan.harkin@linaro.org> | 2014-06-20 15:04:17 +0100 |
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committer | Ryan Harkin <ryan.harkin@linaro.org> | 2014-06-20 15:19:31 +0100 |
commit | 680d3bdfe9d6791bc946419833053bcc37a67537 (patch) | |
tree | a194cee7d646e635a95dd4f485edc1ea291a8189 /SITE1/HBI0262B/board.txt | |
parent | 31964d3856e3429b1bee9322389ebba741ccf1c7 (diff) |
remove previous firmware image
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Diffstat (limited to 'SITE1/HBI0262B/board.txt')
-rw-r--r-- | SITE1/HBI0262B/board.txt | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/SITE1/HBI0262B/board.txt b/SITE1/HBI0262B/board.txt deleted file mode 100644 index 0269b4c..0000000 --- a/SITE1/HBI0262B/board.txt +++ /dev/null @@ -1,17 +0,0 @@ -BOARD: HBI0262
-TITLE: V2M-Juno DevChip Configuration File
-
-[SCC REGISTERS]
-TOTALSCCS: 7 ;Total Number of SCC registers
-SCC: 0x100 0x801F1000 ;A57 PLL Register 0 (800MHz)
-SCC: 0x104 0x0000F100 ;A57 PLL Register 1
-SCC: 0x108 0x801B1000 ;A53 PLL Register 0 (700MHz)
-SCC: 0x10C 0x0000D100 ;A53 PLL Register 1
-SCC: 0x0F8 0x0BEC0000 ;BL1 entry point
-
-SCC: 0x00C 0x000000C2 ;Clock Control, TMIF2XCLK, Register 0xC1 = default
- ;[3:0] CLKSEL : 0 Output gated, 1 AON_REF_CLK, 2 SYSCLK
- ;[7:4] CLKDIV : Clock divider -1 (0 give a division of 1)
-SCC: 0x010 0x000000C2 ;Clock Control, TSIF2XCLK, Register 0xC1 = default
- ;[3:0] CLKSEL : 0 Output gated, 1 AON_REF_CLK, 2 SYSCLK
- ;[7:4] CLKDIV : Clock divider -1 (0 give a division of 1)
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