diff options
| author | Ryan Harkin <ryan.harkin@linaro.org> | 2013-12-09 10:25:11 +0100 |
|---|---|---|
| committer | Ryan Harkin <ryan.harkin@linaro.org> | 2013-12-10 10:40:43 +0000 |
| commit | ef0269a7f50eff9821b7b5034caea680b6aff062 (patch) | |
| tree | 83a988746812a05ca7f749811c65aa44b2891e98 /SITE1/HBI0249A | |
| parent | 4b09e17342c99b7bf8f9f3dbe3abf362c3008de8 (diff) | |
Versatile Express 5.2
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Diffstat (limited to 'SITE1/HBI0249A')
| -rw-r--r-- | SITE1/HBI0249A/board.txt | 28 | ||||
| -rw-r--r-- | SITE1/HBI0249A/images.txt | 2 |
2 files changed, 22 insertions, 8 deletions
diff --git a/SITE1/HBI0249A/board.txt b/SITE1/HBI0249A/board.txt index 48e17f2..715691c 100644 --- a/SITE1/HBI0249A/board.txt +++ b/SITE1/HBI0249A/board.txt @@ -35,13 +35,27 @@ OSC8: 50.0 ;DDR2 (8:1 - 400MHz) [SCC REGISTERS]
TOTALSCCS: 32 ;Total Number of SCC registers
-SCC: 0x018 0x1FFFFFFF ;Reset control (CA7s running, CA15s running) - uncomment this for normal operation
-;SCC: 0x018 0x1FFFF000 ;Reset control - (CA7s running, CA15s reset) - uncomment this to hold A15 cluster in reset
-;SCC: 0x018 0x00001FFF ;Reset control - (CA7s reset, CA15s running) - uncomment this to hold A7 cluster in reset
SCC: 0x01C 0xFF00FF00 ;CFGRW3 - SMC CS6/7 N/U
SCC: 0x118 0x01CD1011 ;CFGRW17 - HDLCD PLL external bypass
-SCC: 0x700 0x00320003 ;CFGRW48 - Boot cluster and CPU (CA15[0]) - uncomment this to boot on A15 cluster
-;SCC: 0x700 0x10320003 ;CFGRW48 - Boot cluster and CPU (CA7[0]) - uncomment this to boot on A7 cluster
+ +SCC: 0x700 0x0032F003 ;CFGRW48 - Cluster configuration register (Default 0x0032F003) + ; [ 28] Boot Cluster (default CA15) + ; [25:24] Boot CPU (default 0) + ; [ 15] A7 Event stream generation (default: enabled) + ; [ 14] A15 Event stream generation (default: enabled) + ; [ 13] Power down the non-boot cluster (default: enabled) + ; [ 12] Use per-cpu mailboxes for power management (default: enabled) + ; [ 11] A15 executes WFEs as nops (default: disabled) + +SCC: 0x400 0x33330C00 ;CFGRW41 - A15 configuration register 0 (Default 0x33330C00) + ; [29:28] SPNIDEN + ; [25:24] SPIDEN + ; [21:20] NIDEN + ; [17:16] DBGEN + ; [13:12] CFGTE + ; [ 9: 8] VINITHI_CORE + ; [ 7] IMINLN + ; [ 3: 0] CLUSTER_ID ;Set the CPU clock PLLs
SCC: 0x120 0x022F1010 ;CFGRW19 - CA15_0 PLL control - 20:1 (lock OFF)
@@ -54,8 +68,8 @@ SCC: 0x138 0x022F1010 ;CFGRW25 - CA7_1 PLL control - 20:1 (lock OFF) SCC: 0x13C 0x0011710D ;CFGRW26 - CA7_1 PLL value
;Power management interface
-SCC: 0xC00 0x00000003 ;Control (enable power management)
-SCC: 0xC04 0x000005DC ;Latency in uS
+SCC: 0xC00 0x00000007 ;Control: [0]PMI_EN [1]DBG_EN [2]SPC_SYSCFG (disable DBG_EN for power measurements) +SCC: 0xC04 0x060E0356 ;Latency in uS max: [15:0]DVFS [31:16]PWRUP SCC: 0xC08 0x00000000 ;Reserved
SCC: 0xC0C 0x00000000 ;Reserved
diff --git a/SITE1/HBI0249A/images.txt b/SITE1/HBI0249A/images.txt index d03cf9f..a640ffc 100644 --- a/SITE1/HBI0249A/images.txt +++ b/SITE1/HBI0249A/images.txt @@ -5,7 +5,7 @@ TOTALIMAGES: 4 ;Number of Images (Max: 32) NOR0UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
NOR0ADDRESS: BOOT ;Image Flash Address
-NOR0FILE: \SOFTWARE\bm_v519r.axf ;Image File Name
+NOR0FILE: \SOFTWARE\bm_v521r.axf ;Image File Name NOR1UPDATE: AUTO ;IMAGE UPDATE:NONE/AUTO/FORCE
NOR1ADDRESS: 00000000 ;Image Flash Address
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