diff options
| author | Ryan Harkin <ryan.harkin@linaro.org> | 2013-06-14 13:50:38 +0100 |
|---|---|---|
| committer | Ryan Harkin <ryan.harkin@linaro.org> | 2013-06-14 13:50:38 +0100 |
| commit | aa495330fac68d9e2220510cc25040ab92500f6d (patch) | |
| tree | 24ac3b8c02458d09983e3ab32a23b12ed367063a /SITE1/HBI0237A/board.txt | |
| parent | 75bef16f29442eda1f3de3e268fd17f992d253a0 (diff) | |
| parent | 4b09e17342c99b7bf8f9f3dbe3abf362c3008de8 (diff) | |
Merge branch 'arm-releases'
Diffstat (limited to 'SITE1/HBI0237A/board.txt')
| -rw-r--r-- | SITE1/HBI0237A/board.txt | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/SITE1/HBI0237A/board.txt b/SITE1/HBI0237A/board.txt index a805b6f..5d17f8d 100644 --- a/SITE1/HBI0237A/board.txt +++ b/SITE1/HBI0237A/board.txt @@ -3,7 +3,7 @@ TITLE: V2P-CA15 Configuration File [DCCS]
TOTALDCCS: 1 ;Total Number of DCCS
-M0FILE: dbb_v102.ebf ;DCC0 Filename
+M0FILE: dbb_v107.ebf ;DCC0 Filename
M0MODE: MICRO ;DCC0 Programming Mode
[FPGAS]
@@ -23,17 +23,18 @@ T2MODE: NONE ;TAP2 Programming Mode [OSCCLKS]
TOTALOSCCLKS: 9 ;Total Number of OSCCLKS
-OSC0: 60.0 ;CPUREFCLK0 A15 CPU (20:1 - 1.2GHz)
+OSC0: 24.0 ;CPUREFCLK0 A15 CPU (20:1 not used in CPU/AXI sync mode)
OSC1: 24.0 ;N/U
OSC2: 24.0 ;N/U
OSC3: 24.0 ;N/U
OSC4: 40.0 ;HSBM AXI (40MHz)
OSC5: 63.5 ;HDLCD (63.5MHz - TC PLL is in bypass)
OSC6: 50.0 ;SMB (50MHz)
-OSC7: 60.0 ;SYSREFCLK (20:1 - 1.2GHz, ACLK - 600MHz)
-OSC8: 40.0 ;DDR2 (8:1 - 320MHz)
+OSC7: 60.0 ;SYSREFCLK (20:1 - 1.2GHz CPU, /2 - 600MHz AXI - sync mode)
+OSC8: 50.0 ;DDR2 (8:1 - 400MHz - async mode)
[SCC REGISTERS]
-TOTALSCCS: 2 ;Total Number of SCC registers
+TOTALSCCS: 3 ;Total Number of SCC registers
SCC: 0x01C 0xFF00FF00 ;CFGRW5 - SMC CS6/7 N/U
+SCC: 0x19C 0xFF201930 ;CFGRW9 - CPU/AXI 2:1 sync mode, DDR async mode
SCC: 0x1B0 0x01CD1011 ;CFGRW14 - HDLCD PLL external bypass
|