diff options
| author | Ryan Harkin <ryan.harkin@linaro.org> | 2017-04-25 11:07:01 +0100 |
|---|---|---|
| committer | Ryan Harkin <ryan.harkin@linaro.org> | 2017-04-25 11:09:28 +0100 |
| commit | ba39c397458f0c07f5f643cad94f4ddc035c4042 (patch) | |
| tree | c8b97750921b9f937e967f2d96f696e897042f3f | |
| parent | 838e33ce471070b02e3d6731233002eaaa78cdfa (diff) | |
Boot Juno R1 from A53 core
Register F4 was set to trigger Juno R1 to boot from the big (A57) core.
Removing the register setting will mean the board will boot from the
little (A53) core by default.
R0 and R2 already boot from the little cores.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
| -rw-r--r-- | SITE1/HBI0262C/board.txt | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/SITE1/HBI0262C/board.txt b/SITE1/HBI0262C/board.txt index 525aa6c..3c23e65 100644 --- a/SITE1/HBI0262C/board.txt +++ b/SITE1/HBI0262C/board.txt @@ -2,7 +2,7 @@ BOARD: HBI0262 TITLE: V2M-Juno DevChip Configuration File
[SCC REGISTERS]
-TOTALSCCS: 14 ;Total Number of SCC registers
+TOTALSCCS: 13 ;Total Number of SCC registers
SCC: 0x054 0x0007FFFE ;Enable non-secure DMA operations
SCC: 0x05C 0x00FE001E ;Enable default GPU Texture Formats
SCC: 0x100 0x003F1000 ;A57 PLL Register 0 (800MHz)
@@ -11,7 +11,6 @@ SCC: 0x108 0x00331000 ;A53 PLL Register 0 (650MHz) SCC: 0x10C 0x00019300 ;A53 PLL Register 1
SCC: 0x118 0x003F1000 ;SYS PLL Register 0 (1600MHz)
SCC: 0x11C 0x0001F100 ;SYS PLL Register 1
-SCC: 0x0F4 0x00004108 ;Primary CPU: A57-0
SCC: 0x0F8 0x0BEC0000 ;BL1 entry point
SCC: 0x0FC 0xABE40000 ;BL0 entry point
|