diff options
| author | Ryan Harkin <ryan.harkin@linaro.org> | 2015-10-22 16:17:56 +0100 |
|---|---|---|
| committer | Ryan Harkin <ryan.harkin@linaro.org> | 2015-10-22 17:21:28 +0100 |
| commit | 9f5f9c68718c0100d781762c0c865622f6994fa8 (patch) | |
| tree | 518a516d1ae2e5fb9e143f80d4a9e46a0f79f736 | |
| parent | 63f282241ea0f778007a91a74462191fedbaf78b (diff) | |
Revert NOR bank flipping so we boot bootmon and u-boota9-uboot-000
The high bit of SCC 4 is used to flip the two NOR flash banks.
0 == normal
1 == flipped
By placing UEFI in the 2nd NOR bank and the files needed for u-boot in
the 1st bank, we can use board.txt to flip between booting u-boot or
UEFI.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
| -rw-r--r-- | SITE1/HBI0191B/board.txt | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/SITE1/HBI0191B/board.txt b/SITE1/HBI0191B/board.txt index f58c355..10a9770 100644 --- a/SITE1/HBI0191B/board.txt +++ b/SITE1/HBI0191B/board.txt @@ -43,7 +43,7 @@ OSC2: 66.67 ;OSC2 Frequency in MHz (TCREFCLK) [SCC REGISTERS]
TOTALSCCS: 3 ;Total Number of SCC registers defined
SCC: 0x000 0xBB8A802A ;CFGRW0 Power up settings - MCLK, AXICLKs, FCLK PLL configuration
-SCC: 0x004 0x10001F09 ;CFGRW1 Power up settings - Remap bits, A9 static signals, MCLK PLL
+SCC: 0x004 0x00001F09 ;CFGRW1 Power up settings - Remap bits, A9 static signals, MCLK PLL
SCC: 0x008 0x00000000 ;CFGRW2 Power up settings - Misc, A9 static signals
|