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authorLeif Lindholm <leif.lindholm@linaro.org>2014-05-22 12:19:33 +0100
committerLeif Lindholm <leif.lindholm@linaro.org>2014-05-22 12:19:33 +0100
commit7ae0e252b114b6f07ab772f8cbd8fa25e588ab2b (patch)
treeaf55f51d89b6e50fa2e15d61d5a23e4ec54b2992
parenta50bf4634f25834e3a99078eba7dec8fa7e10418 (diff)
HiSilicon D01 platform cleanups
Diffstat
-rw-r--r--HisiPkg/D01BoardPkg/Bds/Bds.c47
-rw-r--r--HisiPkg/D01BoardPkg/Bds/Bds.inf3
-rw-r--r--HisiPkg/D01BoardPkg/Bds/BdsHelper.c4
-rw-r--r--HisiPkg/D01BoardPkg/Bds/BdsInternal.h19
-rw-r--r--HisiPkg/D01BoardPkg/Bds/BootMenu.c466
-rw-r--r--HisiPkg/D01BoardPkg/Bds/BootOption.c93
-rw-r--r--HisiPkg/D01BoardPkg/Bds/BootOptionSupport.c16
-rw-r--r--HisiPkg/D01BoardPkg/D01BoardPkg.dsc2
-rw-r--r--HisiPkg/D01BoardPkg/D01BoardPkg.fdf740
-rw-r--r--HisiPkg/D01BoardPkg/Library/D01LibRTSM/RTSM.c424
-rw-r--r--HisiPkg/D01BoardPkg/Library/D01SecLibRTSM/D01SecLib.inf50
-rw-r--r--HisiPkg/D01BoardPkg/Sec/Sec/Sec.c396
-rw-r--r--HisiPkg/Drivers/PL390Gic/PL390GicDxe.c850
-rw-r--r--HisiPkg/Drivers/PL390Gic/PL390GicDxe.inf118
-rw-r--r--HisiPkg/Drivers/TimerDxe/TimerDxe.c1114
-rw-r--r--HisiPkg/Drivers/TimerDxe/TimerDxe.inf118
-rw-r--r--HisiPkg/Include/Library/EblProvisionLib.h28
-rw-r--r--HisiPkg/Include/Library/Std.h4
-rw-r--r--HisiPkg/Include/Library/config.h876
-rw-r--r--HisiPkg/README98
20 files changed, 2512 insertions, 2954 deletions
diff --git a/HisiPkg/D01BoardPkg/Bds/Bds.c b/HisiPkg/D01BoardPkg/Bds/Bds.c
index 8005b0924..b16013199 100644
--- a/HisiPkg/D01BoardPkg/Bds/Bds.c
+++ b/HisiPkg/D01BoardPkg/Bds/Bds.c
@@ -301,11 +301,6 @@ DefineDefaultBootEntries (
EFI_DEVICE_PATH* BootDevicePath;
ARM_BDS_LOADER_ARGUMENTS* BootArguments;
ARM_BDS_LOADER_TYPE BootType;
- EFI_DEVICE_PATH* InitrdPath;
- EFI_DEVICE_PATH* FdtLocalPath;
- UINTN CmdLineSize;
- UINTN InitrdSize;
- UINTN FdtLocalSize;
//
// If Boot Order does not exist then create a default entry
@@ -337,50 +332,16 @@ DefineDefaultBootEntries (
ASSERT (StrCmp ((CHAR16*)PcdGetPtr(PcdDefaultBootDevicePath), DevicePathTxt) == 0);
if (DevicePathTxt != NULL){
- FreePool (DevicePathTxt);
+ FreePool (DevicePathTxt);
}
DEBUG_CODE_END();
+ BootArguments = NULL;
+
// Create the entry is the Default values are correct
if (BootDevicePath != NULL) {
BootType = (ARM_BDS_LOADER_TYPE)PcdGet32 (PcdDefaultBootType);
- if ((BootType == BDS_LOADER_KERNEL_LINUX_ATAG) || (BootType == BDS_LOADER_KERNEL_LINUX_GLOBAL_FDT) || (BootType == BDS_LOADER_KERNEL_LINUX_LOCAL_FDT)) {
- CmdLineSize = AsciiStrSize ((CHAR8*)PcdGetPtr(PcdDefaultBootArgument));
- InitrdPath = EfiDevicePathFromTextProtocol->ConvertTextToDevicePath ((CHAR16*)PcdGetPtr(PcdDefaultBootInitrdPath));
- if (InitrdPath != NULL) {
- InitrdSize = GetDevicePathSize (InitrdPath);
- } else {
- InitrdSize = 0;
- }
- if (BootType == BDS_LOADER_KERNEL_LINUX_LOCAL_FDT) {
- FdtLocalPath = EfiDevicePathFromTextProtocol->ConvertTextToDevicePath ((CHAR16*)PcdGetPtr(PcdDefaultFdtLocalDevicePath));
- FdtLocalSize = GetDevicePathSize (FdtLocalPath);
- } else {
- FdtLocalPath = NULL;
- FdtLocalSize = 0;
- }
-
- BootArguments = (ARM_BDS_LOADER_ARGUMENTS*)AllocatePool (sizeof(ARM_BDS_LOADER_ARGUMENTS) + CmdLineSize + InitrdSize + FdtLocalSize);
- if ( BootArguments != NULL ) {
- BootArguments->LinuxArguments.CmdLineSize = CmdLineSize;
- BootArguments->LinuxArguments.InitrdSize = InitrdSize;
- BootArguments->LinuxArguments.FdtLocalSize = FdtLocalSize;
-
- CopyMem ((VOID*)(BootArguments + 1), (CHAR8*)PcdGetPtr(PcdDefaultBootArgument), CmdLineSize);
- CopyMem ((VOID*)((UINTN)(BootArguments + 1) + CmdLineSize), InitrdPath, InitrdSize);
- CopyMem ((VOID*)((UINTN)(BootArguments + 1) + CmdLineSize + InitrdSize), FdtLocalPath, FdtLocalSize);
- }
- if (FdtLocalPath != NULL ) {
- FreePool (FdtLocalPath);
- }
- if (InitrdPath != NULL ) {
- FreePool (InitrdPath);
- }
- } else {
- BootArguments = NULL;
- }
-
BootOptionCreate (LOAD_OPTION_ACTIVE | LOAD_OPTION_CATEGORY_BOOT,
(CHAR16*)PcdGetPtr(PcdDefaultBootDescription),
BootDevicePath,
@@ -389,7 +350,7 @@ DefineDefaultBootEntries (
&BdsLoadOption
);
if (BdsLoadOption != NULL){
- FreePool (BdsLoadOption);
+ FreePool (BdsLoadOption);
}
if (BootDevicePath != NULL){
FreePool (BootDevicePath);
diff --git a/HisiPkg/D01BoardPkg/Bds/Bds.inf b/HisiPkg/D01BoardPkg/Bds/Bds.inf
index 195d0dcd6..eb63805aa 100644
--- a/HisiPkg/D01BoardPkg/Bds/Bds.inf
+++ b/HisiPkg/D01BoardPkg/Bds/Bds.inf
@@ -71,11 +71,8 @@
gArmPlatformTokenSpaceGuid.PcdFirmwareVendor
gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription
gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath
- gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath
gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument
gArmPlatformTokenSpaceGuid.PcdDefaultBootType
- gArmPlatformTokenSpaceGuid.PcdFdtDevicePath
- gArmPlatformTokenSpaceGuid.PcdDefaultFdtLocalDevicePath
gArmPlatformTokenSpaceGuid.PcdPlatformBootTimeOut
gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths
gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths
diff --git a/HisiPkg/D01BoardPkg/Bds/BdsHelper.c b/HisiPkg/D01BoardPkg/Bds/BdsHelper.c
index 733864ad0..5896baba7 100644
--- a/HisiPkg/D01BoardPkg/Bds/BdsHelper.c
+++ b/HisiPkg/D01BoardPkg/Bds/BdsHelper.c
@@ -36,7 +36,7 @@ EditHIInputStr (
Print (CmdLine);
// To prevent a buffer overflow, we only allow to enter (MaxCmdLine-1) characters
- for (CmdLineIndex = StrLen (CmdLine); CmdLineIndex < MaxCmdLine; ) {
+ for (CmdLineIndex = StrLen (CmdLine); CmdLineIndex < MaxCmdLine; ) {
Status = gBS->WaitForEvent (1, &gST->ConIn->WaitForKey, &WaitIndex);
ASSERT_EFI_ERROR (Status);
@@ -63,7 +63,7 @@ EditHIInputStr (
}
} else if ((Key.ScanCode == SCAN_ESC) || (Char == 0x1B) || (Char == 0x0)) {
return EFI_INVALID_PARAMETER;
- } else if (CmdLineIndex < (MaxCmdLine-1)) {
+ } else if (CmdLineIndex < (MaxCmdLine-1)) {
CmdLine[CmdLineIndex++] = Key.UnicodeChar;
Print (L"%c", Key.UnicodeChar);
}
diff --git a/HisiPkg/D01BoardPkg/Bds/BdsInternal.h b/HisiPkg/D01BoardPkg/Bds/BdsInternal.h
index 050aa32cf..601de1bc8 100644
--- a/HisiPkg/D01BoardPkg/Bds/BdsInternal.h
+++ b/HisiPkg/D01BoardPkg/Bds/BdsInternal.h
@@ -38,11 +38,11 @@
#define BOOT_DEVICE_OPTION_MAX 300
#define BOOT_DEVICE_ADDRESS_MAX (sizeof(L"0x0000000000000000"))
-// Length of the buffer used to hold the user input for the main menu
-// This includes the NULL terminator
-// 1 chars + newline + NULL gives room for up to 9 boot device configs
-#define BOOT_OPTION_LEN 3
-
+// Length of the buffer used to hold the user input for the main menu
+// This includes the NULL terminator
+// 1 chars + newline + NULL gives room for up to 9 boot device configs
+#define BOOT_OPTION_LEN 3
+
#define ARM_BDS_OPTIONAL_DATA_SIGNATURE SIGNATURE_32('a', 'b', 'o', 'd')
#define IS_ARM_BDS_BOOTENTRY(ptr) (ReadUnaligned32 ((CONST UINT32*)&((ARM_BDS_LOADER_OPTIONAL_DATA*)((ptr)->OptionalData))->Header.Signature) == ARM_BDS_OPTIONAL_DATA_SIGNATURE)
@@ -52,21 +52,18 @@
typedef enum {
BDS_LOADER_EFI_APPLICATION = 0,
- BDS_LOADER_KERNEL_LINUX_ATAG,
- BDS_LOADER_KERNEL_LINUX_GLOBAL_FDT,
- BDS_LOADER_KERNEL_LINUX_LOCAL_FDT,
} ARM_BDS_LOADER_TYPE;
typedef struct {
UINT16 CmdLineSize;
UINT16 InitrdSize;
- UINT16 FdtLocalSize;
-
+ UINT16 FdtLocalSize;
+
// These following fields have variable length and are packed:
//CHAR8 *CmdLine;
//EFI_DEVICE_PATH_PROTOCOL *InitrdPathList;
- //EFI_DEVICE_PATH_PROTOCOL *FdtLocalPathList;
+ //EFI_DEVICE_PATH_PROTOCOL *FdtLocalPathList;
} ARM_BDS_LINUX_ARGUMENTS;
typedef union {
diff --git a/HisiPkg/D01BoardPkg/Bds/BootMenu.c b/HisiPkg/D01BoardPkg/Bds/BootMenu.c
index e265c130f..e8f2b78ff 100644
--- a/HisiPkg/D01BoardPkg/Bds/BootMenu.c
+++ b/HisiPkg/D01BoardPkg/Bds/BootMenu.c
@@ -127,20 +127,11 @@ BootMenuAddBootOption (
BDS_SUPPORTED_DEVICE* SupportedBootDevice;
ARM_BDS_LOADER_ARGUMENTS* BootArguments;
CHAR16 BootDescription[BOOT_DEVICE_DESCRIPTION_MAX];
- CHAR8 CmdLine[BOOT_DEVICE_OPTION_MAX];
UINT32 Attributes;
ARM_BDS_LOADER_TYPE BootType;
BDS_LOAD_OPTION_ENTRY *BdsLoadOptionEntry;
EFI_DEVICE_PATH *DevicePath;
EFI_DEVICE_PATH_PROTOCOL *DevicePathNodes;
- EFI_DEVICE_PATH_PROTOCOL *InitrdPathNodes;
- EFI_DEVICE_PATH_PROTOCOL *InitrdPath;
- EFI_DEVICE_PATH_PROTOCOL *FdtLocalPathNode;
- EFI_DEVICE_PATH_PROTOCOL *FdtLocalPath;
- UINTN CmdLineSize;
- BOOLEAN InitrdSupport;
- UINTN InitrdSize;
- UINTN FdtLocalSize;
Attributes = 0;
SupportedBootDevice = NULL;
@@ -165,77 +156,7 @@ BootMenuAddBootOption (
goto EXIT;
}
- if ((BootType == BDS_LOADER_KERNEL_LINUX_ATAG) || (BootType == BDS_LOADER_KERNEL_LINUX_GLOBAL_FDT) || (BootType == BDS_LOADER_KERNEL_LINUX_LOCAL_FDT)) {
- Print(L"Add an initrd: ");
- Status = GetHIInputBoolean (&InitrdSupport);
- if (EFI_ERROR(Status)) {
- Status = EFI_ABORTED;
- goto FREE_DEVICE_PATH;
- }
-
- if (InitrdSupport) {
- // Create the specific device path node
- Status = SupportedBootDevice->Support->CreateDevicePathNode (L"initrd", &InitrdPathNodes, NULL, NULL);
- if (EFI_ERROR(Status) && Status != EFI_NOT_FOUND) { // EFI_NOT_FOUND is returned on empty input string, but we can boot without an initrd
- Status = EFI_ABORTED;
- goto FREE_DEVICE_PATH;
- }
-
- if (InitrdPathNodes != NULL) {
- // Append the Device Path to the selected device path
- InitrdPath = AppendDevicePath (SupportedBootDevice->DevicePathProtocol, (CONST EFI_DEVICE_PATH_PROTOCOL *)InitrdPathNodes);
- if (InitrdPath == NULL) {
- Status = EFI_OUT_OF_RESOURCES;
- goto FREE_DEVICE_PATH;
- }
- } else {
- InitrdPath = NULL;
- }
- } else {
- InitrdPath = NULL;
- }
-
- Print(L"Arguments to pass to the binary: ");
- Status = GetHIInputAscii (CmdLine,BOOT_DEVICE_OPTION_MAX);
- if (EFI_ERROR(Status)) {
- Status = EFI_ABORTED;
- goto FREE_DEVICE_PATH;
- }
-
- if (BootType == BDS_LOADER_KERNEL_LINUX_LOCAL_FDT) {
- // Create the specific device path node
- Status = SupportedBootDevice->Support->CreateDevicePathNode (L"local FDT", &FdtLocalPathNode, NULL, NULL);
- if (EFI_ERROR(Status) || (FdtLocalPathNode == NULL)) {
- Status = EFI_ABORTED;
- goto FREE_DEVICE_PATH;
- }
-
- if (FdtLocalPathNode != NULL) {
- // Append the Device Path node to the select device path
- FdtLocalPath = AppendDevicePathNode (SupportedBootDevice->DevicePathProtocol, (CONST EFI_DEVICE_PATH_PROTOCOL *)FdtLocalPathNode);
- } else {
- FdtLocalPath = NULL;
- }
- } else {
- FdtLocalPath = NULL;
- }
-
- CmdLineSize = AsciiStrSize (CmdLine);
- InitrdSize = GetDevicePathSize (InitrdPath);
- FdtLocalSize = GetDevicePathSize (FdtLocalPath);
-
- BootArguments = (ARM_BDS_LOADER_ARGUMENTS*)AllocatePool (sizeof(ARM_BDS_LOADER_ARGUMENTS) + CmdLineSize + InitrdSize + FdtLocalSize);
- if ( BootArguments != NULL ) {
- BootArguments->LinuxArguments.CmdLineSize = CmdLineSize;
- BootArguments->LinuxArguments.InitrdSize = InitrdSize;
- BootArguments->LinuxArguments.FdtLocalSize = FdtLocalSize;
- CopyMem ((VOID*)(&BootArguments->LinuxArguments + 1), CmdLine, CmdLineSize);
- CopyMem ((VOID*)((UINTN)(&BootArguments->LinuxArguments + 1) + CmdLineSize), InitrdPath, InitrdSize);
- CopyMem ((VOID*)((UINTN)(&BootArguments->LinuxArguments + 1) + CmdLineSize + InitrdSize), FdtLocalPath, FdtLocalSize);
- }
- } else {
- BootArguments = NULL;
- }
+ BootArguments = NULL;
Print(L"Description for this new Entry: ");
Status = GetHIInputStr (BootDescription, BOOT_DEVICE_DESCRIPTION_MAX);
@@ -300,19 +221,12 @@ BootMenuSelectBootOption (
DEBUG_CODE_BEGIN();
CHAR16* DevicePathTxt;
EFI_DEVICE_PATH_TO_TEXT_PROTOCOL* DevicePathToTextProtocol;
- ARM_BDS_LOADER_TYPE LoaderType;
- ARM_BDS_LOADER_OPTIONAL_DATA* OptionalData;
Status = gBS->LocateProtocol(&gEfiDevicePathToTextProtocolGuid, NULL, (VOID **)&DevicePathToTextProtocol);
ASSERT_EFI_ERROR(Status);
DevicePathTxt = DevicePathToTextProtocol->ConvertDevicePathToText(BdsLoadOption->FilePathList,TRUE,TRUE);
Print(L"\t- %s\n",DevicePathTxt);
- OptionalData = BdsLoadOption->OptionalData;
- LoaderType = (ARM_BDS_LOADER_TYPE)ReadUnaligned32 ((CONST UINT32*)&OptionalData->Header.LoaderType);
- if ((LoaderType == BDS_LOADER_KERNEL_LINUX_ATAG) || (LoaderType == BDS_LOADER_KERNEL_LINUX_GLOBAL_FDT) || (LoaderType == BDS_LOADER_KERNEL_LINUX_LOCAL_FDT)) {
- Print (L"\t- Arguments: %a\n",&OptionalData->Arguments.LinuxArguments + 1);
- }
FreePool(DevicePathTxt);
DEBUG_CODE_END();
@@ -399,22 +313,9 @@ BootMenuUpdateBootOption (
BDS_LOAD_OPTION_SUPPORT* DeviceSupport;
ARM_BDS_LOADER_ARGUMENTS* BootArguments;
CHAR16 BootDescription[BOOT_DEVICE_DESCRIPTION_MAX];
- CHAR8 CmdLine[BOOT_DEVICE_OPTION_MAX];
EFI_DEVICE_PATH *DevicePath;
- EFI_DEVICE_PATH *TempInitrdPath;
- EFI_DEVICE_PATH *TempFdtLocalPath;
ARM_BDS_LOADER_TYPE BootType;
ARM_BDS_LOADER_OPTIONAL_DATA* OptionalData;
- ARM_BDS_LINUX_ARGUMENTS* LinuxArguments;
- EFI_DEVICE_PATH *InitrdPathNodes;
- EFI_DEVICE_PATH *InitrdPath;
- UINTN InitrdSize;
- EFI_DEVICE_PATH *FdtLocalPathNode;
- EFI_DEVICE_PATH *FdtLocalPath;
- UINTN FdtLocalSize;
- UINTN CmdLineSize;
- BOOLEAN InitrdSupport;
- BOOLEAN FdtLocalSupport;
Status = BootMenuSelectBootOption (BootOptionsList, UPDATE_BOOT_ENTRY, TRUE, &BootOptionEntry);
if (EFI_ERROR(Status)) {
@@ -438,141 +339,7 @@ BootMenuUpdateBootOption (
OptionalData = BootOption->OptionalData;
BootType = (ARM_BDS_LOADER_TYPE)ReadUnaligned32 ((UINT32 *)(&OptionalData->Header.LoaderType));
- if ((BootType == BDS_LOADER_KERNEL_LINUX_ATAG) || (BootType == BDS_LOADER_KERNEL_LINUX_GLOBAL_FDT) || (BootType == BDS_LOADER_KERNEL_LINUX_LOCAL_FDT)) {
- LinuxArguments = &OptionalData->Arguments.LinuxArguments;
-
- CmdLineSize = ReadUnaligned16 ((CONST UINT16*)&LinuxArguments->CmdLineSize);
-
- InitrdSize = ReadUnaligned16 ((CONST UINT16*)&LinuxArguments->InitrdSize);
- FdtLocalSize = ReadUnaligned16 ((CONST UINT16*)&LinuxArguments->FdtLocalSize);
-
- if (BootType == BDS_LOADER_KERNEL_LINUX_LOCAL_FDT) {
- if (FdtLocalSize > 0) {
- Print(L"Keep the local FDT: ");
- } else {
- Print(L"Add a local FDT: ");
- }
- Status = GetHIInputBoolean (&FdtLocalSupport);
- if (EFI_ERROR(Status)) {
- Status = EFI_ABORTED;
- goto EXIT;
- }
- if (FdtLocalSupport && BootType == BDS_LOADER_KERNEL_LINUX_LOCAL_FDT) {
- if (FdtLocalSize > 0) {
- // Case we update the FDT local device path
- Status = DeviceSupport->UpdateDevicePathNode ((EFI_DEVICE_PATH*)((UINTN)(LinuxArguments + 1) + CmdLineSize + InitrdSize), L"local FDT", &FdtLocalPath, NULL, NULL);
- if (EFI_ERROR(Status) && Status != EFI_NOT_FOUND) {// EFI_NOT_FOUND is returned on empty input string
- Status = EFI_ABORTED;
- goto EXIT;
- }
- FdtLocalSize = GetDevicePathSize (FdtLocalPath);
- } else {
- // Case we create the FdtLocal device path
-
- Status = DeviceSupport->CreateDevicePathNode (L"local FDT", &FdtLocalPathNode, NULL, NULL);
- if (EFI_ERROR(Status) || (FdtLocalPathNode == NULL)) {
- Status = EFI_ABORTED;
- goto EXIT;
- }
-
- if (FdtLocalPathNode != NULL) {
- // Duplicate Linux kernel Device Path
- TempFdtLocalPath = DuplicateDevicePath (BootOption->FilePathList);
- if ( TempFdtLocalPath != NULL ) {
- // Replace Linux kernel Node by EndNode
- SetDevicePathEndNode (GetLastDevicePathNode (TempFdtLocalPath));
- // Append the Device Path node to the select device path
- FdtLocalPath = AppendDevicePathNode (TempFdtLocalPath, (CONST EFI_DEVICE_PATH_PROTOCOL *)FdtLocalPathNode);
- FreePool (TempFdtLocalPath);
- FdtLocalSize = GetDevicePathSize (FdtLocalPath);
- }
- } else {
- FdtLocalPath = NULL;
- }
- }
- } else {
- FdtLocalSize = 0;
- }
- } else {
- FdtLocalSupport = FALSE;
- }
-
- if (InitrdSize > 0) {
- Print(L"Keep the initrd: ");
- } else {
- Print(L"Add an initrd: ");
- }
- Status = GetHIInputBoolean (&InitrdSupport);
- if (EFI_ERROR(Status)) {
- Status = EFI_ABORTED;
- goto EXIT;
- }
-
- if (InitrdSupport) {
- if (InitrdSize > 0) {
- // Case we update the initrd device path
- Status = DeviceSupport->UpdateDevicePathNode ((EFI_DEVICE_PATH*)((UINTN)(LinuxArguments + 1) + CmdLineSize), L"initrd", &InitrdPath, NULL, NULL);
- if (EFI_ERROR(Status) && Status != EFI_NOT_FOUND) {// EFI_NOT_FOUND is returned on empty input string, but we can boot without an initrd
- Status = EFI_ABORTED;
- goto EXIT;
- }
- InitrdSize = GetDevicePathSize (InitrdPath);
- } else {
- // Case we create the initrd device path
-
- Status = DeviceSupport->CreateDevicePathNode (L"initrd", &InitrdPathNodes, NULL, NULL);
- if (EFI_ERROR(Status) && Status != EFI_NOT_FOUND) { // EFI_NOT_FOUND is returned on empty input string, but we can boot without an initrd
- Status = EFI_ABORTED;
- goto EXIT;
- }
-
- if (InitrdPathNodes != NULL) {
- // Duplicate Linux kernel Device Path
- TempInitrdPath = DuplicateDevicePath (BootOption->FilePathList);
- // Replace Linux kernel Node by EndNode
- SetDevicePathEndNode (GetLastDevicePathNode (TempInitrdPath));
- // Append the Device Path to the selected device path
- InitrdPath = AppendDevicePath (TempInitrdPath, (CONST EFI_DEVICE_PATH_PROTOCOL *)InitrdPathNodes);
- FreePool (TempInitrdPath);
- if (InitrdPath == NULL) {
- Status = EFI_OUT_OF_RESOURCES;
- goto EXIT;
- }
- InitrdSize = GetDevicePathSize (InitrdPath);
- } else {
- InitrdPath = NULL;
- }
- }
- } else {
- InitrdSize = 0;
- }
-
- Print(L"Arguments to pass to the binary: ");
- if (CmdLineSize > 0) {
- AsciiStrnCpy(CmdLine, (CONST CHAR8*)(LinuxArguments + 1), CmdLineSize);
- } else {
- CmdLine[0] = '\0';
- }
- Status = EditHIInputAscii (CmdLine, BOOT_DEVICE_OPTION_MAX);
- if (EFI_ERROR(Status)) {
- Status = EFI_ABORTED;
- goto FREE_DEVICE_PATH;
- }
-
- CmdLineSize = AsciiStrSize (CmdLine);
-
- BootArguments = (ARM_BDS_LOADER_ARGUMENTS*)AllocatePool(sizeof(ARM_BDS_LOADER_ARGUMENTS) + CmdLineSize + InitrdSize + FdtLocalSize);
- if ( BootArguments != NULL ) {
- BootArguments->LinuxArguments.CmdLineSize = CmdLineSize;
- BootArguments->LinuxArguments.InitrdSize = InitrdSize;
- BootArguments->LinuxArguments.FdtLocalSize = FdtLocalSize;
- CopyMem (&BootArguments->LinuxArguments + 1, CmdLine, CmdLineSize);
- CopyMem ((VOID*)((UINTN)(&BootArguments->LinuxArguments + 1) + CmdLineSize), InitrdPath, InitrdSize);
- CopyMem ((VOID*)((UINTN)(&BootArguments->LinuxArguments + 1) + CmdLineSize + InitrdSize), FdtLocalPath, FdtLocalSize);
- }
- } else {
- BootArguments = NULL;
- }
+ BootArguments = NULL;
Print(L"Description for this new Entry: ");
StrnCpy (BootDescription, BootOption->Description, BOOT_DEVICE_DESCRIPTION_MAX);
@@ -711,49 +478,49 @@ BootEBL (
return Status;
}
-
-EFI_STATUS
-BootShell (
- IN LIST_ENTRY *BootOptionsList
- )
-{
- EFI_STATUS Status;
-
- // Start EFI Shell
- Status = BdsLoadApplication (mImageHandle, L"Shell", 0, NULL);
- if (Status == EFI_NOT_FOUND) {
- Print (L"Error: EFI Application not found.\n");
- } else if (EFI_ERROR(Status)) {
- Print (L"Error: Status Code: 0x%X\n",(UINT32)Status);
- }
-
- return Status;
-}
-
-EFI_STATUS
-Reboot (
- IN LIST_ENTRY *BootOptionsList
- )
-{
- gRT->ResetSystem(EfiResetCold, EFI_SUCCESS, 0, NULL);
- return EFI_UNSUPPORTED;
-}
-
-EFI_STATUS
-Shutdown (
- IN LIST_ENTRY *BootOptionsList
- )
-{
- gRT->ResetSystem(EfiResetShutdown, EFI_SUCCESS, 0, NULL);
- return EFI_UNSUPPORTED;
-}
-
-EFI_STATUS
-BootLinuxAtagLoader (
- IN LIST_ENTRY *BootOptionsList
- )
-{
- EFI_STATUS Status;
+
+EFI_STATUS
+BootShell (
+ IN LIST_ENTRY *BootOptionsList
+ )
+{
+ EFI_STATUS Status;
+
+ // Start EFI Shell
+ Status = BdsLoadApplication (mImageHandle, L"Shell", 0, NULL);
+ if (Status == EFI_NOT_FOUND) {
+ Print (L"Error: EFI Application not found.\n");
+ } else if (EFI_ERROR(Status)) {
+ Print (L"Error: Status Code: 0x%X\n",(UINT32)Status);
+ }
+
+ return Status;
+}
+
+EFI_STATUS
+Reboot (
+ IN LIST_ENTRY *BootOptionsList
+ )
+{
+ gRT->ResetSystem(EfiResetCold, EFI_SUCCESS, 0, NULL);
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+Shutdown (
+ IN LIST_ENTRY *BootOptionsList
+ )
+{
+ gRT->ResetSystem(EfiResetShutdown, EFI_SUCCESS, 0, NULL);
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+BootLinuxAtagLoader (
+ IN LIST_ENTRY *BootOptionsList
+ )
+{
+ EFI_STATUS Status;
Status = BdsLoadApplication (mImageHandle, (CHAR16 *)L"LinuxAtagLoader", 0, NULL);
if (Status == EFI_NOT_FOUND) {
@@ -763,8 +530,8 @@ BootLinuxAtagLoader (
}
return Status;
-}
-
+}
+
EFI_STATUS LoadLinuxAtSecEnd()
{
LinuxEntry entry = (LinuxEntry)(0x10c00000);
@@ -779,11 +546,11 @@ EFI_STATUS LoadLinuxAtSecEnd()
return Status;
}
-EFI_STATUS
-BootGo (
- IN LIST_ENTRY *BootOptionsList
- )
-{
+EFI_STATUS
+BootGo (
+ IN LIST_ENTRY *BootOptionsList
+ )
+{
EFI_STATUS Status;
Status = ShutdownUefiBootServices ();
@@ -804,18 +571,18 @@ BootGo (
}
return Status;
-}
-
+}
+
struct BOOT_MAIN_ENTRY {
CONST CHAR16* Description;
EFI_STATUS (*Callback) (IN LIST_ENTRY *BootOptionsList);
} BootMainEntries[] = {
{ L"Boot Manager", BootMenuManager },
- { L"EBL", BootEBL },
- { L"Shell", BootShell },
- { L"Reboot", Reboot },
- { L"Shutdown", Shutdown },
- { L"GO", BootGo },
+ { L"EBL", BootEBL },
+ { L"Shell", BootShell },
+ { L"Reboot", Reboot },
+ { L"Shutdown", Shutdown },
+ { L"GO", BootGo },
};
@@ -824,21 +591,19 @@ BootMenuMain (
VOID
)
{
- LIST_ENTRY BootOptionsList;
- UINTN OptionCount;
- UINTN BootOptionCount;
- EFI_STATUS Status;
- LIST_ENTRY* Entry;
- BDS_LOAD_OPTION* BootOption;
- UINTN BootOptionSelected;
- UINTN Index;
- UINTN BootMainEntryCount;
- CHAR8 BootOptionSelectedStr[BOOT_OPTION_LEN];
- EFI_DEVICE_PATH_PROTOCOL* DefaultFdtDevicePath;
- UINTN FdtDevicePathSize;
+ LIST_ENTRY BootOptionsList;
+ UINTN OptionCount;
+ UINTN BootOptionCount;
+ EFI_STATUS Status;
+ LIST_ENTRY* Entry;
+ BDS_LOAD_OPTION* BootOption;
+ UINTN BootOptionSelected;
+ UINTN Index;
+ UINTN BootMainEntryCount;
+ CHAR8 BootOptionSelectedStr[BOOT_OPTION_LEN];
EFI_DEVICE_PATH_TO_TEXT_PROTOCOL* DevicePathToTextProtocol;
CHAR16* DevicePathTxt;
-
+
BootOption = NULL;
BootMainEntryCount = sizeof(BootMainEntries) / sizeof(struct BOOT_MAIN_ENTRY);
@@ -859,10 +624,8 @@ BootMenuMain (
Print(L"[%d] %s\n", OptionCount, BootOption->Description);
- //DEBUG_CODE_BEGIN();
+ //DEBUG_CODE_BEGIN();
ARM_BDS_LOADER_OPTIONAL_DATA* OptionalData;
- UINTN CmdLineSize;
- UINTN InitrdSize;
ARM_BDS_LOADER_TYPE LoaderType;
Status = gBS->LocateProtocol (&gEfiDevicePathToTextProtocolGuid, NULL, (VOID **)&DevicePathToTextProtocol);
@@ -879,43 +642,15 @@ BootMenuMain (
if (IS_ARM_BDS_BOOTENTRY (BootOption)) {
OptionalData = BootOption->OptionalData;
LoaderType = (ARM_BDS_LOADER_TYPE)ReadUnaligned32 ((CONST UINT32*)&OptionalData->Header.LoaderType);
- if ((LoaderType == BDS_LOADER_KERNEL_LINUX_ATAG) || (LoaderType == BDS_LOADER_KERNEL_LINUX_GLOBAL_FDT) || (LoaderType == BDS_LOADER_KERNEL_LINUX_LOCAL_FDT)) {
- if (ReadUnaligned16 (&OptionalData->Arguments.LinuxArguments.InitrdSize) > 0) {
- CmdLineSize = ReadUnaligned16 (&OptionalData->Arguments.LinuxArguments.CmdLineSize);
- DevicePathTxt = DevicePathToTextProtocol->ConvertDevicePathToText (
- GetAlignedDevicePath ((EFI_DEVICE_PATH*)((UINTN)(&OptionalData->Arguments.LinuxArguments + 1) + CmdLineSize)), TRUE, TRUE);
- Print(L"\t- Initrd: %s\n", DevicePathTxt);
- }
- Print(L"\t- Arguments: %a\n", (&OptionalData->Arguments.LinuxArguments + 1));
- }
switch (LoaderType) {
case BDS_LOADER_EFI_APPLICATION:
Print(L"\t- LoaderType: EFI Application\n");
break;
- case BDS_LOADER_KERNEL_LINUX_ATAG:
- Print(L"\t- LoaderType: Linux kernel with ATAG support\n");
- break;
-
- case BDS_LOADER_KERNEL_LINUX_GLOBAL_FDT:
- Print(L"\t- LoaderType: Linux kernel with global FDT support\n");
- break;
- case BDS_LOADER_KERNEL_LINUX_LOCAL_FDT:
- if (ReadUnaligned16 (&OptionalData->Arguments.LinuxArguments.FdtLocalSize) > 0) {
- CmdLineSize = ReadUnaligned16 (&OptionalData->Arguments.LinuxArguments.CmdLineSize);
- InitrdSize = ReadUnaligned16 (&OptionalData->Arguments.LinuxArguments.InitrdSize);
- DevicePathTxt = DevicePathToTextProtocol->ConvertDevicePathToText (
- GetAlignedDevicePath ((EFI_DEVICE_PATH*)((UINTN)(&OptionalData->Arguments.LinuxArguments + 1) + CmdLineSize + InitrdSize)), TRUE, TRUE);
- Print(L"\t- FDT: %s\n", DevicePathTxt);
- } else {
- Print(L"\t- FDT: error, local FDT not specified, using global FDT\n");
- }
- Print(L"\t- LoaderType: Linux kernel with Local FDT\n");
- break;
default:
Print(L"\t- LoaderType: Not recognized (%d)\n", LoaderType);
- break;
+ break;
}
}
FreePool(DevicePathTxt);
@@ -925,37 +660,10 @@ BootMenuMain (
}
BootOptionCount = OptionCount-1;
- // Display the global FDT config
- Print(L"-----------------------\n");
- {
- EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL* EfiDevicePathFromTextProtocol;
- EFI_DEVICE_PATH_PROTOCOL* FdtDevicePath;
-
- // Get the default FDT device path
- Status = gBS->LocateProtocol (&gEfiDevicePathFromTextProtocolGuid, NULL, (VOID **)&EfiDevicePathFromTextProtocol);
- ASSERT_EFI_ERROR(Status);
- DefaultFdtDevicePath = EfiDevicePathFromTextProtocol->ConvertTextToDevicePath ((CHAR16*)PcdGetPtr(PcdFdtDevicePath));
-
- // Get the FDT device path
- FdtDevicePathSize = GetDevicePathSize (DefaultFdtDevicePath);
- Status = GetEnvironmentVariable ((CHAR16 *)L"Fdt", &gArmGlobalVariableGuid, DefaultFdtDevicePath, &FdtDevicePathSize, (VOID **)&FdtDevicePath);
-
- // Convert FdtDevicePath to text
- if (EFI_ERROR(Status)) {
- DevicePathTxt = L"not configured";
- } else {
- Status = gBS->LocateProtocol (&gEfiDevicePathToTextProtocolGuid, NULL, (VOID **)&DevicePathToTextProtocol);
- DevicePathTxt = DevicePathToTextProtocol->ConvertDevicePathToText ( FdtDevicePath, TRUE, TRUE );
- }
- Print(L"Global FDT Config\n\t- %s\n", DevicePathTxt);
- FreePool(DevicePathTxt);
- FreePool(DefaultFdtDevicePath);
- }
-
// Display the hardcoded Boot entries
- Print(L"-----------------------\n");
+ Print(L"-----------------------\n");
for (Index = 0; Index < BootMainEntryCount; Index++) {
- Print(L"[%c] %s\n", ('a' + Index), BootMainEntries[Index]);
+ Print(L"[%c] %s\n", ('a' + Index), BootMainEntries[Index]);
OptionCount++;
}
@@ -963,20 +671,20 @@ BootMenuMain (
BootOptionSelected = 0;
while (BootOptionSelected == 0) {
Print(L"Start: ");
- Status = GetHIInputAscii (BootOptionSelectedStr, BOOT_OPTION_LEN);
-
- if (!EFI_ERROR(Status)) {
- if ((BootOptionSelectedStr[0] - '0') < OptionCount) {
- BootOptionSelected = BootOptionSelectedStr[0] - '0';
- } else if ((BootOptionSelectedStr[0] - 'a') < BootMainEntryCount) {
- BootOptionSelected = BootOptionCount + 1 + BootOptionSelectedStr[0] - 'a';
- }
-
- if ((BootOptionSelected == 0) || (BootOptionSelected > OptionCount)) {
- Print(L"Invalid input, please choose a menu option from the list above\n");
- BootOptionSelected = 0;
+ Status = GetHIInputAscii (BootOptionSelectedStr, BOOT_OPTION_LEN);
+
+ if (!EFI_ERROR(Status)) {
+ if ((BootOptionSelectedStr[0] - '0') < OptionCount) {
+ BootOptionSelected = BootOptionSelectedStr[0] - '0';
+ } else if ((BootOptionSelectedStr[0] - 'a') < BootMainEntryCount) {
+ BootOptionSelected = BootOptionCount + 1 + BootOptionSelectedStr[0] - 'a';
}
- }
+
+ if ((BootOptionSelected == 0) || (BootOptionSelected > OptionCount)) {
+ Print(L"Invalid input, please choose a menu option from the list above\n");
+ BootOptionSelected = 0;
+ }
+ }
}
// Start the selected entry
diff --git a/HisiPkg/D01BoardPkg/Bds/BootOption.c b/HisiPkg/D01BoardPkg/Bds/BootOption.c
index d677687f7..2872b46f0 100644
--- a/HisiPkg/D01BoardPkg/Bds/BootOption.c
+++ b/HisiPkg/D01BoardPkg/Bds/BootOption.c
@@ -24,17 +24,8 @@ BootOptionStart (
)
{
EFI_STATUS Status;
- EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL* EfiDevicePathFromTextProtocol;
UINT32 LoaderType;
ARM_BDS_LOADER_OPTIONAL_DATA* OptionalData;
- ARM_BDS_LINUX_ARGUMENTS* LinuxArguments;
- EFI_DEVICE_PATH_PROTOCOL* FdtDevicePath;
- EFI_DEVICE_PATH_PROTOCOL* DefaultFdtDevicePath;
- UINTN FdtDevicePathSize;
- UINTN CmdLineSize;
- UINTN InitrdSize;
- EFI_DEVICE_PATH* Initrd;
- UINTN FdtLocalSize;
UINT16 LoadOptionIndexSize;
if (IS_ARM_BDS_BOOTENTRY (BootOption)) {
@@ -47,58 +38,7 @@ BootOptionStart (
BdsConnectAllDrivers();
Status = BdsStartEfiApplication (mImageHandle, BootOption->FilePathList, 0, NULL);
- } else if (LoaderType == BDS_LOADER_KERNEL_LINUX_ATAG) {
- LinuxArguments = &(OptionalData->Arguments.LinuxArguments);
- CmdLineSize = ReadUnaligned16 ((CONST UINT16*)&LinuxArguments->CmdLineSize);
- InitrdSize = ReadUnaligned16 ((CONST UINT16*)&LinuxArguments->InitrdSize);
-
- if (InitrdSize > 0) {
- Initrd = GetAlignedDevicePath ((EFI_DEVICE_PATH*)((UINTN)(LinuxArguments + 1) + CmdLineSize));
- } else {
- Initrd = NULL;
- }
-
- Status = BdsBootLinuxAtag (BootOption->FilePathList,
- Initrd, // Initrd
- (CHAR8*)(LinuxArguments + 1)); // CmdLine
- } else if ((LoaderType == BDS_LOADER_KERNEL_LINUX_GLOBAL_FDT) || (LoaderType == BDS_LOADER_KERNEL_LINUX_LOCAL_FDT)) {
- LinuxArguments = &(OptionalData->Arguments.LinuxArguments);
- CmdLineSize = ReadUnaligned16 ((CONST UINT16*)&LinuxArguments->CmdLineSize);
- InitrdSize = ReadUnaligned16 ((CONST UINT16*)&LinuxArguments->InitrdSize);
-
- if (InitrdSize > 0) {
- Initrd = GetAlignedDevicePath ((EFI_DEVICE_PATH*)((UINTN)(LinuxArguments + 1) + CmdLineSize));
- } else {
- Initrd = NULL;
- }
-
- if (LoaderType == BDS_LOADER_KERNEL_LINUX_LOCAL_FDT) {
- FdtLocalSize = ReadUnaligned16 ((CONST UINT16*)&LinuxArguments->FdtLocalSize);
-
- if (FdtLocalSize > 0) {
- FdtDevicePath = GetAlignedDevicePath ((EFI_DEVICE_PATH*)((UINTN)(LinuxArguments + 1) + CmdLineSize + InitrdSize));
- } else {
- FdtDevicePath = NULL;
- }
- } else {
- // Get the default FDT device path
- Status = gBS->LocateProtocol (&gEfiDevicePathFromTextProtocolGuid, NULL, (VOID **)&EfiDevicePathFromTextProtocol);
- ASSERT_EFI_ERROR(Status);
- DefaultFdtDevicePath = EfiDevicePathFromTextProtocol->ConvertTextToDevicePath ((CHAR16*)PcdGetPtr(PcdFdtDevicePath));
-
- // Get the FDT device path
- FdtDevicePathSize = GetDevicePathSize (DefaultFdtDevicePath);
- Status = GetEnvironmentVariable ((CHAR16 *)L"Fdt", &gArmGlobalVariableGuid,
- DefaultFdtDevicePath, &FdtDevicePathSize, (VOID **)&FdtDevicePath);
- ASSERT_EFI_ERROR(Status);
- FreePool (DefaultFdtDevicePath);
- }
- Status = BdsBootLinuxFdt (BootOption->FilePathList,
- Initrd, // Initrd
- (CHAR8*)(LinuxArguments + 1),
- FdtDevicePath);
-
- FreePool (FdtDevicePath);
+ } else {
}
} else {
// Set BootCurrent variable
@@ -170,11 +110,7 @@ BootOptionSetFields (
UINTN BootOptionalDataSize;
UINT16 FilePathListLength;
UINT8* EfiLoadOptionPtr;
- UINT8* InitrdPathListPtr;
- UINT8* FdtLocalPathListPtr;
UINTN OptionalDataSize;
- ARM_BDS_LINUX_ARGUMENTS* DestLinuxArguments;
- ARM_BDS_LINUX_ARGUMENTS* SrcLinuxArguments;
// If we are overwriting an existent Boot Option then we have to free previously allocated memory
if (BootOption->LoadOption) {
@@ -183,9 +119,6 @@ BootOptionSetFields (
BootDescriptionSize = StrSize (BootDescription);
BootOptionalDataSize = sizeof(ARM_BDS_LOADER_OPTIONAL_DATA_HEADER);
- if ((BootType == BDS_LOADER_KERNEL_LINUX_ATAG) || (BootType == BDS_LOADER_KERNEL_LINUX_GLOBAL_FDT) || (BootType == BDS_LOADER_KERNEL_LINUX_LOCAL_FDT)) {
- BootOptionalDataSize += sizeof(ARM_BDS_LINUX_ARGUMENTS) + BootArguments->LinuxArguments.CmdLineSize + BootArguments->LinuxArguments.InitrdSize + BootArguments->LinuxArguments.FdtLocalSize;
- }
// Compute the size of the FilePath list
FilePathListLength = GetUnalignedDevicePathSize (DevicePath);
@@ -226,30 +159,6 @@ BootOptionSetFields (
OptionalDataSize = sizeof(ARM_BDS_LOADER_OPTIONAL_DATA_HEADER);
- if ((BootType == BDS_LOADER_KERNEL_LINUX_ATAG) || (BootType == BDS_LOADER_KERNEL_LINUX_GLOBAL_FDT) || (BootType == BDS_LOADER_KERNEL_LINUX_LOCAL_FDT)) {
- SrcLinuxArguments = &(BootArguments->LinuxArguments);
- DestLinuxArguments = &((ARM_BDS_LOADER_OPTIONAL_DATA*)EfiLoadOptionPtr)->Arguments.LinuxArguments;
-
- WriteUnaligned16 ((UINT16 *)&(DestLinuxArguments->CmdLineSize), SrcLinuxArguments->CmdLineSize);
- WriteUnaligned16 ((UINT16 *)&(DestLinuxArguments->InitrdSize), SrcLinuxArguments->InitrdSize);
- WriteUnaligned16 ((UINT16 *)&(DestLinuxArguments->FdtLocalSize), SrcLinuxArguments->FdtLocalSize);
- OptionalDataSize += sizeof (ARM_BDS_LINUX_ARGUMENTS);
-
- if (SrcLinuxArguments->CmdLineSize > 0) {
- CopyMem ((VOID*)(DestLinuxArguments + 1), (VOID*)(SrcLinuxArguments + 1), SrcLinuxArguments->CmdLineSize);
- OptionalDataSize += SrcLinuxArguments->CmdLineSize;
- }
-
- if (SrcLinuxArguments->InitrdSize > 0) {
- InitrdPathListPtr = (UINT8*)((UINTN)(DestLinuxArguments + 1) + SrcLinuxArguments->CmdLineSize);
- CopyMem (InitrdPathListPtr, (VOID*)((UINTN)(SrcLinuxArguments + 1) + SrcLinuxArguments->CmdLineSize), SrcLinuxArguments->InitrdSize);
- }
-
- if (SrcLinuxArguments->FdtLocalSize > 0) {
- FdtLocalPathListPtr = (UINT8*)((UINTN)(DestLinuxArguments + 1) + SrcLinuxArguments->CmdLineSize + SrcLinuxArguments->InitrdSize);
- CopyMem (FdtLocalPathListPtr, (VOID*)((UINTN)(SrcLinuxArguments + 1) + SrcLinuxArguments->CmdLineSize + SrcLinuxArguments->InitrdSize), SrcLinuxArguments->FdtLocalSize);
- }
- }
BootOption->OptionalDataSize = OptionalDataSize;
// If this function is called at the creation of the Boot Device entry (not at the update) the
diff --git a/HisiPkg/D01BoardPkg/Bds/BootOptionSupport.c b/HisiPkg/D01BoardPkg/Bds/BootOptionSupport.c
index 7c1ca13b1..09fcb23b2 100644
--- a/HisiPkg/D01BoardPkg/Bds/BootOptionSupport.c
+++ b/HisiPkg/D01BoardPkg/Bds/BootOptionSupport.c
@@ -235,7 +235,6 @@ BootDeviceGetType (
EFI_STATUS Status;
BOOLEAN IsEfiApp;
BOOLEAN IsBootLoader;
- CHAR16 FDTType[ LOCAL_FDT_RESPONSE_LEN ];
if (FileName == NULL) {
Print(L"Is an EFI Application? ");
@@ -260,20 +259,7 @@ BootDeviceGetType (
}
*BootType = BDS_LOADER_EFI_APPLICATION;
} else {
- Print(L"Boot Type: [a] ATAGS, [g] Global FDT or [l] Local FDT? [a/g/l] ");
- Status = GetHIInputStr (FDTType, LOCAL_FDT_RESPONSE_LEN );
- if (EFI_ERROR(Status)) {
- return EFI_ABORTED;
- }
- if (StrCmp(FDTType, L"g") == 0) {
- *BootType = BDS_LOADER_KERNEL_LINUX_GLOBAL_FDT;
- } else if (StrCmp(FDTType, L"l") == 0) {
- *BootType = BDS_LOADER_KERNEL_LINUX_LOCAL_FDT;
- } else if (StrCmp(FDTType, L"a") == 0) {
- *BootType = BDS_LOADER_KERNEL_LINUX_ATAG;
- } else {
- return EFI_ABORTED;
- }
+ return EFI_ABORTED;
}
return EFI_SUCCESS;
diff --git a/HisiPkg/D01BoardPkg/D01BoardPkg.dsc b/HisiPkg/D01BoardPkg/D01BoardPkg.dsc
index d1808bfd0..bf856d5d6 100644
--- a/HisiPkg/D01BoardPkg/D01BoardPkg.dsc
+++ b/HisiPkg/D01BoardPkg/D01BoardPkg.dsc
@@ -279,7 +279,7 @@
HisiPkg/Drivers/ramdisk/ramdisk.inf
#HisiPkg/Drivers/FlashDriver/FlashDriver.inf
-
+
#HisiPkg/Drivers/NandFlash/NandFlashDxe.inf
#
diff --git a/HisiPkg/D01BoardPkg/D01BoardPkg.fdf b/HisiPkg/D01BoardPkg/D01BoardPkg.fdf
index 8f9861690..427e5fe2c 100644
--- a/HisiPkg/D01BoardPkg/D01BoardPkg.fdf
+++ b/HisiPkg/D01BoardPkg/D01BoardPkg.fdf
@@ -1,370 +1,370 @@
-# FLASH layout file for ARM VE.
-#
-# Copyright (c) 2011, ARM Limited. All rights reserved.
-# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-
-################################################################################
-#
-# FD Section
-# The [FD] Section is made up of the definition statements and a
-# description of what goes into the Flash Device Image. Each FD section
-# defines one flash "device" image. A flash device image may be one of
-# the following: Removable media bootable image (like a boot floppy
-# image,) an Option ROM image (that would be "flashed" into an add-in
-# card,) a System "Flash" image (that would be burned into a system's
-# flash) or an Update ("Capsule") image that will be used to update and
-# existing system flash.
-#
-################################################################################
-
-[FD.D01]
-BaseAddress = 0xf0100000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
-Size = 0x00100000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device
-ErasePolarity = 1
-
-# This one is tricky, it must be: BlockSize * NumBlocks = Size
-BlockSize = 0x00001000
-NumBlocks = 0x100
-
-################################################################################
-#
-# Following are lists of FD Region layout which correspond to the locations of different
-# images within the flash device.
-#
-# Regions must be defined in ascending order and may not overlap.
-#
-# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
-# the pipe "|" character, followed by the size of the region, also in hex with the leading
-# "0x" characters. Like:
-# Offset|Size
-# PcdOffsetCName|PcdSizeCName
-# RegionType <FV, DATA, or FILE>
-#
-################################################################################
-
-0x00000000|0x00020000
-gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize
-FV = FVMAIN_SEC
-
-0x00020000|0x000e0000
-gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
-FV = FVMAIN_COMPACT
-
-
-################################################################################
-#
-# FV Section
-#
-# [FV] section is used to define what components or modules are placed within a flash
-# device file. This section also defines order the components and modules are positioned
-# within the image. The [FV] section consists of define statements, set statements and
-# module statements.
-#
-################################################################################
-
-[FV.FVMAIN_SEC]
-FvAlignment = 8
-ERASE_POLARITY = 1
-MEMORY_MAPPED = TRUE
-STICKY_WRITE = TRUE
-LOCK_CAP = TRUE
-LOCK_STATUS = TRUE
-WRITE_DISABLED_CAP = TRUE
-WRITE_ENABLED_CAP = TRUE
-WRITE_STATUS = TRUE
-WRITE_LOCK_CAP = TRUE
-WRITE_LOCK_STATUS = TRUE
-READ_DISABLED_CAP = TRUE
-READ_ENABLED_CAP = TRUE
-READ_STATUS = TRUE
-READ_LOCK_CAP = TRUE
-READ_LOCK_STATUS = TRUE
-
- INF HisiPkg/D01BoardPkg/Sec/Sec/Sec.inf
-
-
-[FV.FvMain]
-BlockSize = 0x40
-NumBlocks = 0 # This FV gets compressed so make it just big enough
-FvAlignment = 8 # FV alignment and FV attributes setting.
-ERASE_POLARITY = 1
-MEMORY_MAPPED = TRUE
-STICKY_WRITE = TRUE
-LOCK_CAP = TRUE
-LOCK_STATUS = TRUE
-WRITE_DISABLED_CAP = TRUE
-WRITE_ENABLED_CAP = TRUE
-WRITE_STATUS = TRUE
-WRITE_LOCK_CAP = TRUE
-WRITE_LOCK_STATUS = TRUE
-READ_DISABLED_CAP = TRUE
-READ_ENABLED_CAP = TRUE
-READ_STATUS = TRUE
-READ_LOCK_CAP = TRUE
-READ_LOCK_STATUS = TRUE
-
- INF MdeModulePkg/Core/Dxe/DxeMain.inf
-
- #
- # PI DXE Drivers producing Architectural Protocols (EFI Services)
- #
- INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
- INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
- INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
- INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
- #INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
- #INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
- INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
- #INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
- INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
- INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
- INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
- INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
-
- INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
-
- #
- # Multiple Console IO support
- #
- INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
- INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
- #INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
- INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
- INF EmbeddedPkg/SerialDxe/SerialDxe.inf
-
- INF HisiPkg/Drivers/PL390Gic/PL390GicDxe.inf
- #INF ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf
- INF HisiPkg/Drivers/TimerDxe/TimerDxe.inf
-
- INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
- INF HisiPkg/Drivers/WatchDogDriver/WatchDogDriver.inf
-
- INF HisiPkg/Drivers/LinuxAtagList/LinuxAtagList.inf
-
- #
- # Semi-hosting filesystem
- #
- #INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
-
- # RamDisk filesystem
- INF HisiPkg/Drivers/ramdisk/ramdisk.inf
-
- #NorFlash Driver
- INF HisiPkg/Drivers/FlashDriver/FlashDriver.inf
-
-
- INF HisiPkg/Drivers/NandFlash/NandFlashDxe.inf
-
- #
- # FAT filesystem + GPT/MBR partitioning
- #
- INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
- INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
- #INF FatPkg/EnhancedFatDxe/Fat.inf
- INF RuleOverride = BINARY FatBinPkg/EnhancedFatDxe/Fat.inf
- INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
-
-
- INF HisiPkg/Drivers/AtaAtapiPassThru/AtaAtapiPassThru.inf
- INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
-
- #
- # Multimedia Card Interface
- #
- #INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
- #INF ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
-
- #
- # network
- #
- INF HisiPkg/D01BoardPkg/Drivers/SnpPV600Dxe/SnpPV600Dxe.inf
- INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
- INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
- INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
- INF MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf
- INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
- INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
- INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
- INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
- INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
- INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
- INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
-
- #
- # UEFI application (Shell Embedded Boot Loader)
- #
- INF HisiPkg/D01BoardPkg/Application/Ebl/Ebl.inf
- INF ShellBinPkg/UefiShell/UefiShell.inf
-
- #
- # Bds
- #
- INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
- INF HisiPkg/D01BoardPkg/Bds/Bds.inf
-
-[FV.FVMAIN_COMPACT]
-FvAlignment = 8
-ERASE_POLARITY = 1
-MEMORY_MAPPED = TRUE
-STICKY_WRITE = TRUE
-LOCK_CAP = TRUE
-LOCK_STATUS = TRUE
-WRITE_DISABLED_CAP = TRUE
-WRITE_ENABLED_CAP = TRUE
-WRITE_STATUS = TRUE
-WRITE_LOCK_CAP = TRUE
-WRITE_LOCK_STATUS = TRUE
-READ_DISABLED_CAP = TRUE
-READ_ENABLED_CAP = TRUE
-READ_STATUS = TRUE
-READ_LOCK_CAP = TRUE
-READ_LOCK_STATUS = TRUE
-
-#!if $(EDK2_SKIP_PEICORE) == 1
- INF ArmPlatformPkg/PrePi/PeiMPCore.inf
-#!else
-# INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
-# INF MdeModulePkg/Core/Pei/PeiMain.inf
-# INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
-# INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
-# INF ArmPkg/Drivers/CpuPei/CpuPei.inf
-# INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
-# INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
-# INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
-# INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
-#!endif
-
- FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
- SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
- SECTION FV_IMAGE = FVMAIN
- }
- }
-
-
-################################################################################
-#
-# Rules are use with the [FV] section's module INF type to define
-# how an FFS file is created for a given INF file. The following Rule are the default
-# rules for the different module type. User can add the customized rules to define the
-# content of the FFS file.
-#
-################################################################################
-
-
-############################################################################
-# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
-############################################################################
-#
-#[Rule.Common.DXE_DRIVER]
-# FILE DRIVER = $(NAMED_GUID) {
-# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
-# COMPRESS PI_STD {
-# GUIDED {
-# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
-# UI STRING="$(MODULE_NAME)" Optional
-# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
-# }
-# }
-# }
-#
-############################################################################
-
-[Rule.Common.SEC]
- FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
- TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
- }
-
-[Rule.Common.SEC.BINARY]
- FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
- TE TE Align = 32 |.efi
- }
-
-[Rule.Common.PEI_CORE]
- FILE PEI_CORE = $(NAMED_GUID) {
- TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
- UI STRING ="$(MODULE_NAME)" Optional
- }
-
-[Rule.Common.PEIM]
- FILE PEIM = $(NAMED_GUID) {
- PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
- TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
- UI STRING="$(MODULE_NAME)" Optional
- }
-
-[Rule.Common.PEIM.TIANOCOMPRESSED]
- FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
- PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
- GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
- UI STRING="$(MODULE_NAME)" Optional
- }
- }
-
-[Rule.Common.DXE_CORE]
- FILE DXE_CORE = $(NAMED_GUID) {
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
- UI STRING="$(MODULE_NAME)" Optional
- }
-
-[Rule.Common.UEFI_DRIVER]
- FILE DRIVER = $(NAMED_GUID) {
- DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
- UI STRING="$(MODULE_NAME)" Optional
- }
-
-[Rule.Common.UEFI_DRIVER.BINARY]
- FILE DRIVER = $(NAMED_GUID) {
- DXE_DEPEX DXE_DEPEX Optional |.depex
- PE32 PE32 |.efi
- UI STRING="$(MODULE_NAME)" Optional
- }
-
-[Rule.Common.DXE_DRIVER]
- FILE DRIVER = $(NAMED_GUID) {
- DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
- UI STRING="$(MODULE_NAME)" Optional
- }
-[Rule.Common.DXE_DRIVER.BINARY]
- FILE DRIVER = $(NAMED_GUID) {
- DXE_DEPEX DXE_DEPEX Optional |.depex
- PE32 PE32 |.efi
- UI STRING="$(MODULE_NAME)" Optional
- }
-
-[Rule.Common.DXE_RUNTIME_DRIVER]
- FILE DRIVER = $(NAMED_GUID) {
- DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
- UI STRING="$(MODULE_NAME)" Optional
- }
-
-[Rule.Common.UEFI_APPLICATION]
- FILE APPLICATION = $(NAMED_GUID) {
- UI STRING ="$(MODULE_NAME)" Optional
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
- }
-
-[Rule.Common.UEFI_APPLICATION.BINARY]
- FILE APPLICATION = $(NAMED_GUID) {
- PE32 PE32 |.efi
- UI STRING="$(MODULE_NAME)" Optional
-}
-
-[Rule.Common.USER_DEFINED]
- FILE FREEFORM = $(NAMED_GUID) {
- RAW ACPI Optional |.acpi
- RAW ASL Optional |.aml
- }
-
+# FLASH layout file for ARM VE.
+#
+# Copyright (c) 2011, ARM Limited. All rights reserved.
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.D01]
+BaseAddress = 0xf0100000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
+Size = 0x00100000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize = 0x00001000
+NumBlocks = 0x100
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x00020000
+gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize
+FV = FVMAIN_SEC
+
+0x00020000|0x000e0000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FVMAIN_SEC]
+FvAlignment = 8
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF HisiPkg/D01BoardPkg/Sec/Sec/Sec.inf
+
+
+[FV.FvMain]
+BlockSize = 0x40
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 8 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ #INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ #INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+ INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+ #INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+ INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+ #
+ # Multiple Console IO support
+ #
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ #INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ INF EmbeddedPkg/SerialDxe/SerialDxe.inf
+
+ INF HisiPkg/Drivers/PL390Gic/PL390GicDxe.inf
+ #INF ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf
+ INF HisiPkg/Drivers/TimerDxe/TimerDxe.inf
+
+ INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+ INF HisiPkg/Drivers/WatchDogDriver/WatchDogDriver.inf
+
+ INF HisiPkg/Drivers/LinuxAtagList/LinuxAtagList.inf
+
+ #
+ # Semi-hosting filesystem
+ #
+ #INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
+
+ # RamDisk filesystem
+ INF HisiPkg/Drivers/ramdisk/ramdisk.inf
+
+ #NorFlash Driver
+ INF HisiPkg/Drivers/FlashDriver/FlashDriver.inf
+
+
+ INF HisiPkg/Drivers/NandFlash/NandFlashDxe.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ #INF FatPkg/EnhancedFatDxe/Fat.inf
+ INF RuleOverride = BINARY FatBinPkg/EnhancedFatDxe/Fat.inf
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+
+ INF HisiPkg/Drivers/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+
+ #
+ # Multimedia Card Interface
+ #
+ #INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
+ #INF ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
+
+ #
+ # network
+ #
+ INF HisiPkg/D01BoardPkg/Drivers/SnpPV600Dxe/SnpPV600Dxe.inf
+ INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ INF MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf
+ INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+ INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+ INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ INF HisiPkg/D01BoardPkg/Application/Ebl/Ebl.inf
+ INF ShellBinPkg/UefiShell/UefiShell.inf
+
+ #
+ # Bds
+ #
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF HisiPkg/D01BoardPkg/Bds/Bds.inf
+
+[FV.FVMAIN_COMPACT]
+FvAlignment = 8
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+#!if $(EDK2_SKIP_PEICORE) == 1
+ INF ArmPlatformPkg/PrePi/PeiMPCore.inf
+#!else
+# INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+# INF MdeModulePkg/Core/Pei/PeiMain.inf
+# INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+# INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+# INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+# INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+# INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+# INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+# INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+#!endif
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
+
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+# FILE DRIVER = $(NAMED_GUID) {
+# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+# COMPRESS PI_STD {
+# GUIDED {
+# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+# UI STRING="$(MODULE_NAME)" Optional
+# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+# }
+# }
+# }
+#
+############################################################################
+
+[Rule.Common.SEC]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+ TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.SEC.BINARY]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+ TE TE Align = 32 |.efi
+ }
+
+[Rule.Common.PEI_CORE]
+ FILE PEI_CORE = $(NAMED_GUID) {
+ TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING ="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM]
+ FILE PEIM = $(NAMED_GUID) {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+ FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+ }
+
+[Rule.Common.DXE_CORE]
+ FILE DXE_CORE = $(NAMED_GUID) {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+[Rule.Common.DXE_DRIVER.BINARY]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_APPLICATION]
+ FILE APPLICATION = $(NAMED_GUID) {
+ UI STRING ="$(MODULE_NAME)" Optional
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.UEFI_APPLICATION.BINARY]
+ FILE APPLICATION = $(NAMED_GUID) {
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+}
+
+[Rule.Common.USER_DEFINED]
+ FILE FREEFORM = $(NAMED_GUID) {
+ RAW ACPI Optional |.acpi
+ RAW ASL Optional |.aml
+ }
+
diff --git a/HisiPkg/D01BoardPkg/Library/D01LibRTSM/RTSM.c b/HisiPkg/D01BoardPkg/Library/D01LibRTSM/RTSM.c
index 928eafa34..3cb42acfd 100644
--- a/HisiPkg/D01BoardPkg/Library/D01LibRTSM/RTSM.c
+++ b/HisiPkg/D01BoardPkg/Library/D01LibRTSM/RTSM.c
@@ -1,212 +1,212 @@
-/** @file
-*
-* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
-* Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#include <Library/IoLib.h>
-#include <Library/ArmPlatformLib.h>
-#include <Library/DebugLib.h>
-#include <Library/PcdLib.h>
-
-#include <Ppi/ArmMpCoreInfo.h>
-
-#include <ArmPlatform.h>
-
-UINTN
-ArmGetCpuCountPerCluster (
- VOID
- );
-
-ARM_CORE_INFO mVersatileExpressMpCoreInfoTable[] = {
- {
- // Cluster 0, Core 0
- 0x0, 0x0,
-
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
- (UINT64)0xFFFFFFFF
- },
- {
- // Cluster 0, Core 1
- 0x0, 0x1,
-
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
- (UINT64)0xFFFFFFFF
- },
- {
- // Cluster 0, Core 2
- 0x0, 0x2,
-
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
- (UINT64)0xFFFFFFFF
- },
- {
- // Cluster 0, Core 3
- 0x0, 0x3,
-
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
- (UINT64)0xFFFFFFFF
- },
- {
- // Cluster 1, Core 0
- 0x1, 0x0,
-
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
- (UINT64)0xFFFFFFFF
- },
- {
- // Cluster 1, Core 1
- 0x1, 0x1,
-
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
- (UINT64)0xFFFFFFFF
- },
- {
- // Cluster 1, Core 2
- 0x1, 0x2,
-
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
- (UINT64)0xFFFFFFFF
- },
- {
- // Cluster 1, Core 3
- 0x1, 0x3,
-
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
- (UINT64)0xFFFFFFFF
- }
-};
-
-/**
- Return the current Boot Mode
-
- This function returns the boot reason on the platform
-
- @return Return the current Boot Mode of the platform
-
-**/
-EFI_BOOT_MODE
-ArmPlatformGetBootMode (
- VOID
- )
-{
- return BOOT_WITH_FULL_CONFIGURATION;
-}
-
-/**
- Initialize controllers that must setup in the normal world
-
- This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
- in the PEI phase.
-
-**/
-RETURN_STATUS
-ArmPlatformInitialize (
- IN UINTN MpId
- )
-{
- if (!(((MpId) & PcdGet32(PcdArmPrimaryCoreMask)) == PcdGet32(PcdArmPrimaryCore))) {
- return RETURN_SUCCESS;
- }
-
- // Disable memory remapping and return to normal mapping
- MmioOr32 (SP810_CTRL_BASE, BIT8);
-
- return RETURN_SUCCESS;
-}
-
-/**
- Initialize the system (or sometimes called permanent) memory
-
- This memory is generally represented by the DRAM.
-
-**/
-VOID
-ArmPlatformInitializeSystemMemory (
- VOID
- )
-{
- // Nothing to do here
-}
-
-EFI_STATUS
-PrePeiCoreGetMpCoreInfo (
- OUT UINTN *CoreCount,
- OUT ARM_CORE_INFO **ArmCoreTable
- )
-{
-#if 0
- UINT32 ProcType;
-
- ProcType = MmioRead32 (ARM_VE_SYS_PROCID0_REG) & ARM_VE_SYS_PROC_ID_MASK;
- if ((ProcType == ARM_VE_SYS_PROC_ID_CORTEX_A9) || (ProcType == ARM_VE_SYS_PROC_ID_CORTEX_A15)) {
- // Only support one cluster
- *CoreCount = ArmGetCpuCountPerCluster ();
- *ArmCoreTable = mVersatileExpressMpCoreInfoTable;
- return EFI_SUCCESS;
- } else {
- return EFI_UNSUPPORTED;
- }
-#else
-
- *CoreCount = 2 * ArmGetCpuCountPerCluster ();
- *ArmCoreTable = mVersatileExpressMpCoreInfoTable;
-
- return EFI_SUCCESS;
-#endif
-}
-
-// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
-EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;
-ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
-
-EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
- {
- EFI_PEI_PPI_DESCRIPTOR_PPI,
- &mArmMpCoreInfoPpiGuid,
- &mMpCoreInfoPpi
- }
-};
-
-VOID
-ArmPlatformGetPlatformPpiList (
- OUT UINTN *PpiListSize,
- OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
- )
-{
- *PpiListSize = sizeof(gPlatformPpiTable);
- *PpiList = gPlatformPpiTable;
-}
+/** @file
+*
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+* Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/IoLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+
+#include <Ppi/ArmMpCoreInfo.h>
+
+#include <ArmPlatform.h>
+
+UINTN
+ArmGetCpuCountPerCluster (
+ VOID
+ );
+
+ARM_CORE_INFO mVersatileExpressMpCoreInfoTable[] = {
+ {
+ // Cluster 0, Core 0
+ 0x0, 0x0,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+ (UINT64)0xFFFFFFFF
+ },
+ {
+ // Cluster 0, Core 1
+ 0x0, 0x1,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+ (UINT64)0xFFFFFFFF
+ },
+ {
+ // Cluster 0, Core 2
+ 0x0, 0x2,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+ (UINT64)0xFFFFFFFF
+ },
+ {
+ // Cluster 0, Core 3
+ 0x0, 0x3,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+ (UINT64)0xFFFFFFFF
+ },
+ {
+ // Cluster 1, Core 0
+ 0x1, 0x0,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+ (UINT64)0xFFFFFFFF
+ },
+ {
+ // Cluster 1, Core 1
+ 0x1, 0x1,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+ (UINT64)0xFFFFFFFF
+ },
+ {
+ // Cluster 1, Core 2
+ 0x1, 0x2,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+ (UINT64)0xFFFFFFFF
+ },
+ {
+ // Cluster 1, Core 3
+ 0x1, 0x3,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+ (UINT64)0xFFFFFFFF
+ }
+};
+
+/**
+ Return the current Boot Mode
+
+ This function returns the boot reason on the platform
+
+ @return Return the current Boot Mode of the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+ VOID
+ )
+{
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+ Initialize controllers that must setup in the normal world
+
+ This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
+ in the PEI phase.
+
+**/
+RETURN_STATUS
+ArmPlatformInitialize (
+ IN UINTN MpId
+ )
+{
+ if (!(((MpId) & PcdGet32(PcdArmPrimaryCoreMask)) == PcdGet32(PcdArmPrimaryCore))) {
+ return RETURN_SUCCESS;
+ }
+
+ // Disable memory remapping and return to normal mapping
+ MmioOr32 (SP810_CTRL_BASE, BIT8);
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Initialize the system (or sometimes called permanent) memory
+
+ This memory is generally represented by the DRAM.
+
+**/
+VOID
+ArmPlatformInitializeSystemMemory (
+ VOID
+ )
+{
+ // Nothing to do here
+}
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+ OUT UINTN *CoreCount,
+ OUT ARM_CORE_INFO **ArmCoreTable
+ )
+{
+#if 0
+ UINT32 ProcType;
+
+ ProcType = MmioRead32 (ARM_VE_SYS_PROCID0_REG) & ARM_VE_SYS_PROC_ID_MASK;
+ if ((ProcType == ARM_VE_SYS_PROC_ID_CORTEX_A9) || (ProcType == ARM_VE_SYS_PROC_ID_CORTEX_A15)) {
+ // Only support one cluster
+ *CoreCount = ArmGetCpuCountPerCluster ();
+ *ArmCoreTable = mVersatileExpressMpCoreInfoTable;
+ return EFI_SUCCESS;
+ } else {
+ return EFI_UNSUPPORTED;
+ }
+#else
+
+ *CoreCount = 2 * ArmGetCpuCountPerCluster ();
+ *ArmCoreTable = mVersatileExpressMpCoreInfoTable;
+
+ return EFI_SUCCESS;
+#endif
+}
+
+// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
+EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &mArmMpCoreInfoPpiGuid,
+ &mMpCoreInfoPpi
+ }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+ OUT UINTN *PpiListSize,
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
+ )
+{
+ *PpiListSize = sizeof(gPlatformPpiTable);
+ *PpiList = gPlatformPpiTable;
+}
diff --git a/HisiPkg/D01BoardPkg/Library/D01SecLibRTSM/D01SecLib.inf b/HisiPkg/D01BoardPkg/Library/D01SecLibRTSM/D01SecLib.inf
index 36926c76b..e6c96cc86 100644
--- a/HisiPkg/D01BoardPkg/Library/D01SecLibRTSM/D01SecLib.inf
+++ b/HisiPkg/D01BoardPkg/Library/D01SecLibRTSM/D01SecLib.inf
@@ -1,25 +1,25 @@
-#/* @file
-# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
-# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#*/
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = RTSMArmD01SecLib
- FILE_GUID = 1fdaabb0-ab7d-480c-91ff-428dc1546f3a
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = ArmPlatformSecLib
-
-[binaries.common]
- LIB|RTSMArmD01SecLib.lib
-
+#/* @file
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = RTSMArmD01SecLib
+ FILE_GUID = 1fdaabb0-ab7d-480c-91ff-428dc1546f3a
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformSecLib
+
+[binaries.common]
+ LIB|RTSMArmD01SecLib.lib
+
diff --git a/HisiPkg/D01BoardPkg/Sec/Sec/Sec.c b/HisiPkg/D01BoardPkg/Sec/Sec/Sec.c
index 22cf7aa8a..d66916b0f 100644
--- a/HisiPkg/D01BoardPkg/Sec/Sec/Sec.c
+++ b/HisiPkg/D01BoardPkg/Sec/Sec/Sec.c
@@ -1,198 +1,198 @@
-/** @file
-* Main file supporting the SEC Phase on ARM Platforms
-*
-* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
-* Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#include <Library/ArmTrustedMonitorLib.h>
-#include <Library/DebugAgentLib.h>
-#include <Library/PrintLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/SerialPortLib.h>
-#include <Library/ArmGicLib.h>
-
-#include "SecInternal.h"
-
-#define SerialPrint(txt) SerialPortWrite ((UINT8*)txt, AsciiStrLen(txt)+1);
-VOID
-CEntryPoint (
- IN UINTN MpId,
- IN UINTN SecBootMode
- )
-{
- CHAR8 Buffer[100];
- UINTN CharCount;
- UINTN JumpAddress;
-
- // Invalidate the data cache. Doesn't have to do the Data cache clean.
- ArmInvalidateDataCache();
-
- // Invalidate Instruction Cache
- ArmInvalidateInstructionCache();
-
- // Invalidate I & D TLBs
- ArmInvalidateInstructionAndDataTlb();
-
- // CPU specific settings
- ArmCpuSetup (MpId);
-
- // Enable Floating Point Coprocessor if supported by the platform
- if (FixedPcdGet32 (PcdVFPEnabled)) {
- ArmEnableVFP();
- }
-
- // Initialize peripherals that must be done at the early stage
- // Example: Some L2 controller, interconnect, clock, DMC, etc
- ArmPlatformSecInitialize (MpId);
-
- // Primary CPU clears out the SCU tag RAMs, secondaries wait
- if ((((MpId) & PcdGet32(PcdArmPrimaryCoreMask)) == PcdGet32(PcdArmPrimaryCore)) && (SecBootMode == ARM_SEC_COLD_BOOT)) {
- if (ArmIsMpCore()) {
- // Signal for the initial memory is configured (event: BOOT_MEM_INIT)
- ArmCallSEV ();
- }
-
- // SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib
- // In non SEC modules the init call is in autogenerated code.
- SerialPortInitialize ();
-
- // Start talking
- if (FixedPcdGetBool (PcdTrustzoneSupport)) {
- CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Secure UEFI firmware %s built at %a on %a\n\r",
- (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);
- } else {
- CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Boot firmware %s built at %a on %a\n\r",
- (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);
- }
- SerialPortWrite ((UINT8 *) Buffer, CharCount);
-
- // Initialize the Debug Agent for Source Level Debugging
- InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL);
- SaveAndSetDebugTimerInterrupt (TRUE);
-
- // Enable the GIC distributor and CPU Interface
- // - no other Interrupts are enabled, doesn't have to worry about the priority.
- // - all the cores are in secure state, use secure SGI's
- ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
- ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
- } else {
- // Enable the GIC CPU Interface
- ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
- }
-
- // Enable Full Access to CoProcessors
- ArmWriteCpacr (CPACR_CP_FULL_ACCESS);
-
- // Test if Trustzone is supported on this platform
- if (FixedPcdGetBool (PcdTrustzoneSupport)) {
- if (ArmIsMpCore()) {
- // Setup SMP in Non Secure world
- ArmCpuSetupSmpNonSecure (GET_CORE_ID(MpId));
- }
-
- // Either we use the Secure Stacks for Secure Monitor (in this case (Base == 0) && (Size == 0))
- // Or we use separate Secure Monitor stacks (but (Base != 0) && (Size != 0))
- ASSERT (((PcdGet32(PcdCPUCoresSecMonStackBase) == 0) && (PcdGet32(PcdCPUCoreSecMonStackSize) == 0)) ||
- ((PcdGet32(PcdCPUCoresSecMonStackBase) != 0) && (PcdGet32(PcdCPUCoreSecMonStackSize) != 0)));
-
- // Enter Monitor Mode
- enter_monitor_mode ((UINTN)TrustedWorldInitialization, MpId, SecBootMode, (VOID*)(PcdGet32(PcdCPUCoresSecMonStackBase) + (PcdGet32(PcdCPUCoreSecMonStackSize) * (GET_CORE_POS(MpId) + 1))));
- } else {
- if (((MpId) & PcdGet32(PcdArmPrimaryCoreMask)) == PcdGet32(PcdArmPrimaryCore)) {
- SerialPrint ("Trust Zone Configuration is disabled\n\r");
- }
-
- // With Trustzone support the transition from Sec to Normal world is done by return_from_exception().
- // If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program
- // Status Register as the the current one (CPSR).
- copy_cpsr_into_spsr ();
-
- // Call the Platform specific function to execute additional actions if required
- JumpAddress = PcdGet32 (PcdFvBaseAddress);
- ArmPlatformSecExtraAction (MpId, &JumpAddress);
-
- NonTrustedWorldTransition (MpId, JumpAddress);
- }
- ASSERT (0); // We must never return from the above function
-}
-
-VOID
-TrustedWorldInitialization (
- IN UINTN MpId,
- IN UINTN SecBootMode
- )
-{
- UINTN JumpAddress;
-
- //-------------------- Monitor Mode ---------------------
-
- // Set up Monitor World (Vector Table, etc)
- ArmSecureMonitorWorldInitialize ();
-
- // Transfer the interrupt to Non-secure World
- ArmGicSetupNonSecure (MpId, PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase));
-
- // Initialize platform specific security policy
- ArmPlatformSecTrustzoneInit (MpId);
-
- // Setup the Trustzone Chipsets
- if (SecBootMode == ARM_SEC_COLD_BOOT) {
- if (((MpId) & PcdGet32(PcdArmPrimaryCoreMask)) == PcdGet32(PcdArmPrimaryCore)) {
- if (ArmIsMpCore()) {
- // Signal the secondary core the Security settings is done (event: EVENT_SECURE_INIT)
- ArmCallSEV ();
- }
- } else {
- // The secondary cores need to wait until the Trustzone chipsets configuration is done
- // before switching to Non Secure World
-
- // Wait for the Primary Core to finish the initialization of the Secure World (event: EVENT_SECURE_INIT)
- ArmCallWFE ();
- }
- }
-
- // Call the Platform specific function to execute additional actions if required
- JumpAddress = PcdGet32 (PcdFvBaseAddress);
- ArmPlatformSecExtraAction (MpId, &JumpAddress);
-
- // Write to CP15 Non-secure Access Control Register
- ArmWriteNsacr (PcdGet32 (PcdArmNsacr));
-
- /* set SMP bit */
- ArmWriteAuxCr(ArmReadAuxCr() | BIT6);
-
- // CP15 Secure Configuration Register
- ArmWriteScr (PcdGet32 (PcdArmScr));
-
- NonTrustedWorldTransition (MpId, JumpAddress);
-}
-
-VOID
-NonTrustedWorldTransition (
- IN UINTN MpId,
- IN UINTN JumpAddress
- )
-{
- // If PcdArmNonSecModeTransition is defined then set this specific mode to CPSR before the transition
- // By not set, the mode for Non Secure World is SVC
- if (PcdGet32 (PcdArmNonSecModeTransition) != 0) {
- set_non_secure_mode ((ARM_PROCESSOR_MODE)PcdGet32 (PcdArmNonSecModeTransition));
- }
-
- return_from_exception (JumpAddress);
- //-------------------- Non Secure Mode ---------------------
-
- // PEI Core should always load and never return
- ASSERT (FALSE);
-}
-
+/** @file
+* Main file supporting the SEC Phase on ARM Platforms
+*
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+* Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmTrustedMonitorLib.h>
+#include <Library/DebugAgentLib.h>
+#include <Library/PrintLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/SerialPortLib.h>
+#include <Library/ArmGicLib.h>
+
+#include "SecInternal.h"
+
+#define SerialPrint(txt) SerialPortWrite ((UINT8*)txt, AsciiStrLen(txt)+1);
+VOID
+CEntryPoint (
+ IN UINTN MpId,
+ IN UINTN SecBootMode
+ )
+{
+ CHAR8 Buffer[100];
+ UINTN CharCount;
+ UINTN JumpAddress;
+
+ // Invalidate the data cache. Doesn't have to do the Data cache clean.
+ ArmInvalidateDataCache();
+
+ // Invalidate Instruction Cache
+ ArmInvalidateInstructionCache();
+
+ // Invalidate I & D TLBs
+ ArmInvalidateInstructionAndDataTlb();
+
+ // CPU specific settings
+ ArmCpuSetup (MpId);
+
+ // Enable Floating Point Coprocessor if supported by the platform
+ if (FixedPcdGet32 (PcdVFPEnabled)) {
+ ArmEnableVFP();
+ }
+
+ // Initialize peripherals that must be done at the early stage
+ // Example: Some L2 controller, interconnect, clock, DMC, etc
+ ArmPlatformSecInitialize (MpId);
+
+ // Primary CPU clears out the SCU tag RAMs, secondaries wait
+ if ((((MpId) & PcdGet32(PcdArmPrimaryCoreMask)) == PcdGet32(PcdArmPrimaryCore)) && (SecBootMode == ARM_SEC_COLD_BOOT)) {
+ if (ArmIsMpCore()) {
+ // Signal for the initial memory is configured (event: BOOT_MEM_INIT)
+ ArmCallSEV ();
+ }
+
+ // SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib
+ // In non SEC modules the init call is in autogenerated code.
+ SerialPortInitialize ();
+
+ // Start talking
+ if (FixedPcdGetBool (PcdTrustzoneSupport)) {
+ CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Secure UEFI firmware %s built at %a on %a\n\r",
+ (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);
+ } else {
+ CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Boot firmware %s built at %a on %a\n\r",
+ (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);
+ }
+ SerialPortWrite ((UINT8 *) Buffer, CharCount);
+
+ // Initialize the Debug Agent for Source Level Debugging
+ InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL);
+ SaveAndSetDebugTimerInterrupt (TRUE);
+
+ // Enable the GIC distributor and CPU Interface
+ // - no other Interrupts are enabled, doesn't have to worry about the priority.
+ // - all the cores are in secure state, use secure SGI's
+ ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
+ ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
+ } else {
+ // Enable the GIC CPU Interface
+ ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
+ }
+
+ // Enable Full Access to CoProcessors
+ ArmWriteCpacr (CPACR_CP_FULL_ACCESS);
+
+ // Test if Trustzone is supported on this platform
+ if (FixedPcdGetBool (PcdTrustzoneSupport)) {
+ if (ArmIsMpCore()) {
+ // Setup SMP in Non Secure world
+ ArmCpuSetupSmpNonSecure (GET_CORE_ID(MpId));
+ }
+
+ // Either we use the Secure Stacks for Secure Monitor (in this case (Base == 0) && (Size == 0))
+ // Or we use separate Secure Monitor stacks (but (Base != 0) && (Size != 0))
+ ASSERT (((PcdGet32(PcdCPUCoresSecMonStackBase) == 0) && (PcdGet32(PcdCPUCoreSecMonStackSize) == 0)) ||
+ ((PcdGet32(PcdCPUCoresSecMonStackBase) != 0) && (PcdGet32(PcdCPUCoreSecMonStackSize) != 0)));
+
+ // Enter Monitor Mode
+ enter_monitor_mode ((UINTN)TrustedWorldInitialization, MpId, SecBootMode, (VOID*)(PcdGet32(PcdCPUCoresSecMonStackBase) + (PcdGet32(PcdCPUCoreSecMonStackSize) * (GET_CORE_POS(MpId) + 1))));
+ } else {
+ if (((MpId) & PcdGet32(PcdArmPrimaryCoreMask)) == PcdGet32(PcdArmPrimaryCore)) {
+ SerialPrint ("Trust Zone Configuration is disabled\n\r");
+ }
+
+ // With Trustzone support the transition from Sec to Normal world is done by return_from_exception().
+ // If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program
+ // Status Register as the the current one (CPSR).
+ copy_cpsr_into_spsr ();
+
+ // Call the Platform specific function to execute additional actions if required
+ JumpAddress = PcdGet32 (PcdFvBaseAddress);
+ ArmPlatformSecExtraAction (MpId, &JumpAddress);
+
+ NonTrustedWorldTransition (MpId, JumpAddress);
+ }
+ ASSERT (0); // We must never return from the above function
+}
+
+VOID
+TrustedWorldInitialization (
+ IN UINTN MpId,
+ IN UINTN SecBootMode
+ )
+{
+ UINTN JumpAddress;
+
+ //-------------------- Monitor Mode ---------------------
+
+ // Set up Monitor World (Vector Table, etc)
+ ArmSecureMonitorWorldInitialize ();
+
+ // Transfer the interrupt to Non-secure World
+ ArmGicSetupNonSecure (MpId, PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase));
+
+ // Initialize platform specific security policy
+ ArmPlatformSecTrustzoneInit (MpId);
+
+ // Setup the Trustzone Chipsets
+ if (SecBootMode == ARM_SEC_COLD_BOOT) {
+ if (((MpId) & PcdGet32(PcdArmPrimaryCoreMask)) == PcdGet32(PcdArmPrimaryCore)) {
+ if (ArmIsMpCore()) {
+ // Signal the secondary core the Security settings is done (event: EVENT_SECURE_INIT)
+ ArmCallSEV ();
+ }
+ } else {
+ // The secondary cores need to wait until the Trustzone chipsets configuration is done
+ // before switching to Non Secure World
+
+ // Wait for the Primary Core to finish the initialization of the Secure World (event: EVENT_SECURE_INIT)
+ ArmCallWFE ();
+ }
+ }
+
+ // Call the Platform specific function to execute additional actions if required
+ JumpAddress = PcdGet32 (PcdFvBaseAddress);
+ ArmPlatformSecExtraAction (MpId, &JumpAddress);
+
+ // Write to CP15 Non-secure Access Control Register
+ ArmWriteNsacr (PcdGet32 (PcdArmNsacr));
+
+ /* set SMP bit */
+ ArmWriteAuxCr(ArmReadAuxCr() | BIT6);
+
+ // CP15 Secure Configuration Register
+ ArmWriteScr (PcdGet32 (PcdArmScr));
+
+ NonTrustedWorldTransition (MpId, JumpAddress);
+}
+
+VOID
+NonTrustedWorldTransition (
+ IN UINTN MpId,
+ IN UINTN JumpAddress
+ )
+{
+ // If PcdArmNonSecModeTransition is defined then set this specific mode to CPSR before the transition
+ // By not set, the mode for Non Secure World is SVC
+ if (PcdGet32 (PcdArmNonSecModeTransition) != 0) {
+ set_non_secure_mode ((ARM_PROCESSOR_MODE)PcdGet32 (PcdArmNonSecModeTransition));
+ }
+
+ return_from_exception (JumpAddress);
+ //-------------------- Non Secure Mode ---------------------
+
+ // PEI Core should always load and never return
+ ASSERT (FALSE);
+}
+
diff --git a/HisiPkg/Drivers/PL390Gic/PL390GicDxe.c b/HisiPkg/Drivers/PL390Gic/PL390GicDxe.c
index ada262d7d..cd653a944 100644
--- a/HisiPkg/Drivers/PL390Gic/PL390GicDxe.c
+++ b/HisiPkg/Drivers/PL390Gic/PL390GicDxe.c
@@ -1,425 +1,425 @@
-/*++
-
-Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>
-Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>
-Portions copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
-Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
-
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-Module Name:
-
- Gic.c
-
-Abstract:
-
- Driver implementing the GIC interrupt controller protocol
-
---*/
-
-#include <PiDxe.h>
-
-#include <Library/BaseLib.h>
-#include <Library/DebugLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/UefiLib.h>
-#include <Library/PcdLib.h>
-#include <Library/IoLib.h>
-#include <Library/ArmGicLib.h>
-
-#include <Protocol/Cpu.h>
-#include <Protocol/HardwareInterrupt.h>
-
-#define ARM_GIC_DEFAULT_PRIORITY 0x80
-
-extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol;
-
-//
-// Notifications
-//
-EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
-
-// Maximum Number of Interrupts
-UINTN mGicNumInterrupts = 0;
-
-HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers = NULL;
-
-/**
- Register Handler for the specified interrupt source.
-
- @param This Instance pointer for this protocol
- @param Source Hardware source of the interrupt
- @param Handler Callback for interrupt. NULL to unregister
-
- @retval EFI_SUCCESS Source was updated to support Handler.
- @retval EFI_DEVICE_ERROR Hardware could not be programmed.
-
-**/
-EFI_STATUS
-EFIAPI
-RegisterInterruptSource (
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
- IN HARDWARE_INTERRUPT_SOURCE Source,
- IN HARDWARE_INTERRUPT_HANDLER Handler
- )
-{
- if (Source > mGicNumInterrupts) {
- ASSERT(FALSE);
- return EFI_UNSUPPORTED;
- }
-
- if ((Handler == NULL) && (gRegisteredInterruptHandlers[Source] == NULL)) {
- return EFI_INVALID_PARAMETER;
- }
-
- if ((Handler != NULL) && (gRegisteredInterruptHandlers[Source] != NULL)) {
- return EFI_ALREADY_STARTED;
- }
-
- gRegisteredInterruptHandlers[Source] = Handler;
-
- // If the interrupt handler is unregistered then disable the interrupt
- if (NULL == Handler){
- return This->DisableInterruptSource (This, Source);
- } else {
- return This->EnableInterruptSource (This, Source);
- }
-}
-
-/**
- Enable interrupt source Source.
-
- @param This Instance pointer for this protocol
- @param Source Hardware source of the interrupt
-
- @retval EFI_SUCCESS Source interrupt enabled.
- @retval EFI_DEVICE_ERROR Hardware could not be programmed.
-
-**/
-EFI_STATUS
-EFIAPI
-EnableInterruptSource (
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
- IN HARDWARE_INTERRUPT_SOURCE Source
- )
-{
- UINT32 RegOffset;
- UINTN RegShift;
-
- if (Source > mGicNumInterrupts) {
- ASSERT(FALSE);
- return EFI_UNSUPPORTED;
- }
-
- // calculate enable register offset and bit position
- RegOffset = Source / 32;
- RegShift = Source % 32;
-
- // write set-enable register
- MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset), 1 << RegShift);
-
- return EFI_SUCCESS;
-}
-
-/**
- Disable interrupt source Source.
-
- @param This Instance pointer for this protocol
- @param Source Hardware source of the interrupt
-
- @retval EFI_SUCCESS Source interrupt disabled.
- @retval EFI_DEVICE_ERROR Hardware could not be programmed.
-
-**/
-EFI_STATUS
-EFIAPI
-DisableInterruptSource (
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
- IN HARDWARE_INTERRUPT_SOURCE Source
- )
-{
- UINT32 RegOffset;
- UINTN RegShift;
-
- if (Source > mGicNumInterrupts) {
- ASSERT(FALSE);
- return EFI_UNSUPPORTED;
- }
-
- // Calculate enable register offset and bit position
- RegOffset = Source / 32;
- RegShift = Source % 32;
-
- // Write set-enable register
- MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDICER + (4*RegOffset), 1 << RegShift);
-
- return EFI_SUCCESS;
-}
-
-/**
- Return current state of interrupt source Source.
-
- @param This Instance pointer for this protocol
- @param Source Hardware source of the interrupt
- @param InterruptState TRUE: source enabled, FALSE: source disabled.
-
- @retval EFI_SUCCESS InterruptState is valid
- @retval EFI_DEVICE_ERROR InterruptState is not valid
-
-**/
-EFI_STATUS
-EFIAPI
-GetInterruptSourceState (
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
- IN HARDWARE_INTERRUPT_SOURCE Source,
- IN BOOLEAN *InterruptState
- )
-{
- UINT32 RegOffset;
- UINTN RegShift;
-
- if (Source > mGicNumInterrupts) {
- ASSERT(FALSE);
- return EFI_UNSUPPORTED;
- }
-
- // calculate enable register offset and bit position
- RegOffset = Source / 32;
- RegShift = Source % 32;
-
- if ((MmioRead32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset)) & (1<<RegShift)) == 0) {
- *InterruptState = FALSE;
- } else {
- *InterruptState = TRUE;
- }
-
- return EFI_SUCCESS;
-}
-
-/**
- Signal to the hardware that the End Of Intrrupt state
- has been reached.
-
- @param This Instance pointer for this protocol
- @param Source Hardware source of the interrupt
-
- @retval EFI_SUCCESS Source interrupt EOI'ed.
- @retval EFI_DEVICE_ERROR Hardware could not be programmed.
-
-**/
-EFI_STATUS
-EFIAPI
-EndOfInterrupt (
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
- IN HARDWARE_INTERRUPT_SOURCE Source
- )
-{
- if (Source > mGicNumInterrupts) {
- ASSERT(FALSE);
- return EFI_UNSUPPORTED;
- }
-
- MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCEIOR, Source);
- return EFI_SUCCESS;
-}
-
-/**
- EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.
-
- @param InterruptType Defines the type of interrupt or exception that
- occurred on the processor.This parameter is processor architecture specific.
- @param SystemContext A pointer to the processor context when
- the interrupt occurred on the processor.
-
- @return None
-
-**/
-VOID
-EFIAPI
-IrqInterruptHandler (
- IN EFI_EXCEPTION_TYPE InterruptType,
- IN EFI_SYSTEM_CONTEXT SystemContext
- )
-{
- UINT32 GicInterrupt;
- HARDWARE_INTERRUPT_HANDLER InterruptHandler;
-
- GicInterrupt = MmioRead32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCIAR);
-
- // Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the number of interrupt (ie: Spurious interrupt).
- if (GicInterrupt >= mGicNumInterrupts) {
- // The special interrupt do not need to be acknowledge
- return;
- }
-
- InterruptHandler = gRegisteredInterruptHandlers[GicInterrupt];
- if (InterruptHandler != NULL) {
- // Call the registered interrupt handler.
- InterruptHandler (GicInterrupt, SystemContext);
- } else {
- DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));
- }
-
- EndOfInterrupt (&gHardwareInterruptProtocol, GicInterrupt);
-}
-
-//
-// Making this global saves a few bytes in image size
-//
-EFI_HANDLE gHardwareInterruptHandle = NULL;
-
-//
-// The protocol instance produced by this driver
-//
-EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol = {
- RegisterInterruptSource,
- EnableInterruptSource,
- DisableInterruptSource,
- GetInterruptSourceState,
- EndOfInterrupt
-};
-
-/**
- Shutdown our hardware
-
- DXE Core will disable interrupts and turn off the timer and disable interrupts
- after all the event handlers have run.
-
- @param[in] Event The Event that is being processed
- @param[in] Context Event Context
-**/
-VOID
-EFIAPI
-ExitBootServicesEvent (
- IN EFI_EVENT Event,
- IN VOID *Context
- )
-{
- UINTN Index;
-
- // Acknowledge all pending interrupts
- for (Index = 0; Index < mGicNumInterrupts; Index++) {
- DisableInterruptSource (&gHardwareInterruptProtocol, Index);
- }
-
- for (Index = 0; Index < mGicNumInterrupts; Index++) {
- EndOfInterrupt (&gHardwareInterruptProtocol, Index);
- }
-
- // Disable Gic Interface
- MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x0);
- MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0x0);
-
- // Disable Gic Distributor
- MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x0);
-}
-
-/**
- Initialize the state information for the CPU Architectural Protocol
-
- @param ImageHandle of the loaded driver
- @param SystemTable Pointer to the System Table
-
- @retval EFI_SUCCESS Protocol registered
- @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
- @retval EFI_DEVICE_ERROR Hardware problems
-
-**/
-EFI_STATUS
-InterruptDxeInitialize (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
- )
-{
- EFI_STATUS Status;
- UINTN Index;
- UINT32 RegOffset;
- UINTN RegShift;
- EFI_CPU_ARCH_PROTOCOL *Cpu;
- UINT32 CpuTarget;
-
- // Check PcdGicPrimaryCoreId has been set in case the Primary Core is not the core 0 of Cluster 0
- DEBUG_CODE_BEGIN();
- if ((PcdGet32(PcdArmPrimaryCore) != 0) && (PcdGet32 (PcdGicPrimaryCoreId) == 0)) {
- DEBUG((EFI_D_WARN,"Warning: the PCD PcdGicPrimaryCoreId does not seem to be set up for the configuration.\n"));
- }
- DEBUG_CODE_END();
-
- // Make sure the Interrupt Controller Protocol is not already installed in the system.
- ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
-
- mGicNumInterrupts = ArmGicGetMaxNumInterrupts (PcdGet32(PcdGicDistributorBase));
-
- for (Index = 0; Index < mGicNumInterrupts; Index++) {
- DisableInterruptSource (&gHardwareInterruptProtocol, Index);
-
- // Set Priority
- RegOffset = Index / 4;
- RegShift = (Index % 4) * 8;
- MmioAndThenOr32 (
- PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPR + (4*RegOffset),
- ~(0xff << RegShift),
- ARM_GIC_DEFAULT_PRIORITY << RegShift
- );
- }
- // Configure interrupts for Primary Cpu
- CpuTarget = (1 << PcdGet32 (PcdGicPrimaryCoreId));
- CpuTarget |= CpuTarget << 16;
- for (Index = 0; Index < (mGicNumInterrupts / 2); Index++) {
- MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index*4), CpuTarget);
- }
-
- // Set binary point reg to 0x7 (no preemption)
- MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCBPR, 0x7);
-
- // Set priority mask reg to 0xff to allow all priorities through
- MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0xff);
-
- // Enable gic cpu interface
- MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x1);
-
- // Enable gic distributor
- MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x1);
-
- // Initialize the array for the Interrupt Handlers
- gRegisteredInterruptHandlers = (HARDWARE_INTERRUPT_HANDLER*)AllocateZeroPool (sizeof(HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts);
-
- Status = gBS->InstallMultipleProtocolInterfaces (
- &gHardwareInterruptHandle,
- &gHardwareInterruptProtocolGuid, &gHardwareInterruptProtocol,
- NULL
- );
- ASSERT_EFI_ERROR (Status);
-
- //
- // Get the CPU protocol that this driver requires.
- //
- Status = gBS->LocateProtocol(&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);
- ASSERT_EFI_ERROR(Status);
-
- //
- // Unregister the default exception handler.
- //
- Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, NULL);
- ASSERT_EFI_ERROR(Status);
-
- //
- // Register to receive interrupts
- //
- Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, IrqInterruptHandler);
- ASSERT_EFI_ERROR(Status);
-
- // Register for an ExitBootServicesEvent
- Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);
- ASSERT_EFI_ERROR (Status);
-
- return Status;
-}
+/*++
+
+Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>
+Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>
+Portions copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
+Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ Gic.c
+
+Abstract:
+
+ Driver implementing the GIC interrupt controller protocol
+
+--*/
+
+#include <PiDxe.h>
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/ArmGicLib.h>
+
+#include <Protocol/Cpu.h>
+#include <Protocol/HardwareInterrupt.h>
+
+#define ARM_GIC_DEFAULT_PRIORITY 0x80
+
+extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol;
+
+//
+// Notifications
+//
+EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
+
+// Maximum Number of Interrupts
+UINTN mGicNumInterrupts = 0;
+
+HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers = NULL;
+
+/**
+ Register Handler for the specified interrupt source.
+
+ @param This Instance pointer for this protocol
+ @param Source Hardware source of the interrupt
+ @param Handler Callback for interrupt. NULL to unregister
+
+ @retval EFI_SUCCESS Source was updated to support Handler.
+ @retval EFI_DEVICE_ERROR Hardware could not be programmed.
+
+**/
+EFI_STATUS
+EFIAPI
+RegisterInterruptSource (
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source,
+ IN HARDWARE_INTERRUPT_HANDLER Handler
+ )
+{
+ if (Source > mGicNumInterrupts) {
+ ASSERT(FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ if ((Handler == NULL) && (gRegisteredInterruptHandlers[Source] == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((Handler != NULL) && (gRegisteredInterruptHandlers[Source] != NULL)) {
+ return EFI_ALREADY_STARTED;
+ }
+
+ gRegisteredInterruptHandlers[Source] = Handler;
+
+ // If the interrupt handler is unregistered then disable the interrupt
+ if (NULL == Handler){
+ return This->DisableInterruptSource (This, Source);
+ } else {
+ return This->EnableInterruptSource (This, Source);
+ }
+}
+
+/**
+ Enable interrupt source Source.
+
+ @param This Instance pointer for this protocol
+ @param Source Hardware source of the interrupt
+
+ @retval EFI_SUCCESS Source interrupt enabled.
+ @retval EFI_DEVICE_ERROR Hardware could not be programmed.
+
+**/
+EFI_STATUS
+EFIAPI
+EnableInterruptSource (
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source
+ )
+{
+ UINT32 RegOffset;
+ UINTN RegShift;
+
+ if (Source > mGicNumInterrupts) {
+ ASSERT(FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ // calculate enable register offset and bit position
+ RegOffset = Source / 32;
+ RegShift = Source % 32;
+
+ // write set-enable register
+ MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset), 1 << RegShift);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Disable interrupt source Source.
+
+ @param This Instance pointer for this protocol
+ @param Source Hardware source of the interrupt
+
+ @retval EFI_SUCCESS Source interrupt disabled.
+ @retval EFI_DEVICE_ERROR Hardware could not be programmed.
+
+**/
+EFI_STATUS
+EFIAPI
+DisableInterruptSource (
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source
+ )
+{
+ UINT32 RegOffset;
+ UINTN RegShift;
+
+ if (Source > mGicNumInterrupts) {
+ ASSERT(FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ // Calculate enable register offset and bit position
+ RegOffset = Source / 32;
+ RegShift = Source % 32;
+
+ // Write set-enable register
+ MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDICER + (4*RegOffset), 1 << RegShift);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Return current state of interrupt source Source.
+
+ @param This Instance pointer for this protocol
+ @param Source Hardware source of the interrupt
+ @param InterruptState TRUE: source enabled, FALSE: source disabled.
+
+ @retval EFI_SUCCESS InterruptState is valid
+ @retval EFI_DEVICE_ERROR InterruptState is not valid
+
+**/
+EFI_STATUS
+EFIAPI
+GetInterruptSourceState (
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source,
+ IN BOOLEAN *InterruptState
+ )
+{
+ UINT32 RegOffset;
+ UINTN RegShift;
+
+ if (Source > mGicNumInterrupts) {
+ ASSERT(FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ // calculate enable register offset and bit position
+ RegOffset = Source / 32;
+ RegShift = Source % 32;
+
+ if ((MmioRead32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset)) & (1<<RegShift)) == 0) {
+ *InterruptState = FALSE;
+ } else {
+ *InterruptState = TRUE;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Signal to the hardware that the End Of Intrrupt state
+ has been reached.
+
+ @param This Instance pointer for this protocol
+ @param Source Hardware source of the interrupt
+
+ @retval EFI_SUCCESS Source interrupt EOI'ed.
+ @retval EFI_DEVICE_ERROR Hardware could not be programmed.
+
+**/
+EFI_STATUS
+EFIAPI
+EndOfInterrupt (
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source
+ )
+{
+ if (Source > mGicNumInterrupts) {
+ ASSERT(FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCEIOR, Source);
+ return EFI_SUCCESS;
+}
+
+/**
+ EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.
+
+ @param InterruptType Defines the type of interrupt or exception that
+ occurred on the processor.This parameter is processor architecture specific.
+ @param SystemContext A pointer to the processor context when
+ the interrupt occurred on the processor.
+
+ @return None
+
+**/
+VOID
+EFIAPI
+IrqInterruptHandler (
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
+ )
+{
+ UINT32 GicInterrupt;
+ HARDWARE_INTERRUPT_HANDLER InterruptHandler;
+
+ GicInterrupt = MmioRead32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCIAR);
+
+ // Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the number of interrupt (ie: Spurious interrupt).
+ if (GicInterrupt >= mGicNumInterrupts) {
+ // The special interrupt do not need to be acknowledge
+ return;
+ }
+
+ InterruptHandler = gRegisteredInterruptHandlers[GicInterrupt];
+ if (InterruptHandler != NULL) {
+ // Call the registered interrupt handler.
+ InterruptHandler (GicInterrupt, SystemContext);
+ } else {
+ DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));
+ }
+
+ EndOfInterrupt (&gHardwareInterruptProtocol, GicInterrupt);
+}
+
+//
+// Making this global saves a few bytes in image size
+//
+EFI_HANDLE gHardwareInterruptHandle = NULL;
+
+//
+// The protocol instance produced by this driver
+//
+EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol = {
+ RegisterInterruptSource,
+ EnableInterruptSource,
+ DisableInterruptSource,
+ GetInterruptSourceState,
+ EndOfInterrupt
+};
+
+/**
+ Shutdown our hardware
+
+ DXE Core will disable interrupts and turn off the timer and disable interrupts
+ after all the event handlers have run.
+
+ @param[in] Event The Event that is being processed
+ @param[in] Context Event Context
+**/
+VOID
+EFIAPI
+ExitBootServicesEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ UINTN Index;
+
+ // Acknowledge all pending interrupts
+ for (Index = 0; Index < mGicNumInterrupts; Index++) {
+ DisableInterruptSource (&gHardwareInterruptProtocol, Index);
+ }
+
+ for (Index = 0; Index < mGicNumInterrupts; Index++) {
+ EndOfInterrupt (&gHardwareInterruptProtocol, Index);
+ }
+
+ // Disable Gic Interface
+ MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x0);
+ MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0x0);
+
+ // Disable Gic Distributor
+ MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x0);
+}
+
+/**
+ Initialize the state information for the CPU Architectural Protocol
+
+ @param ImageHandle of the loaded driver
+ @param SystemTable Pointer to the System Table
+
+ @retval EFI_SUCCESS Protocol registered
+ @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
+ @retval EFI_DEVICE_ERROR Hardware problems
+
+**/
+EFI_STATUS
+InterruptDxeInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ UINTN Index;
+ UINT32 RegOffset;
+ UINTN RegShift;
+ EFI_CPU_ARCH_PROTOCOL *Cpu;
+ UINT32 CpuTarget;
+
+ // Check PcdGicPrimaryCoreId has been set in case the Primary Core is not the core 0 of Cluster 0
+ DEBUG_CODE_BEGIN();
+ if ((PcdGet32(PcdArmPrimaryCore) != 0) && (PcdGet32 (PcdGicPrimaryCoreId) == 0)) {
+ DEBUG((EFI_D_WARN,"Warning: the PCD PcdGicPrimaryCoreId does not seem to be set up for the configuration.\n"));
+ }
+ DEBUG_CODE_END();
+
+ // Make sure the Interrupt Controller Protocol is not already installed in the system.
+ ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
+
+ mGicNumInterrupts = ArmGicGetMaxNumInterrupts (PcdGet32(PcdGicDistributorBase));
+
+ for (Index = 0; Index < mGicNumInterrupts; Index++) {
+ DisableInterruptSource (&gHardwareInterruptProtocol, Index);
+
+ // Set Priority
+ RegOffset = Index / 4;
+ RegShift = (Index % 4) * 8;
+ MmioAndThenOr32 (
+ PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPR + (4*RegOffset),
+ ~(0xff << RegShift),
+ ARM_GIC_DEFAULT_PRIORITY << RegShift
+ );
+ }
+ // Configure interrupts for Primary Cpu
+ CpuTarget = (1 << PcdGet32 (PcdGicPrimaryCoreId));
+ CpuTarget |= CpuTarget << 16;
+ for (Index = 0; Index < (mGicNumInterrupts / 2); Index++) {
+ MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index*4), CpuTarget);
+ }
+
+ // Set binary point reg to 0x7 (no preemption)
+ MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCBPR, 0x7);
+
+ // Set priority mask reg to 0xff to allow all priorities through
+ MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0xff);
+
+ // Enable gic cpu interface
+ MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x1);
+
+ // Enable gic distributor
+ MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x1);
+
+ // Initialize the array for the Interrupt Handlers
+ gRegisteredInterruptHandlers = (HARDWARE_INTERRUPT_HANDLER*)AllocateZeroPool (sizeof(HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts);
+
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &gHardwareInterruptHandle,
+ &gHardwareInterruptProtocolGuid, &gHardwareInterruptProtocol,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Get the CPU protocol that this driver requires.
+ //
+ Status = gBS->LocateProtocol(&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);
+ ASSERT_EFI_ERROR(Status);
+
+ //
+ // Unregister the default exception handler.
+ //
+ Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, NULL);
+ ASSERT_EFI_ERROR(Status);
+
+ //
+ // Register to receive interrupts
+ //
+ Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, IrqInterruptHandler);
+ ASSERT_EFI_ERROR(Status);
+
+ // Register for an ExitBootServicesEvent
+ Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
diff --git a/HisiPkg/Drivers/PL390Gic/PL390GicDxe.inf b/HisiPkg/Drivers/PL390Gic/PL390GicDxe.inf
index 3dcd7863c..1f2d3990e 100644
--- a/HisiPkg/Drivers/PL390Gic/PL390GicDxe.inf
+++ b/HisiPkg/Drivers/PL390Gic/PL390GicDxe.inf
@@ -1,59 +1,59 @@
-#/** @file
-#
-# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-# Copyright (c) 2012, ARM Ltd. All rights reserved.<BR>
-# Copyright Huawei Technologies Co., Ltd. 1998-2013. All rights reserved.
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = PL390GicDxe
- FILE_GUID = DE371F7C-DEC4-4D21-ADF1-593ABCC15882
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
-
- ENTRY_POINT = InterruptDxeInitialize
-
-
-[Sources.common]
- PL390Gic.c
- PL390GicDxe.c
-
-[Packages]
- MdePkg/MdePkg.dec
- EmbeddedPkg/EmbeddedPkg.dec
- ArmPkg/ArmPkg.dec
- HisiPkg/HisiPlatformPkg.dec
-
-[LibraryClasses]
- BaseLib
- UefiLib
- UefiBootServicesTableLib
- DebugLib
- PrintLib
- MemoryAllocationLib
- UefiDriverEntryPoint
- IoLib
-
-[Protocols]
- gHardwareInterruptProtocolGuid
- gEfiCpuArchProtocolGuid
-
-[FixedPcd.common]
- gArmTokenSpaceGuid.PcdGicDistributorBase
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
-
- gArmTokenSpaceGuid.PcdArmPrimaryCore
- gHwTokenSpaceGuid.PcdGicPrimaryCoreId
-
-[Depex]
- gEfiCpuArchProtocolGuid
+#/** @file
+#
+# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+# Copyright (c) 2012, ARM Ltd. All rights reserved.<BR>
+# Copyright Huawei Technologies Co., Ltd. 1998-2013. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PL390GicDxe
+ FILE_GUID = DE371F7C-DEC4-4D21-ADF1-593ABCC15882
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = InterruptDxeInitialize
+
+
+[Sources.common]
+ PL390Gic.c
+ PL390GicDxe.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPkg/ArmPkg.dec
+ HisiPkg/HisiPlatformPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ UefiLib
+ UefiBootServicesTableLib
+ DebugLib
+ PrintLib
+ MemoryAllocationLib
+ UefiDriverEntryPoint
+ IoLib
+
+[Protocols]
+ gHardwareInterruptProtocolGuid
+ gEfiCpuArchProtocolGuid
+
+[FixedPcd.common]
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
+ gHwTokenSpaceGuid.PcdGicPrimaryCoreId
+
+[Depex]
+ gEfiCpuArchProtocolGuid
diff --git a/HisiPkg/Drivers/TimerDxe/TimerDxe.c b/HisiPkg/Drivers/TimerDxe/TimerDxe.c
index fd482f460..a95a6d006 100644
--- a/HisiPkg/Drivers/TimerDxe/TimerDxe.c
+++ b/HisiPkg/Drivers/TimerDxe/TimerDxe.c
@@ -1,557 +1,557 @@
-/** @file
- Timer Architecture Protocol driver of the ARM flavor
-
- Copyright (c) 2011 ARM Ltd. All rights reserved.<BR>
- Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
-
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-
-#include <PiDxe.h>
-
-#include <Library/ArmLib.h>
-#include <Library/BaseLib.h>
-#include <Library/DebugLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/UefiLib.h>
-#include <Library/PcdLib.h>
-#include <Library/IoLib.h>
-#include <Library/ArmArchTimerLib.h>
-
-#include <Protocol/Timer.h>
-#include <Protocol/HardwareInterrupt.h>
-
-// The notification function to call on every timer interrupt.
-EFI_TIMER_NOTIFY mTimerNotifyFunction = (EFI_TIMER_NOTIFY)NULL;
-EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
-
-// The current period of the timer interrupt
-UINT64 mTimerPeriod = 0;
-
-// Cached copy of the Hardware Interrupt protocol instance
-EFI_HARDWARE_INTERRUPT_PROTOCOL *gInterrupt = NULL;
-
-#define SRE_HITIMER_ADDR 0xe3000000
-
-#define SRE_HITIMER32_OFFSET (0x00000020)
-
-/****************** Timer32 register addresses offset start ***********************/
-#define SRE_HITIMER32_LOAD_OFFSET (0x0)
-#define SRE_HITIMER32_VALUE_OFFSET (0x4)
-#define SRE_HITIMER32_CNTL_OFFSET (0x8)
-#define SRE_HITIMER32_INTC_OFFSET (0xC)
-#define SRE_HITIMER32_RIS_OFFSET (0x10)
-#define SRE_HITIMER32_MIS_OFFSET (0x0014)
-#define SRE_HITIMER32_BGLOAD_OFFSET (0x18)
-/****************** end ******************************/
-
-#define SRE_HITIMER_NUM 48
-#define SRE_HITIMER64_START_INDEX 32
-#define SRE_HITIMER_ENCLK_SEL_BIT (1 << 7) /* Timer enable flag */
-
-
-#define SRE_HITIMER_CLK_IN_FREQ 187500000
-#define SRE_HITIMER_MICROSECOND_PER_SECOND 1000000
-
-#define SRE_HITIMER_DEFAULT_TICKS 100
-#define SRE_HITIMER_RELOAD_TICKS 1
-
-#define SRE_HITIMER_INT_CLEAR (0x01)
-#define SRE_HITIMER_CNTL_ENABLE (0x80)
-#define SRE_HITIMER_CNTL_MODE (0x40)
-#define SRE_HITIMER_CNTL_IRQ_ENABLE (0x20)
-#define SRE_HITIMER_CNTL_SIZEMODE (0x2)
-
-
-#define SRE_HITIMER_CNTL_MODE_ONCE 0
-#define SRE_HITIMER_CNTL_MODE_CYCLE 1
-#define SRE_HITIMER_CNTL_IRQ_ON 1
-#define SRE_HITIMER_CNTL_IRQ_OFF 0
-
-
-#define SRE_D01_HITIMER01_INTVEC (256)
-#define SRE_D01_HITIMER23_INTVEC (257)
-#define SRE_D01_HITIMER45_INTVEC (258)
-#define SRE_D01_HITIMER67_INTVEC (259)
-#define SRE_D01_HITIMER89_INTVEC (260)
-#define SRE_D01_HITIMER1011_INTVEC (261)
-#define SRE_D01_HITIMER1213_INTVEC (262)
-#define SRE_D01_HITIMER1415_INTVEC (263)
-#define SRE_D01_HITIMER1617_INTVEC (264)
-#define SRE_D01_HITIMER1819_INTVEC (265)
-#define SRE_D01_HITIMER2021_INTVEC (266)
-#define SRE_D01_HITIMER2223_INTVEC (267)
-#define SRE_D01_HITIMER2425_INTVEC (268)
-#define SRE_D01_HITIMER2627_INTVEC (269)
-#define SRE_D01_HITIMER2829_INTVEC (270)
-#define SRE_D01_HITIMER3031_INTVEC (271)
-#define SRE_D01_HITIMER3233_INTVEC (272)
-#define SRE_D01_HITIMER3435_INTVEC (273)
-#define SRE_D01_HITIMER3637_INTVEC (274)
-#define SRE_D01_HITIMER3839_INTVEC (275)
-#define SRE_D01_HITIMER4041_INTVEC (276)
-#define SRE_D01_HITIMER4243_INTVEC (277)
-#define SRE_D01_HITIMER4445_INTVEC (278)
-#define SRE_D01_HITIMER4647_INTVEC (279)
-
-UINT32 gRegBase = SRE_HITIMER_ADDR;
-#define SC_CTRL 0xe3e00000
-
-void HITIMER_Start()
-{
- UINT32 ulRegAddr;
- UINT32 ulVal = 0;
- UINT32 ulMask;
-
- ulVal = *(UINT32*)SC_CTRL;
- ulVal |= BIT17 | BIT16 | BIT18 | BIT19;
- *(UINT32*)SC_CTRL = ulVal;
-
- /*timer mode*/
- ulMask = SRE_HITIMER_CNTL_MODE; //BIT6
- ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET;
- ulVal = *(UINT32*)ulRegAddr;
- ulVal = ulVal;
- ulVal |= ulMask; /*cycle*/
- *(UINT32*)ulRegAddr = ulVal;
-
- /*int mode*/
- ulMask = SRE_HITIMER_CNTL_IRQ_ENABLE; //BIT5
- ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET;
- ulVal = *(UINT32*)ulRegAddr;
- ulVal = ulVal;
- ulVal |= ulMask;
- //DEBUG((EFI_D_ERROR, "int mode = %0x at %0x\n", ulVal, ulRegAddr));
- *(UINT32*)ulRegAddr = ulVal;
-
- /*start up*/
- ulMask = (SRE_HITIMER_ENCLK_SEL_BIT | SRE_HITIMER_CNTL_SIZEMODE); //BIT7 | BIT1
- ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET;
- ulVal = *(UINT32*)ulRegAddr;
- ulVal = ulVal;
- ulVal |= ulMask;
- //DEBUG((EFI_D_ERROR, "start up = %0x at %0x\n", ulVal, ulRegAddr));
- *(UINT32*)ulRegAddr = ulVal;
-
-}
-
-void HITMER_ClearInt()
-{
- UINT32 ulRegAddr;
- UINT32 ulVal = 0;
-
-
- ulRegAddr = gRegBase + SRE_HITIMER32_INTC_OFFSET;
- ulVal = SRE_HITIMER_INT_CLEAR;
- //DEBUG((EFI_D_ERROR, "HITMER_ClearInt = %0x at %0x\n", ulVal, ulRegAddr));
- *(UINT32*)ulRegAddr = ulVal;
-
-}
-
-void DisableTimer()
-{
- UINT32 ulRegAddr;
- UINT32 ulVal = 0;
- UINT32 ulMask;
-
- /*disable*/
- ulMask = SRE_HITIMER_ENCLK_SEL_BIT;
- ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET;
- ulVal = *(UINT32*)ulRegAddr;
- ulVal = ulVal;
- ulVal &= (~ulMask);
- //DEBUG((EFI_D_ERROR, "DisableTimer = %0x at %0x\n", ulVal, ulRegAddr));
- *(UINT32*)ulRegAddr = ulVal;
-
-}
-
-void EnableTimer()
-{
- UINT32 ulRegAddr;
- UINT32 ulVal = 1;
- UINT32 ulMask;
-
- /*disable*/
- ulMask = SRE_HITIMER_ENCLK_SEL_BIT;
- ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET;
- ulVal = *(UINT32*)ulRegAddr;
- ulVal = ulVal;
- ulVal |= ulMask;
- //DEBUG((EFI_D_ERROR, "EnableTimer = %0x at %0x\n", ulVal, ulRegAddr));
- *(UINT32*)ulRegAddr = ulVal;
-
-}
-
-/**
- This function registers the handler NotifyFunction so it is called every time
- the timer interrupt fires. It also passes the amount of time since the last
- handler call to the NotifyFunction. If NotifyFunction is NULL, then the
- handler is unregistered. If the handler is registered, then EFI_SUCCESS is
- returned. If the CPU does not support registering a timer interrupt handler,
- then EFI_UNSUPPORTED is returned. If an attempt is made to register a handler
- when a handler is already registered, then EFI_ALREADY_STARTED is returned.
- If an attempt is made to unregister a handler when a handler is not registered,
- then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to
- register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR
- is returned.
-
- @param This The EFI_TIMER_ARCH_PROTOCOL instance.
- @param NotifyFunction The function to call when a timer interrupt fires. This
- function executes at TPL_HIGH_LEVEL. The DXE Core will
- register a handler for the timer interrupt, so it can know
- how much time has passed. This information is used to
- signal timer based events. NULL will unregister the handler.
- @retval EFI_SUCCESS The timer handler was registered.
- @retval EFI_UNSUPPORTED The platform does not support timer interrupts.
- @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already
- registered.
- @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not
- previously registered.
- @retval EFI_DEVICE_ERROR The timer handler could not be registered.
-
-**/
-EFI_STATUS
-EFIAPI
-TimerDriverRegisterHandler (
- IN EFI_TIMER_ARCH_PROTOCOL *This,
- IN EFI_TIMER_NOTIFY NotifyFunction
- )
-{
- if ((NotifyFunction == NULL) && (mTimerNotifyFunction == NULL)) {
- return EFI_INVALID_PARAMETER;
- }
-
- if ((NotifyFunction != NULL) && (mTimerNotifyFunction != NULL)) {
- return EFI_ALREADY_STARTED;
- }
-
- mTimerNotifyFunction = NotifyFunction;
-
- return EFI_SUCCESS;
-}
-
-/**
- Disable the timer
-**/
-VOID
-EFIAPI
-ExitBootServicesEvent (
- IN EFI_EVENT Event,
- IN VOID *Context
- )
-{
- DisableTimer ();
-}
-
-/**
-
- This function adjusts the period of timer interrupts to the value specified
- by TimerPeriod. If the timer period is updated, then the selected timer
- period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If
- the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
- If an error occurs while attempting to update the timer period, then the
- timer hardware will be put back in its state prior to this call, and
- EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt
- is disabled. This is not the same as disabling the CPU's interrupts.
- Instead, it must either turn off the timer hardware, or it must adjust the
- interrupt controller so that a CPU interrupt is not generated when the timer
- interrupt fires.
-
- @param This The EFI_TIMER_ARCH_PROTOCOL instance.
- @param TimerPeriod The rate to program the timer interrupt in 100 nS units. If
- the timer hardware is not programmable, then EFI_UNSUPPORTED is
- returned. If the timer is programmable, then the timer period
- will be rounded up to the nearest timer period that is supported
- by the timer hardware. If TimerPeriod is set to 0, then the
- timer interrupts will be disabled.
-
-
- @retval EFI_SUCCESS The timer period was changed.
- @retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt.
- @retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error.
-
-**/
-EFI_STATUS
-EFIAPI
-TimerDriverSetTimerPeriod (
- IN EFI_TIMER_ARCH_PROTOCOL *This,
- IN UINT64 TimerPeriod
- )
-{
- UINT64 TimerTicks;
-
- UINT32 ulRegAddr;
-
- // always disable the timer
- DisableTimer ();
-
- if (TimerPeriod != 0) {
- // Convert TimerPeriod to micro sec units
- #if 0
- TimerTicks = DivU64x32 (TimerPeriod, 10);
-
- TimerTicks = MultU64x32 (TimerTicks, (PcdGet32(PcdArmArchTimerFreqInHz)/1000000));
- #endif
-
- TimerTicks = DivU64x32 (TimerPeriod, 100);
- TimerTicks = MultU64x32 (TimerTicks, (PcdGet32(PcdArmArchTimerFreqInHz)/100000));
-
- //ArmArchTimerSetTimerVal((UINTN)TimerTicks);
-
- ulRegAddr = gRegBase + SRE_HITIMER32_LOAD_OFFSET;
- //DEBUG((EFI_D_ERROR, "TimerTicks1 = %0x at %0x ======\n", TimerTicks, ulRegAddr));
- *(UINT32*)ulRegAddr = TimerTicks;
- ulRegAddr = gRegBase + SRE_HITIMER32_BGLOAD_OFFSET;
- //DEBUG((EFI_D_ERROR, "TimerTicks2 = %0x at %0x \n", TimerTicks, ulRegAddr));
- *(UINT32*)ulRegAddr = TimerTicks;
-
- // Enable the timer
- EnableTimer ();
- }
-
- // Save the new timer period
- mTimerPeriod = TimerPeriod;
- return EFI_SUCCESS;
-}
-
-/**
- This function retrieves the period of timer interrupts in 100 ns units,
- returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod
- is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is
- returned, then the timer is currently disabled.
-
- @param This The EFI_TIMER_ARCH_PROTOCOL instance.
- @param TimerPeriod A pointer to the timer period to retrieve in 100 ns units. If
- 0 is returned, then the timer is currently disabled.
-
-
- @retval EFI_SUCCESS The timer period was returned in TimerPeriod.
- @retval EFI_INVALID_PARAMETER TimerPeriod is NULL.
-
-**/
-EFI_STATUS
-EFIAPI
-TimerDriverGetTimerPeriod (
- IN EFI_TIMER_ARCH_PROTOCOL *This,
- OUT UINT64 *TimerPeriod
- )
-{
- if (TimerPeriod == NULL) {
- return EFI_INVALID_PARAMETER;
- }
-
- *TimerPeriod = mTimerPeriod;
- return EFI_SUCCESS;
-}
-
-/**
- This function generates a soft timer interrupt. If the platform does not support soft
- timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned.
- If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler()
- service, then a soft timer interrupt will be generated. If the timer interrupt is
- enabled when this service is called, then the registered handler will be invoked. The
- registered handler should not be able to distinguish a hardware-generated timer
- interrupt from a software-generated timer interrupt.
-
- @param This The EFI_TIMER_ARCH_PROTOCOL instance.
-
- @retval EFI_SUCCESS The soft timer interrupt was generated.
- @retval EFI_UNSUPPORTED The platform does not support the generation of soft timer interrupts.
-
-**/
-EFI_STATUS
-EFIAPI
-TimerDriverGenerateSoftInterrupt (
- IN EFI_TIMER_ARCH_PROTOCOL *This
- )
-{
- return EFI_UNSUPPORTED;
-}
-
-/**
- Interface structure for the Timer Architectural Protocol.
-
- @par Protocol Description:
- This protocol provides the services to initialize a periodic timer
- interrupt, and to register a handler that is called each time the timer
- interrupt fires. It may also provide a service to adjust the rate of the
- periodic timer interrupt. When a timer interrupt occurs, the handler is
- passed the amount of time that has passed since the previous timer
- interrupt.
-
- @param RegisterHandler
- Registers a handler that will be called each time the
- timer interrupt fires. TimerPeriod defines the minimum
- time between timer interrupts, so TimerPeriod will also
- be the minimum time between calls to the registered
- handler.
-
- @param SetTimerPeriod
- Sets the period of the timer interrupt in 100 nS units.
- This function is optional, and may return EFI_UNSUPPORTED.
- If this function is supported, then the timer period will
- be rounded up to the nearest supported timer period.
-
-
- @param GetTimerPeriod
- Retrieves the period of the timer interrupt in 100 nS units.
-
- @param GenerateSoftInterrupt
- Generates a soft timer interrupt that simulates the firing of
- the timer interrupt. This service can be used to invoke the registered handler if the timer interrupt has been masked for
- a period of time.
-
-**/
-EFI_TIMER_ARCH_PROTOCOL gTimer = {
- TimerDriverRegisterHandler,
- TimerDriverSetTimerPeriod,
- TimerDriverGetTimerPeriod,
- TimerDriverGenerateSoftInterrupt
-};
-
-/**
-
- C Interrupt Handler called in the interrupt context when Source interrupt is active.
-
-
- @param Source Source of the interrupt. Hardware routing off a specific platform defines
- what source means.
-
- @param SystemContext Pointer to system register context. Mostly used by debuggers and will
- update the system context after the return from the interrupt if
- modified. Don't change these values unless you know what you are doing
-
-**/
-VOID
-EFIAPI
-TimerInterruptHandler (
- IN HARDWARE_INTERRUPT_SOURCE Source,
- IN EFI_SYSTEM_CONTEXT SystemContext
- )
-{
- EFI_TPL OriginalTPL;
-
- //
- // DXE core uses this callback for the EFI timer tick. The DXE core uses locks
- // that raise to TPL_HIGH and then restore back to current level. Thus we need
- // to make sure TPL level is set to TPL_HIGH while we are handling the timer tick.
- //
- //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
- OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
- //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
-
- // Check if the timer interrupt is active
- //if ((*(UINT32*)(gRegBase + SRE_HITIMER32_RIS_OFFSET)) & BIT0) {
- //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
- HITMER_ClearInt();
-
- // Signal end of interrupt early to help avoid losing subsequent ticks from long duration handlers
- gInterrupt->EndOfInterrupt (gInterrupt, Source);
-
-
- if (mTimerNotifyFunction) {
- mTimerNotifyFunction (mTimerPeriod);
- }
-
- // Reload the Timer
- //TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32(PcdTimerPeriod));
- //}
- //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
-
- //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
-
- // Enable timer interrupts
- //gInterrupt->EnableInterruptSource (gInterrupt, Source);
- //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
-
- gBS->RestoreTPL (OriginalTPL);
-}
-
-
-
-
-/**
- Initialize the state information for the Timer Architectural Protocol and
- the Timer Debug support protocol that allows the debugger to break into a
- running program.
-
- @param ImageHandle of the loaded driver
- @param SystemTable Pointer to the System Table
-
- @retval EFI_SUCCESS Protocol registered
- @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
- @retval EFI_DEVICE_ERROR Hardware problems
-
-**/
-EFI_STATUS
-EFIAPI
-TimerInitialize (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
- )
-{
- EFI_HANDLE Handle = NULL;
- EFI_STATUS Status;
-
-
- // Find the interrupt controller protocol. ASSERT if not found.
- Status = gBS->LocateProtocol (&gHardwareInterruptProtocolGuid, NULL, (VOID **)&gInterrupt);
- ASSERT_EFI_ERROR (Status);
- //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
-
- // Disable the timer
- Status = TimerDriverSetTimerPeriod (&gTimer, 0);
- ASSERT_EFI_ERROR (Status);
-
- //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
- // Install secure and Non-secure interrupt handlers
- // Note: Because it is not possible to determine the security state of the
- // CPU dynamically, we just install interrupt handler for both sec and non-sec
- // timer PPI
- Status = gInterrupt->RegisterInterruptSource (gInterrupt, 256, TimerInterruptHandler);
- ASSERT_EFI_ERROR (Status);
-
- //Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32 (PcdArmArchTimerIntrNum), TimerInterruptHandler);
- //ASSERT_EFI_ERROR (Status);
-
- //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
- // Unmask timer interrupts
- HITIMER_Start();
-
- //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
-
- // Set up default timer
- Status = TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32(PcdTimerPeriod)); // TIMER_DEFAULT_PERIOD
- ASSERT_EFI_ERROR (Status);
- //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
-
- // Install the Timer Architectural Protocol onto a new handle
- Status = gBS->InstallMultipleProtocolInterfaces(
- &Handle,
- &gEfiTimerArchProtocolGuid, &gTimer,
- NULL
- );
- ASSERT_EFI_ERROR(Status);
- //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
-
- // enable Secure timer interrupts
- Status = gInterrupt->EnableInterruptSource (gInterrupt, 256);
-
- // enable NonSecure timer interrupts
- //Status = gInterrupt->EnableInterruptSource (gInterrupt, PcdGet32 (PcdArmArchTimerIntrNum));
-
- // Register for an ExitBootServicesEvent
- Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);
- ASSERT_EFI_ERROR (Status);
-
- return Status;
-}
+/** @file
+ Timer Architecture Protocol driver of the ARM flavor
+
+ Copyright (c) 2011 ARM Ltd. All rights reserved.<BR>
+ Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+#include <PiDxe.h>
+
+#include <Library/ArmLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/ArmArchTimerLib.h>
+
+#include <Protocol/Timer.h>
+#include <Protocol/HardwareInterrupt.h>
+
+// The notification function to call on every timer interrupt.
+EFI_TIMER_NOTIFY mTimerNotifyFunction = (EFI_TIMER_NOTIFY)NULL;
+EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
+
+// The current period of the timer interrupt
+UINT64 mTimerPeriod = 0;
+
+// Cached copy of the Hardware Interrupt protocol instance
+EFI_HARDWARE_INTERRUPT_PROTOCOL *gInterrupt = NULL;
+
+#define SRE_HITIMER_ADDR 0xe3000000
+
+#define SRE_HITIMER32_OFFSET (0x00000020)
+
+/****************** Timer32 register addresses offset start ***********************/
+#define SRE_HITIMER32_LOAD_OFFSET (0x0)
+#define SRE_HITIMER32_VALUE_OFFSET (0x4)
+#define SRE_HITIMER32_CNTL_OFFSET (0x8)
+#define SRE_HITIMER32_INTC_OFFSET (0xC)
+#define SRE_HITIMER32_RIS_OFFSET (0x10)
+#define SRE_HITIMER32_MIS_OFFSET (0x0014)
+#define SRE_HITIMER32_BGLOAD_OFFSET (0x18)
+/****************** end ******************************/
+
+#define SRE_HITIMER_NUM 48
+#define SRE_HITIMER64_START_INDEX 32
+#define SRE_HITIMER_ENCLK_SEL_BIT (1 << 7) /* Timer enable flag */
+
+
+#define SRE_HITIMER_CLK_IN_FREQ 187500000
+#define SRE_HITIMER_MICROSECOND_PER_SECOND 1000000
+
+#define SRE_HITIMER_DEFAULT_TICKS 100
+#define SRE_HITIMER_RELOAD_TICKS 1
+
+#define SRE_HITIMER_INT_CLEAR (0x01)
+#define SRE_HITIMER_CNTL_ENABLE (0x80)
+#define SRE_HITIMER_CNTL_MODE (0x40)
+#define SRE_HITIMER_CNTL_IRQ_ENABLE (0x20)
+#define SRE_HITIMER_CNTL_SIZEMODE (0x2)
+
+
+#define SRE_HITIMER_CNTL_MODE_ONCE 0
+#define SRE_HITIMER_CNTL_MODE_CYCLE 1
+#define SRE_HITIMER_CNTL_IRQ_ON 1
+#define SRE_HITIMER_CNTL_IRQ_OFF 0
+
+
+#define SRE_D01_HITIMER01_INTVEC (256)
+#define SRE_D01_HITIMER23_INTVEC (257)
+#define SRE_D01_HITIMER45_INTVEC (258)
+#define SRE_D01_HITIMER67_INTVEC (259)
+#define SRE_D01_HITIMER89_INTVEC (260)
+#define SRE_D01_HITIMER1011_INTVEC (261)
+#define SRE_D01_HITIMER1213_INTVEC (262)
+#define SRE_D01_HITIMER1415_INTVEC (263)
+#define SRE_D01_HITIMER1617_INTVEC (264)
+#define SRE_D01_HITIMER1819_INTVEC (265)
+#define SRE_D01_HITIMER2021_INTVEC (266)
+#define SRE_D01_HITIMER2223_INTVEC (267)
+#define SRE_D01_HITIMER2425_INTVEC (268)
+#define SRE_D01_HITIMER2627_INTVEC (269)
+#define SRE_D01_HITIMER2829_INTVEC (270)
+#define SRE_D01_HITIMER3031_INTVEC (271)
+#define SRE_D01_HITIMER3233_INTVEC (272)
+#define SRE_D01_HITIMER3435_INTVEC (273)
+#define SRE_D01_HITIMER3637_INTVEC (274)
+#define SRE_D01_HITIMER3839_INTVEC (275)
+#define SRE_D01_HITIMER4041_INTVEC (276)
+#define SRE_D01_HITIMER4243_INTVEC (277)
+#define SRE_D01_HITIMER4445_INTVEC (278)
+#define SRE_D01_HITIMER4647_INTVEC (279)
+
+UINT32 gRegBase = SRE_HITIMER_ADDR;
+#define SC_CTRL 0xe3e00000
+
+void HITIMER_Start()
+{
+ UINT32 ulRegAddr;
+ UINT32 ulVal = 0;
+ UINT32 ulMask;
+
+ ulVal = *(UINT32*)SC_CTRL;
+ ulVal |= BIT17 | BIT16 | BIT18 | BIT19;
+ *(UINT32*)SC_CTRL = ulVal;
+
+ /*timer mode*/
+ ulMask = SRE_HITIMER_CNTL_MODE; //BIT6
+ ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET;
+ ulVal = *(UINT32*)ulRegAddr;
+ ulVal = ulVal;
+ ulVal |= ulMask; /*cycle*/
+ *(UINT32*)ulRegAddr = ulVal;
+
+ /*int mode*/
+ ulMask = SRE_HITIMER_CNTL_IRQ_ENABLE; //BIT5
+ ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET;
+ ulVal = *(UINT32*)ulRegAddr;
+ ulVal = ulVal;
+ ulVal |= ulMask;
+ //DEBUG((EFI_D_ERROR, "int mode = %0x at %0x\n", ulVal, ulRegAddr));
+ *(UINT32*)ulRegAddr = ulVal;
+
+ /*start up*/
+ ulMask = (SRE_HITIMER_ENCLK_SEL_BIT | SRE_HITIMER_CNTL_SIZEMODE); //BIT7 | BIT1
+ ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET;
+ ulVal = *(UINT32*)ulRegAddr;
+ ulVal = ulVal;
+ ulVal |= ulMask;
+ //DEBUG((EFI_D_ERROR, "start up = %0x at %0x\n", ulVal, ulRegAddr));
+ *(UINT32*)ulRegAddr = ulVal;
+
+}
+
+void HITMER_ClearInt()
+{
+ UINT32 ulRegAddr;
+ UINT32 ulVal = 0;
+
+
+ ulRegAddr = gRegBase + SRE_HITIMER32_INTC_OFFSET;
+ ulVal = SRE_HITIMER_INT_CLEAR;
+ //DEBUG((EFI_D_ERROR, "HITMER_ClearInt = %0x at %0x\n", ulVal, ulRegAddr));
+ *(UINT32*)ulRegAddr = ulVal;
+
+}
+
+void DisableTimer()
+{
+ UINT32 ulRegAddr;
+ UINT32 ulVal = 0;
+ UINT32 ulMask;
+
+ /*disable*/
+ ulMask = SRE_HITIMER_ENCLK_SEL_BIT;
+ ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET;
+ ulVal = *(UINT32*)ulRegAddr;
+ ulVal = ulVal;
+ ulVal &= (~ulMask);
+ //DEBUG((EFI_D_ERROR, "DisableTimer = %0x at %0x\n", ulVal, ulRegAddr));
+ *(UINT32*)ulRegAddr = ulVal;
+
+}
+
+void EnableTimer()
+{
+ UINT32 ulRegAddr;
+ UINT32 ulVal = 1;
+ UINT32 ulMask;
+
+ /*disable*/
+ ulMask = SRE_HITIMER_ENCLK_SEL_BIT;
+ ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET;
+ ulVal = *(UINT32*)ulRegAddr;
+ ulVal = ulVal;
+ ulVal |= ulMask;
+ //DEBUG((EFI_D_ERROR, "EnableTimer = %0x at %0x\n", ulVal, ulRegAddr));
+ *(UINT32*)ulRegAddr = ulVal;
+
+}
+
+/**
+ This function registers the handler NotifyFunction so it is called every time
+ the timer interrupt fires. It also passes the amount of time since the last
+ handler call to the NotifyFunction. If NotifyFunction is NULL, then the
+ handler is unregistered. If the handler is registered, then EFI_SUCCESS is
+ returned. If the CPU does not support registering a timer interrupt handler,
+ then EFI_UNSUPPORTED is returned. If an attempt is made to register a handler
+ when a handler is already registered, then EFI_ALREADY_STARTED is returned.
+ If an attempt is made to unregister a handler when a handler is not registered,
+ then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to
+ register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR
+ is returned.
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param NotifyFunction The function to call when a timer interrupt fires. This
+ function executes at TPL_HIGH_LEVEL. The DXE Core will
+ register a handler for the timer interrupt, so it can know
+ how much time has passed. This information is used to
+ signal timer based events. NULL will unregister the handler.
+ @retval EFI_SUCCESS The timer handler was registered.
+ @retval EFI_UNSUPPORTED The platform does not support timer interrupts.
+ @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already
+ registered.
+ @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not
+ previously registered.
+ @retval EFI_DEVICE_ERROR The timer handler could not be registered.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverRegisterHandler (
+ IN EFI_TIMER_ARCH_PROTOCOL *This,
+ IN EFI_TIMER_NOTIFY NotifyFunction
+ )
+{
+ if ((NotifyFunction == NULL) && (mTimerNotifyFunction == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((NotifyFunction != NULL) && (mTimerNotifyFunction != NULL)) {
+ return EFI_ALREADY_STARTED;
+ }
+
+ mTimerNotifyFunction = NotifyFunction;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Disable the timer
+**/
+VOID
+EFIAPI
+ExitBootServicesEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ DisableTimer ();
+}
+
+/**
+
+ This function adjusts the period of timer interrupts to the value specified
+ by TimerPeriod. If the timer period is updated, then the selected timer
+ period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If
+ the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
+ If an error occurs while attempting to update the timer period, then the
+ timer hardware will be put back in its state prior to this call, and
+ EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt
+ is disabled. This is not the same as disabling the CPU's interrupts.
+ Instead, it must either turn off the timer hardware, or it must adjust the
+ interrupt controller so that a CPU interrupt is not generated when the timer
+ interrupt fires.
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param TimerPeriod The rate to program the timer interrupt in 100 nS units. If
+ the timer hardware is not programmable, then EFI_UNSUPPORTED is
+ returned. If the timer is programmable, then the timer period
+ will be rounded up to the nearest timer period that is supported
+ by the timer hardware. If TimerPeriod is set to 0, then the
+ timer interrupts will be disabled.
+
+
+ @retval EFI_SUCCESS The timer period was changed.
+ @retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt.
+ @retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverSetTimerPeriod (
+ IN EFI_TIMER_ARCH_PROTOCOL *This,
+ IN UINT64 TimerPeriod
+ )
+{
+ UINT64 TimerTicks;
+
+ UINT32 ulRegAddr;
+
+ // always disable the timer
+ DisableTimer ();
+
+ if (TimerPeriod != 0) {
+ // Convert TimerPeriod to micro sec units
+ #if 0
+ TimerTicks = DivU64x32 (TimerPeriod, 10);
+
+ TimerTicks = MultU64x32 (TimerTicks, (PcdGet32(PcdArmArchTimerFreqInHz)/1000000));
+ #endif
+
+ TimerTicks = DivU64x32 (TimerPeriod, 100);
+ TimerTicks = MultU64x32 (TimerTicks, (PcdGet32(PcdArmArchTimerFreqInHz)/100000));
+
+ //ArmArchTimerSetTimerVal((UINTN)TimerTicks);
+
+ ulRegAddr = gRegBase + SRE_HITIMER32_LOAD_OFFSET;
+ //DEBUG((EFI_D_ERROR, "TimerTicks1 = %0x at %0x ======\n", TimerTicks, ulRegAddr));
+ *(UINT32*)ulRegAddr = TimerTicks;
+ ulRegAddr = gRegBase + SRE_HITIMER32_BGLOAD_OFFSET;
+ //DEBUG((EFI_D_ERROR, "TimerTicks2 = %0x at %0x \n", TimerTicks, ulRegAddr));
+ *(UINT32*)ulRegAddr = TimerTicks;
+
+ // Enable the timer
+ EnableTimer ();
+ }
+
+ // Save the new timer period
+ mTimerPeriod = TimerPeriod;
+ return EFI_SUCCESS;
+}
+
+/**
+ This function retrieves the period of timer interrupts in 100 ns units,
+ returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod
+ is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is
+ returned, then the timer is currently disabled.
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param TimerPeriod A pointer to the timer period to retrieve in 100 ns units. If
+ 0 is returned, then the timer is currently disabled.
+
+
+ @retval EFI_SUCCESS The timer period was returned in TimerPeriod.
+ @retval EFI_INVALID_PARAMETER TimerPeriod is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverGetTimerPeriod (
+ IN EFI_TIMER_ARCH_PROTOCOL *This,
+ OUT UINT64 *TimerPeriod
+ )
+{
+ if (TimerPeriod == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *TimerPeriod = mTimerPeriod;
+ return EFI_SUCCESS;
+}
+
+/**
+ This function generates a soft timer interrupt. If the platform does not support soft
+ timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned.
+ If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler()
+ service, then a soft timer interrupt will be generated. If the timer interrupt is
+ enabled when this service is called, then the registered handler will be invoked. The
+ registered handler should not be able to distinguish a hardware-generated timer
+ interrupt from a software-generated timer interrupt.
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+
+ @retval EFI_SUCCESS The soft timer interrupt was generated.
+ @retval EFI_UNSUPPORTED The platform does not support the generation of soft timer interrupts.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverGenerateSoftInterrupt (
+ IN EFI_TIMER_ARCH_PROTOCOL *This
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Interface structure for the Timer Architectural Protocol.
+
+ @par Protocol Description:
+ This protocol provides the services to initialize a periodic timer
+ interrupt, and to register a handler that is called each time the timer
+ interrupt fires. It may also provide a service to adjust the rate of the
+ periodic timer interrupt. When a timer interrupt occurs, the handler is
+ passed the amount of time that has passed since the previous timer
+ interrupt.
+
+ @param RegisterHandler
+ Registers a handler that will be called each time the
+ timer interrupt fires. TimerPeriod defines the minimum
+ time between timer interrupts, so TimerPeriod will also
+ be the minimum time between calls to the registered
+ handler.
+
+ @param SetTimerPeriod
+ Sets the period of the timer interrupt in 100 nS units.
+ This function is optional, and may return EFI_UNSUPPORTED.
+ If this function is supported, then the timer period will
+ be rounded up to the nearest supported timer period.
+
+
+ @param GetTimerPeriod
+ Retrieves the period of the timer interrupt in 100 nS units.
+
+ @param GenerateSoftInterrupt
+ Generates a soft timer interrupt that simulates the firing of
+ the timer interrupt. This service can be used to invoke the registered handler if the timer interrupt has been masked for
+ a period of time.
+
+**/
+EFI_TIMER_ARCH_PROTOCOL gTimer = {
+ TimerDriverRegisterHandler,
+ TimerDriverSetTimerPeriod,
+ TimerDriverGetTimerPeriod,
+ TimerDriverGenerateSoftInterrupt
+};
+
+/**
+
+ C Interrupt Handler called in the interrupt context when Source interrupt is active.
+
+
+ @param Source Source of the interrupt. Hardware routing off a specific platform defines
+ what source means.
+
+ @param SystemContext Pointer to system register context. Mostly used by debuggers and will
+ update the system context after the return from the interrupt if
+ modified. Don't change these values unless you know what you are doing
+
+**/
+VOID
+EFIAPI
+TimerInterruptHandler (
+ IN HARDWARE_INTERRUPT_SOURCE Source,
+ IN EFI_SYSTEM_CONTEXT SystemContext
+ )
+{
+ EFI_TPL OriginalTPL;
+
+ //
+ // DXE core uses this callback for the EFI timer tick. The DXE core uses locks
+ // that raise to TPL_HIGH and then restore back to current level. Thus we need
+ // to make sure TPL level is set to TPL_HIGH while we are handling the timer tick.
+ //
+ //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
+ OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
+ //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
+
+ // Check if the timer interrupt is active
+ //if ((*(UINT32*)(gRegBase + SRE_HITIMER32_RIS_OFFSET)) & BIT0) {
+ //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
+ HITMER_ClearInt();
+
+ // Signal end of interrupt early to help avoid losing subsequent ticks from long duration handlers
+ gInterrupt->EndOfInterrupt (gInterrupt, Source);
+
+
+ if (mTimerNotifyFunction) {
+ mTimerNotifyFunction (mTimerPeriod);
+ }
+
+ // Reload the Timer
+ //TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32(PcdTimerPeriod));
+ //}
+ //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
+
+ //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
+
+ // Enable timer interrupts
+ //gInterrupt->EnableInterruptSource (gInterrupt, Source);
+ //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
+
+ gBS->RestoreTPL (OriginalTPL);
+}
+
+
+
+
+/**
+ Initialize the state information for the Timer Architectural Protocol and
+ the Timer Debug support protocol that allows the debugger to break into a
+ running program.
+
+ @param ImageHandle of the loaded driver
+ @param SystemTable Pointer to the System Table
+
+ @retval EFI_SUCCESS Protocol registered
+ @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
+ @retval EFI_DEVICE_ERROR Hardware problems
+
+**/
+EFI_STATUS
+EFIAPI
+TimerInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_HANDLE Handle = NULL;
+ EFI_STATUS Status;
+
+
+ // Find the interrupt controller protocol. ASSERT if not found.
+ Status = gBS->LocateProtocol (&gHardwareInterruptProtocolGuid, NULL, (VOID **)&gInterrupt);
+ ASSERT_EFI_ERROR (Status);
+ //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
+
+ // Disable the timer
+ Status = TimerDriverSetTimerPeriod (&gTimer, 0);
+ ASSERT_EFI_ERROR (Status);
+
+ //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
+ // Install secure and Non-secure interrupt handlers
+ // Note: Because it is not possible to determine the security state of the
+ // CPU dynamically, we just install interrupt handler for both sec and non-sec
+ // timer PPI
+ Status = gInterrupt->RegisterInterruptSource (gInterrupt, 256, TimerInterruptHandler);
+ ASSERT_EFI_ERROR (Status);
+
+ //Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32 (PcdArmArchTimerIntrNum), TimerInterruptHandler);
+ //ASSERT_EFI_ERROR (Status);
+
+ //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
+ // Unmask timer interrupts
+ HITIMER_Start();
+
+ //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
+
+ // Set up default timer
+ Status = TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32(PcdTimerPeriod)); // TIMER_DEFAULT_PERIOD
+ ASSERT_EFI_ERROR (Status);
+ //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
+
+ // Install the Timer Architectural Protocol onto a new handle
+ Status = gBS->InstallMultipleProtocolInterfaces(
+ &Handle,
+ &gEfiTimerArchProtocolGuid, &gTimer,
+ NULL
+ );
+ ASSERT_EFI_ERROR(Status);
+ //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
+
+ // enable Secure timer interrupts
+ Status = gInterrupt->EnableInterruptSource (gInterrupt, 256);
+
+ // enable NonSecure timer interrupts
+ //Status = gInterrupt->EnableInterruptSource (gInterrupt, PcdGet32 (PcdArmArchTimerIntrNum));
+
+ // Register for an ExitBootServicesEvent
+ Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
diff --git a/HisiPkg/Drivers/TimerDxe/TimerDxe.inf b/HisiPkg/Drivers/TimerDxe/TimerDxe.inf
index 3ccb746ca..6dd90ecd2 100644
--- a/HisiPkg/Drivers/TimerDxe/TimerDxe.inf
+++ b/HisiPkg/Drivers/TimerDxe/TimerDxe.inf
@@ -1,60 +1,60 @@
-#/** @file
-#
-# Component description file for Timer DXE module
-#
-# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
-# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = ArmTimerDxe
- FILE_GUID = 49ea041e-6752-42ca-b0b1-7344fe2546b7
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
-
- ENTRY_POINT = TimerInitialize
-
-[Sources.common]
- TimerDxe.c
-
-[Packages]
- MdePkg/MdePkg.dec
- EmbeddedPkg/EmbeddedPkg.dec
- ArmPkg/ArmPkg.dec
- ArmPlatformPkg/ArmPlatformPkg.dec
-
-[LibraryClasses]
- ArmLib
- BaseLib
- UefiRuntimeServicesTableLib
- UefiLib
- UefiBootServicesTableLib
- BaseMemoryLib
- DebugLib
- UefiDriverEntryPoint
- IoLib
-
-[Guids]
-
-[Protocols]
- gEfiTimerArchProtocolGuid
- gHardwareInterruptProtocolGuid
-
-[Pcd.common]
- gEmbeddedTokenSpaceGuid.PcdTimerPeriod
- gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
- gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
- gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
-
-[Depex]
- gHardwareInterruptProtocolGuid
+#/** @file
+#
+# Component description file for Timer DXE module
+#
+# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ArmTimerDxe
+ FILE_GUID = 49ea041e-6752-42ca-b0b1-7344fe2546b7
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = TimerInitialize
+
+[Sources.common]
+ TimerDxe.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+
+[LibraryClasses]
+ ArmLib
+ BaseLib
+ UefiRuntimeServicesTableLib
+ UefiLib
+ UefiBootServicesTableLib
+ BaseMemoryLib
+ DebugLib
+ UefiDriverEntryPoint
+ IoLib
+
+[Guids]
+
+[Protocols]
+ gEfiTimerArchProtocolGuid
+ gHardwareInterruptProtocolGuid
+
+[Pcd.common]
+ gEmbeddedTokenSpaceGuid.PcdTimerPeriod
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
+
+[Depex]
+ gHardwareInterruptProtocolGuid
\ No newline at end of file
diff --git a/HisiPkg/Include/Library/EblProvisionLib.h b/HisiPkg/Include/Library/EblProvisionLib.h
index 6838b7436..8dcc7ba18 100644
--- a/HisiPkg/Include/Library/EblProvisionLib.h
+++ b/HisiPkg/Include/Library/EblProvisionLib.h
@@ -19,7 +19,7 @@
#include <Library/UefiBootServicesTableLib.h>
#include <Library/DebugLib.h>
#include <Uefi/UefiBaseType.h>
-#include <Protocol/SimpleFileSystem.h>
+#include <Protocol/SimpleFileSystem.h>
#include <Protocol/SimpleNetwork.h>
typedef struct {
@@ -34,26 +34,26 @@ LibOpenRoot (
);
EFI_STATUS
-EditHIInputStr (
- IN OUT CHAR16 *CmdLine,
- IN UINTN MaxCmdLine
+EditHIInputStr (
+ IN OUT CHAR16 *CmdLine,
+ IN UINTN MaxCmdLine
);
-EFI_STATUS
-EditHIInputAscii (
- IN OUT CHAR8 *CmdLine,
- IN UINTN MaxCmdLine
+EFI_STATUS
+EditHIInputAscii (
+ IN OUT CHAR8 *CmdLine,
+ IN UINTN MaxCmdLine
);
-EFI_STATUS
-GetHIInputAscii (
- IN OUT CHAR8 *CmdLine,
- IN UINTN MaxCmdLine
+EFI_STATUS
+GetHIInputAscii (
+ IN OUT CHAR8 *CmdLine,
+ IN UINTN MaxCmdLine
);
EFI_STATUS
-GetHIInputInteger (
- OUT UINTN *Integer
+GetHIInputInteger (
+ OUT UINTN *Integer
);
#endif
diff --git a/HisiPkg/Include/Library/Std.h b/HisiPkg/Include/Library/Std.h
index 17c692658..60648477c 100644
--- a/HisiPkg/Include/Library/Std.h
+++ b/HisiPkg/Include/Library/Std.h
@@ -126,8 +126,8 @@ typedef volatile unsigned long VUWORD;
(REG_READ((offset), (data))); \
}while(0)
#ifndef MEM_MMU_OFFSET
-//#define MEM_MMU_OFFSET 0x80000000
-#define MEM_MMU_OFFSET 0x00
+//#define MEM_MMU_OFFSET 0x80000000
+#define MEM_MMU_OFFSET 0x00
#endif
#define NELEMENTS(array) (sizeof (array) / sizeof ((array) [0]))
diff --git a/HisiPkg/Include/Library/config.h b/HisiPkg/Include/Library/config.h
index 171932ce6..7f53d02f7 100644
--- a/HisiPkg/Include/Library/config.h
+++ b/HisiPkg/Include/Library/config.h
@@ -1,438 +1,438 @@
-/* config.h - Mistral OMAP35xx configuration header */
-
-/*
- * Copyright (c) 2008-2009 Wind River Systems, Inc.
- * Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
- *
- * The right to copy, distribute, modify or otherwise make use
- * of this software may be licensed only pursuant to the terms
- * of an applicable Wind River license agreement.
- */
-
-/*
-modification history
---------------------
-01f,25mar09,m_h add support for copyback cache & RTP
-01e,19mar09,m_h Cache is writethrough not copyback
-01d,19feb09,m_h cleanup
-01c,22jan09,m_h OneNand Flash Support
-01b,24nov08,m_h Configure to add networking
-01a,16jun08,m_h created.
-*/
-
-/*
-DESCRIPTION
-This module contains the configuration parameters for the Mistral OMAP35xx BSP.
-*/
-
-#ifndef __INCconfigh
-#define __INCconfigh
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* BSP version/revision identification, before configAll.h */
-
-#define BSP_VER_1_1 1 /* 1.2 is backwards compatible with 1.1 */
-#define BSP_VER_1_2 1
-#define BSP_VERSION "2.0"
-#define BSP_REV "/0" /* 0 for first revision */
-
-//#include <configAll.h>
-/*
- * vxbus support
- */
-#ifdef _BSP_BUILD_VXWORKS
-#define INCLUDE_VXBUS
-#else
-#undef INCLUDE_VXBUS
-#endif
-#ifdef INCLUDE_VXBUS
-#define INCLUDE_HWMEM_ALLOC
-#define INCLUDE_VXB_CMDLINE
-
-#define HWMEM_POOL_SIZE 50000
-
-#endif /* INCLUDE_VXBUS */
-
-/*
- * SYS_MODEL define
- *
- */
-
-#define SYS_MODEL "HISILICON - CortexA9 (ARM)"
-
-
-/* Support network devices */
-#define INCLUDE_NET_DAEMON
-#undef INCLUDE_APPL_LOG_UTIL
-#undef INCLUDE_END2_LINKBUFPOOL
-
-#define DEFAULT_BOOT_LINE \
- "HiFE(0,0)OMC:vxWorks.bin h=192.168.0.200 e=192.168.0.100 u=aa pw=123"
-
-
-
-#ifndef HDF_MASTER_CORE_FLAG
-#define HDF_MASTER_CORE_FLAG 0
-#define HDF_SLAVE_CORE_FLAG 1
-#define HDF_BOOTROM_COMPILE_FLAG 0
-#define HDF_VXWORKS_COMPILE_FLAG 1
-#endif
-
-
-
-
-
-/* Memory configuration */
-#undef LOCAL_MEM_AUTOSIZE /* run-time memory sizing */
-
-#ifndef _BSP_BUILD_VXWORKS
-#ifdef _CONTROL_SLAVE_CORE_IMG
-#define USER_RESERVED_MEM HDF_GetMemPoolResSizeConfig(HDF_SLAVE_CORE_FLAG,HDF_BOOTROM_COMPILE_FLAG)
-#else
-#define USER_RESERVED_MEM HDF_GetMemPoolResSizeConfig(HDF_MASTER_CORE_FLAG,HDF_BOOTROM_COMPILE_FLAG)
-#endif
-#else
-#ifdef _CONTROL_SLAVE_CORE_IMG
-#define USER_RESERVED_MEM HDF_GetMemPoolResSizeConfig(HDF_SLAVE_CORE_FLAG,HDF_VXWORKS_COMPILE_FLAG)
-#else
-#define USER_RESERVED_MEM HDF_GetMemPoolResSizeConfig(HDF_MASTER_CORE_FLAG,HDF_VXWORKS_COMPILE_FLAG)
-#endif
-#endif
-
-#define LOCAL_MEM_LOCAL_ADRS (0x0)
-
-
-
-#ifndef _BSP_BUILD_VXWORKS
-#ifdef _CONTROL_SLAVE_CORE_IMG
-#define LOCAL_MEM_SIZE HDF_GetMemPoolPhyMemTopConfig(HDF_SLAVE_CORE_FLAG,HDF_BOOTROM_COMPILE_FLAG)
-#else
-#define LOCAL_MEM_SIZE HDF_GetMemPoolPhyMemTopConfig(HDF_MASTER_CORE_FLAG,HDF_BOOTROM_COMPILE_FLAG)
-#endif
-#else
-#ifdef _CONTROL_SLAVE_CORE_IMG
-#define LOCAL_MEM_SIZE HDF_GetMemPoolPhyMemTopConfig(HDF_SLAVE_CORE_FLAG,HDF_VXWORKS_COMPILE_FLAG)
-#else
-#define LOCAL_MEM_SIZE HDF_GetMemPoolPhyMemTopConfig(HDF_MASTER_CORE_FLAG,HDF_VXWORKS_COMPILE_FLAG)
-#endif
-
-#endif
-#define LOCAL_MEM_END_ADRS (LOCAL_MEM_LOCAL_ADRS + LOCAL_MEM_SIZE)
-
-
-/*
- * Boot ROM is an image written into Flash. Part of the Flash can be
- * reserved for boot parameters etc. (see the Flash section below).
- *
- * The following parameters are defined here and in the Makefile.
- * They must be kept synchronized; effectively config.h depends on Makefile.
- * Any changes made here must be made in the Makefile and vice versa.
- *
- * ROM_BASE_ADRS is the base of the Flash ROM/EPROM.
- * ROM_TEXT_ADRS is the entry point of the VxWorks image
- * ROM_SIZE is the size of the part of the Flash ROM/EPROM allocated to
- * the VxWorks image (block size - size of headers)
- *
- * Two other constants are used:
- * ROM_COPY_SIZE is the size of the part of the ROM to be copied into RAM
- * (e.g. in uncompressed boot ROM)
- * ROM_SIZE_TOTAL is the size of the entire Flash ROM (used in sysPhysMemDesc)
- *
- * The values are given as literals here to make it easier to ensure
- * that they are the same as those in the Makefile.
- */
-
-#undef RAM_LOW_ADRS
-#undef RAM_HIGH_ADRS
-
-#define IMAGE_LOW_ADRS 0x00a00000
-
-/* VxWorks entry link address */
-#define VXWORKS_ENTRY IMAGE_LOW_ADRS
-
-#ifdef _CONTROL_SLAVE_CORE_IMG
-#define RAM_LOW_ADRS 0x00200000 /* VxWorks image entry point */
-#define RAM_HIGH_ADRS 0x03000000 /* RAM address for ROM boot */
-
-#else
-
-#ifndef _BSP_BUILD_VXWORKS
-#define ROM_BASE_ADRS (HDFINF_GetTextBase())
-#define ROM_TEXT_ADRS (HDFINF_GetTextBase())
-#define RAM_LOW_ADRS 0x05000000 /* VxWorks image entry point */
-#define RAM_HIGH_ADRS 0x06000000 /* RAM address for ROM boot */
-#else
-#define ROM_BASE_ADRS 0x40200000 /* base of Flash/EPROM */
-#define ROM_TEXT_ADRS 0x40200000 /* code start addr in ROM */
-#define RAM_LOW_ADRS IMAGE_LOW_ADRS /* VxWorks image entry point */
-#define RAM_HIGH_ADRS 0x05000000 /* RAM address for ROM boot */
-#endif
-
-#endif
-
-#undef ROM_SIZE
-#define ROM_SIZE 0x00200000 /* size of ROM holding VxWorks*/
-
-
-/*
- * Flash/NVRAM memory configuration
- *
- * A block of the Flash memory (FLASH_SIZE bytes at FLASH_ADRS) is
- * reserved for non-volatile storage of data.
- *
- */
-
-#undef INCLUDE_FLASH
-
-/* Serial port configuration */
-
-#define N_SIO_CHANNELS 3
-
-#undef NUM_TTY
-#define NUM_TTY N_SIO_CHANNELS
-
-#define DEFAULT_BAUD (HDF_GetUartBaudRate())
-
-/* Console baud rate reconfiguration. */
-#undef CONSOLE_BAUD_RATE
-#define CONSOLE_BAUD_RATE DEFAULT_BAUD /* Reconfigure default baud rate */
-
-/*
- * Define SERIAL_DEBUG to enable debugging
- * via the serial ports
- */
-
-#undef SERIAL_DEBUG
-#undef INCLUDE_BOOT_WDB
-
-#undef INCLUDE_WDB
-
-
-
-#if defined(INCLUDE_WDB) || defined (INCLUDE_BOOT_WDB)
-# undef WDB_COMM_TYPE
-# undef WDB_TTY_BAUD
-# undef WDB_TTY_CHANNEL
-# undef WDB_TTY_DEV_NAME
-# ifdef SERIAL_DEBUG
-# define WDB_NO_BAUD_AUTO_CONFIG
-# define WDB_COMM_TYPE WDB_COMM_SERIAL /* WDB in Serial mode */
-# define WDB_TTY_BAUD 38400 /* Baud rate for WDB Connctn */
-# define WDB_TTY_CHANNEL 1 /* COM PORT #2 */
-# define WDB_TTY_DEV_NAME "/tyCo/1" /* deflt TYCODRV_5_2 dev name */
-# else /* SERIAL_DEBUG */
-# define WDB_COMM_TYPE WDB_COMM_END
-# define WDB_TTY_BAUD DEFAULT_BAUD /* Baud rate for WDB Connctn */
-# define WDB_TTY_CHANNEL 0 /* COM PORT #1 */
-# define WDB_TTY_DEV_NAME "/tyCo/0" /* deflt TYCODRV_5_2 dev name */
-# endif /* SERIAL_DEBUG */
-#endif /* INCLUDE_WDB || INCLUDE_BOOT_WDB */
-
-
-/*
- * We use the generic architecture libraries, with caches/MMUs present. A
- * call to sysHwInit0() is needed from within usrInit before
- * cacheLibInit() is called.
- */
-
-/*
- * Cache/MMU configuration
- *
- * Note that when MMU is enabled, cache modes are controlled by
- * the MMU table entries in sysPhysMemDesc[], not the cache mode
- * macros defined here.
- */
-#define SYS_CACHE_UNCACHED_ADRS 0xffffffff/*OMAP35XX_L4_MPU_INTC*/
-
-# undef USER_I_CACHE_MODE
-# define USER_I_CACHE_MODE CACHE_COPYBACK
-
-# undef USER_D_CACHE_MODE
-# define USER_D_CACHE_MODE CACHE_COPYBACK
-
-
-/* Include MMU BASIC and CACHE support for command line and project builds */
-
-# define INCLUDE_MMU_BASIC
-# define INCLUDE_BOOT_MMU_BASIC
-# define INCLUDE_CACHE_SUPPORT
-
-#if defined(INCLUDE_MMU_BASIC) || defined(INCLUDE_MMU_FULL)
-# define INCLUDE_MMU
-#endif /* INCLUDE_MMU_BASIC || INCLUDE_MMU_FULL */
-
-/* Include MMU BASIC and CACHE support for command line and project builds */
-
-# define INCLUDE_MMU_BASIC
-# define INCLUDE_BOOT_MMU_BASIC
-# define INCLUDE_CACHE_SUPPORT
-
-#if defined(INCLUDE_MMU_BASIC) || defined(INCLUDE_MMU_FULL)
-# define INCLUDE_MMU
-#endif /* INCLUDE_MMU_BASIC || INCLUDE_MMU_FULL */
-
-#ifndef MEM_MMU_OFFSET
-#define MEM_MMU_OFFSET 0x00
-#endif
-
-/*
- * Network driver configuration.
- *
- * De-select unused (default) network drivers selected in configAll.h.
- */
-
-#undef INCLUDE_ENP /* include CMC Ethernet interface*/
-#undef INCLUDE_EX /* include Excelan Ethernet interface */
-#undef INCLUDE_SM_NET /* include backplane net interface */
-#undef INCLUDE_SM_SEQ_ADDR /* shared memory network auto address setup */
-
-#define INCLUDE_IPCOM_USE_AUTH_RADIUS
-
-
-/* Enhanced Network Driver (END) Support */
-
-#define INCLUDE_END
-
-#ifdef INCLUDE_END
-# ifndef SERIAL_DEBUG
-# define WBD_AGENT_END
-# else
-# undef WBD_AGENT_END
-# endif /* SERIAL_DEBUG */
-
-#endif /* INCLUDE_END */
-
-#ifdef _BSP_BUILD_VXWORKS
-#ifndef _CONTROL_SLAVE_CORE_IMG
-#if 1
-#define INCLUDE_USB
-#define INCLUDE_USB_INIT
-
-/*ehci*/
-#define INCLUDE_EHCI
-#define INCLUDE_EHCI_INIT
-#define INCLUDE_EHCI_BUS
-
-/*ohci*/
-#define INCLUDE_OHCI
-#define INCLUDE_OHCI_INIT
-#define INCLUDE_OHCI_BUS
-
-/*MASS STORGY device*/
-#define INCLUDE_USB_MS_BULKONLY
-#define INCLUDE_USB_MS_BULKONLY_INIT
-#define INCLUDE_USB_MS_CBI
-#define INCLUDE_USB_MS_CBI_INIT
-#define INCLUDE_NOR_FILESYS
-#endif
-#endif
-#endif
-
-#define INCLUDE_BSP_WATCHDOG
-
-#ifdef _CONTROL_SLAVE_CORE_IMG
-#undef _INCLUDE_FILESYS
-#else
-#define _INCLUDE_FILESYS
-#endif
-
-#undef INCLUDE_TFFS
-
-#ifdef _CONTROL_SLAVE_CORE_IMG
-#undef INCLUDE_DOSFS
-#else
-/*define for FS*/
-#define INCLUDE_DOSFS
-#endif
-
-#define INCLUDE_XBD_RAMDRV /*ramDisk*/
-
-#ifdef INCLUDE_DOSFS
-#define INCLUDE_ERF
-#define INCLUDE_DEVICE_MANAGER
-#define INCLUDE_FS_EVENT_UTIL
-#define INCLUDE_FS_MONITOR
-#define INCLUDE_XBD
-#define INCLUDE_XBD_BLK_DEV
-#define INCLUDE_XBD_TRANS
-#define INCLUDE_DOSFS_DIR_FIXED
-#define INCLUDE_DOSFS_DIR_VFAT
-#define INCLUDE_DOSFS_FAT
-#define INCLUDE_DOSFS_FMT
-#define INCLUDE_DOSFS_CHKDSK
-#define INCLUDE_DOSFS_MAIN
-#endif /* INCLUDE_DOSFS*/
-
-/* I2C not supported */
-#undef INCLUDE_I2C
-
-/* touch screen not supported */
-#undef INCLUDE_TOUCHSCREEN
-
-/*
- * Interrupt mode. Preemptive interrupts are not supported by the interrupt
- * driver so INT_MODE must be set to INT_NON_PREEMPT_MODEL.
- */
-
-#define INT_MODE INT_NON_PREEMPT_MODEL
-
-/*
- * miscellaneous definitions
- * Note: ISR_STACK_SIZE is defined here rather than in ../all/configAll.h
- * (as is more usual) because the stack size depends on the interrupt
- * structure of the BSP.
- */
-
-#define ISR_STACK_SIZE 0x2000 /* size of ISR stack, in bytes */
-
-/* Optional timestamp support */
-
-#undef INCLUDE_TIMESTAMP /* define to include timestamp driver */
-#define INCLUDE_TIMESTAMP
-
-#ifndef INCLUDE_LOADER
-#define INCLUDE_LOADER
-#endif
-#ifndef INCLUDE_LOADER_HOOKS
-#define INCLUDE_LOADER_HOOKS
-#endif
-#ifndef INCLUDE_PTYDRV
-#define INCLUDE_PTYDRV /* pseudo terminal driver */
-#endif
-/*script*/
-#ifndef INCLUDE_STARTUP_SCRIPT
-#define INCLUDE_STARTUP_SCRIPT
-#endif
-
-
-#define INCLUDE_SHELL_INTERP_C /* C interpreter */
-#define INCLUDE_SHELL_INTERP_CMD /* shell command interpreter */
-
-#undef SHELL_COMPATIBLE
-#define SHELL_COMPATIBLE TRUE
-
-#ifndef BSP_BUILD_BASIC_BTRM
-#define INCLUDE_RAWFS
-#define INCLUDE_XBD_RAMDRV
-#endif
-#ifndef _CONTROL_SLAVE_CORE_IMG
-#ifdef _BSP_BUILD_VXWORKS
-#define INCLUDE_SECURITY
-#endif
-#endif
-#ifdef INCLUDE_SECURITY
-#define LOGIN_USER_NAME "target"
-#endif
-
-#include "BrdCommon.h"
-//#include "configExtend.h"
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* __INCconfigh */
-
-
+/* config.h - Mistral OMAP35xx configuration header */
+
+/*
+ * Copyright (c) 2008-2009 Wind River Systems, Inc.
+ * Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+ *
+ * The right to copy, distribute, modify or otherwise make use
+ * of this software may be licensed only pursuant to the terms
+ * of an applicable Wind River license agreement.
+ */
+
+/*
+modification history
+--------------------
+01f,25mar09,m_h add support for copyback cache & RTP
+01e,19mar09,m_h Cache is writethrough not copyback
+01d,19feb09,m_h cleanup
+01c,22jan09,m_h OneNand Flash Support
+01b,24nov08,m_h Configure to add networking
+01a,16jun08,m_h created.
+*/
+
+/*
+DESCRIPTION
+This module contains the configuration parameters for the Mistral OMAP35xx BSP.
+*/
+
+#ifndef __INCconfigh
+#define __INCconfigh
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* BSP version/revision identification, before configAll.h */
+
+#define BSP_VER_1_1 1 /* 1.2 is backwards compatible with 1.1 */
+#define BSP_VER_1_2 1
+#define BSP_VERSION "2.0"
+#define BSP_REV "/0" /* 0 for first revision */
+
+//#include <configAll.h>
+/*
+ * vxbus support
+ */
+#ifdef _BSP_BUILD_VXWORKS
+#define INCLUDE_VXBUS
+#else
+#undef INCLUDE_VXBUS
+#endif
+#ifdef INCLUDE_VXBUS
+#define INCLUDE_HWMEM_ALLOC
+#define INCLUDE_VXB_CMDLINE
+
+#define HWMEM_POOL_SIZE 50000
+
+#endif /* INCLUDE_VXBUS */
+
+/*
+ * SYS_MODEL define
+ *
+ */
+
+#define SYS_MODEL "HISILICON - CortexA9 (ARM)"
+
+
+/* Support network devices */
+#define INCLUDE_NET_DAEMON
+#undef INCLUDE_APPL_LOG_UTIL
+#undef INCLUDE_END2_LINKBUFPOOL
+
+#define DEFAULT_BOOT_LINE \
+ "HiFE(0,0)OMC:vxWorks.bin h=192.168.0.200 e=192.168.0.100 u=aa pw=123"
+
+
+
+#ifndef HDF_MASTER_CORE_FLAG
+#define HDF_MASTER_CORE_FLAG 0
+#define HDF_SLAVE_CORE_FLAG 1
+#define HDF_BOOTROM_COMPILE_FLAG 0
+#define HDF_VXWORKS_COMPILE_FLAG 1
+#endif
+
+
+
+
+
+/* Memory configuration */
+#undef LOCAL_MEM_AUTOSIZE /* run-time memory sizing */
+
+#ifndef _BSP_BUILD_VXWORKS
+#ifdef _CONTROL_SLAVE_CORE_IMG
+#define USER_RESERVED_MEM HDF_GetMemPoolResSizeConfig(HDF_SLAVE_CORE_FLAG,HDF_BOOTROM_COMPILE_FLAG)
+#else
+#define USER_RESERVED_MEM HDF_GetMemPoolResSizeConfig(HDF_MASTER_CORE_FLAG,HDF_BOOTROM_COMPILE_FLAG)
+#endif
+#else
+#ifdef _CONTROL_SLAVE_CORE_IMG
+#define USER_RESERVED_MEM HDF_GetMemPoolResSizeConfig(HDF_SLAVE_CORE_FLAG,HDF_VXWORKS_COMPILE_FLAG)
+#else
+#define USER_RESERVED_MEM HDF_GetMemPoolResSizeConfig(HDF_MASTER_CORE_FLAG,HDF_VXWORKS_COMPILE_FLAG)
+#endif
+#endif
+
+#define LOCAL_MEM_LOCAL_ADRS (0x0)
+
+
+
+#ifndef _BSP_BUILD_VXWORKS
+#ifdef _CONTROL_SLAVE_CORE_IMG
+#define LOCAL_MEM_SIZE HDF_GetMemPoolPhyMemTopConfig(HDF_SLAVE_CORE_FLAG,HDF_BOOTROM_COMPILE_FLAG)
+#else
+#define LOCAL_MEM_SIZE HDF_GetMemPoolPhyMemTopConfig(HDF_MASTER_CORE_FLAG,HDF_BOOTROM_COMPILE_FLAG)
+#endif
+#else
+#ifdef _CONTROL_SLAVE_CORE_IMG
+#define LOCAL_MEM_SIZE HDF_GetMemPoolPhyMemTopConfig(HDF_SLAVE_CORE_FLAG,HDF_VXWORKS_COMPILE_FLAG)
+#else
+#define LOCAL_MEM_SIZE HDF_GetMemPoolPhyMemTopConfig(HDF_MASTER_CORE_FLAG,HDF_VXWORKS_COMPILE_FLAG)
+#endif
+
+#endif
+#define LOCAL_MEM_END_ADRS (LOCAL_MEM_LOCAL_ADRS + LOCAL_MEM_SIZE)
+
+
+/*
+ * Boot ROM is an image written into Flash. Part of the Flash can be
+ * reserved for boot parameters etc. (see the Flash section below).
+ *
+ * The following parameters are defined here and in the Makefile.
+ * They must be kept synchronized; effectively config.h depends on Makefile.
+ * Any changes made here must be made in the Makefile and vice versa.
+ *
+ * ROM_BASE_ADRS is the base of the Flash ROM/EPROM.
+ * ROM_TEXT_ADRS is the entry point of the VxWorks image
+ * ROM_SIZE is the size of the part of the Flash ROM/EPROM allocated to
+ * the VxWorks image (block size - size of headers)
+ *
+ * Two other constants are used:
+ * ROM_COPY_SIZE is the size of the part of the ROM to be copied into RAM
+ * (e.g. in uncompressed boot ROM)
+ * ROM_SIZE_TOTAL is the size of the entire Flash ROM (used in sysPhysMemDesc)
+ *
+ * The values are given as literals here to make it easier to ensure
+ * that they are the same as those in the Makefile.
+ */
+
+#undef RAM_LOW_ADRS
+#undef RAM_HIGH_ADRS
+
+#define IMAGE_LOW_ADRS 0x00a00000
+
+/* VxWorks entry link address */
+#define VXWORKS_ENTRY IMAGE_LOW_ADRS
+
+#ifdef _CONTROL_SLAVE_CORE_IMG
+#define RAM_LOW_ADRS 0x00200000 /* VxWorks image entry point */
+#define RAM_HIGH_ADRS 0x03000000 /* RAM address for ROM boot */
+
+#else
+
+#ifndef _BSP_BUILD_VXWORKS
+#define ROM_BASE_ADRS (HDFINF_GetTextBase())
+#define ROM_TEXT_ADRS (HDFINF_GetTextBase())
+#define RAM_LOW_ADRS 0x05000000 /* VxWorks image entry point */
+#define RAM_HIGH_ADRS 0x06000000 /* RAM address for ROM boot */
+#else
+#define ROM_BASE_ADRS 0x40200000 /* base of Flash/EPROM */
+#define ROM_TEXT_ADRS 0x40200000 /* code start addr in ROM */
+#define RAM_LOW_ADRS IMAGE_LOW_ADRS /* VxWorks image entry point */
+#define RAM_HIGH_ADRS 0x05000000 /* RAM address for ROM boot */
+#endif
+
+#endif
+
+#undef ROM_SIZE
+#define ROM_SIZE 0x00200000 /* size of ROM holding VxWorks*/
+
+
+/*
+ * Flash/NVRAM memory configuration
+ *
+ * A block of the Flash memory (FLASH_SIZE bytes at FLASH_ADRS) is
+ * reserved for non-volatile storage of data.
+ *
+ */
+
+#undef INCLUDE_FLASH
+
+/* Serial port configuration */
+
+#define N_SIO_CHANNELS 3
+
+#undef NUM_TTY
+#define NUM_TTY N_SIO_CHANNELS
+
+#define DEFAULT_BAUD (HDF_GetUartBaudRate())
+
+/* Console baud rate reconfiguration. */
+#undef CONSOLE_BAUD_RATE
+#define CONSOLE_BAUD_RATE DEFAULT_BAUD /* Reconfigure default baud rate */
+
+/*
+ * Define SERIAL_DEBUG to enable debugging
+ * via the serial ports
+ */
+
+#undef SERIAL_DEBUG
+#undef INCLUDE_BOOT_WDB
+
+#undef INCLUDE_WDB
+
+
+
+#if defined(INCLUDE_WDB) || defined (INCLUDE_BOOT_WDB)
+# undef WDB_COMM_TYPE
+# undef WDB_TTY_BAUD
+# undef WDB_TTY_CHANNEL
+# undef WDB_TTY_DEV_NAME
+# ifdef SERIAL_DEBUG
+# define WDB_NO_BAUD_AUTO_CONFIG
+# define WDB_COMM_TYPE WDB_COMM_SERIAL /* WDB in Serial mode */
+# define WDB_TTY_BAUD 38400 /* Baud rate for WDB Connctn */
+# define WDB_TTY_CHANNEL 1 /* COM PORT #2 */
+# define WDB_TTY_DEV_NAME "/tyCo/1" /* deflt TYCODRV_5_2 dev name */
+# else /* SERIAL_DEBUG */
+# define WDB_COMM_TYPE WDB_COMM_END
+# define WDB_TTY_BAUD DEFAULT_BAUD /* Baud rate for WDB Connctn */
+# define WDB_TTY_CHANNEL 0 /* COM PORT #1 */
+# define WDB_TTY_DEV_NAME "/tyCo/0" /* deflt TYCODRV_5_2 dev name */
+# endif /* SERIAL_DEBUG */
+#endif /* INCLUDE_WDB || INCLUDE_BOOT_WDB */
+
+
+/*
+ * We use the generic architecture libraries, with caches/MMUs present. A
+ * call to sysHwInit0() is needed from within usrInit before
+ * cacheLibInit() is called.
+ */
+
+/*
+ * Cache/MMU configuration
+ *
+ * Note that when MMU is enabled, cache modes are controlled by
+ * the MMU table entries in sysPhysMemDesc[], not the cache mode
+ * macros defined here.
+ */
+#define SYS_CACHE_UNCACHED_ADRS 0xffffffff/*OMAP35XX_L4_MPU_INTC*/
+
+# undef USER_I_CACHE_MODE
+# define USER_I_CACHE_MODE CACHE_COPYBACK
+
+# undef USER_D_CACHE_MODE
+# define USER_D_CACHE_MODE CACHE_COPYBACK
+
+
+/* Include MMU BASIC and CACHE support for command line and project builds */
+
+# define INCLUDE_MMU_BASIC
+# define INCLUDE_BOOT_MMU_BASIC
+# define INCLUDE_CACHE_SUPPORT
+
+#if defined(INCLUDE_MMU_BASIC) || defined(INCLUDE_MMU_FULL)
+# define INCLUDE_MMU
+#endif /* INCLUDE_MMU_BASIC || INCLUDE_MMU_FULL */
+
+/* Include MMU BASIC and CACHE support for command line and project builds */
+
+# define INCLUDE_MMU_BASIC
+# define INCLUDE_BOOT_MMU_BASIC
+# define INCLUDE_CACHE_SUPPORT
+
+#if defined(INCLUDE_MMU_BASIC) || defined(INCLUDE_MMU_FULL)
+# define INCLUDE_MMU
+#endif /* INCLUDE_MMU_BASIC || INCLUDE_MMU_FULL */
+
+#ifndef MEM_MMU_OFFSET
+#define MEM_MMU_OFFSET 0x00
+#endif
+
+/*
+ * Network driver configuration.
+ *
+ * De-select unused (default) network drivers selected in configAll.h.
+ */
+
+#undef INCLUDE_ENP /* include CMC Ethernet interface*/
+#undef INCLUDE_EX /* include Excelan Ethernet interface */
+#undef INCLUDE_SM_NET /* include backplane net interface */
+#undef INCLUDE_SM_SEQ_ADDR /* shared memory network auto address setup */
+
+#define INCLUDE_IPCOM_USE_AUTH_RADIUS
+
+
+/* Enhanced Network Driver (END) Support */
+
+#define INCLUDE_END
+
+#ifdef INCLUDE_END
+# ifndef SERIAL_DEBUG
+# define WBD_AGENT_END
+# else
+# undef WBD_AGENT_END
+# endif /* SERIAL_DEBUG */
+
+#endif /* INCLUDE_END */
+
+#ifdef _BSP_BUILD_VXWORKS
+#ifndef _CONTROL_SLAVE_CORE_IMG
+#if 1
+#define INCLUDE_USB
+#define INCLUDE_USB_INIT
+
+/*ehci*/
+#define INCLUDE_EHCI
+#define INCLUDE_EHCI_INIT
+#define INCLUDE_EHCI_BUS
+
+/*ohci*/
+#define INCLUDE_OHCI
+#define INCLUDE_OHCI_INIT
+#define INCLUDE_OHCI_BUS
+
+/*MASS STORGY device*/
+#define INCLUDE_USB_MS_BULKONLY
+#define INCLUDE_USB_MS_BULKONLY_INIT
+#define INCLUDE_USB_MS_CBI
+#define INCLUDE_USB_MS_CBI_INIT
+#define INCLUDE_NOR_FILESYS
+#endif
+#endif
+#endif
+
+#define INCLUDE_BSP_WATCHDOG
+
+#ifdef _CONTROL_SLAVE_CORE_IMG
+#undef _INCLUDE_FILESYS
+#else
+#define _INCLUDE_FILESYS
+#endif
+
+#undef INCLUDE_TFFS
+
+#ifdef _CONTROL_SLAVE_CORE_IMG
+#undef INCLUDE_DOSFS
+#else
+/*define for FS*/
+#define INCLUDE_DOSFS
+#endif
+
+#define INCLUDE_XBD_RAMDRV /*ramDisk*/
+
+#ifdef INCLUDE_DOSFS
+#define INCLUDE_ERF
+#define INCLUDE_DEVICE_MANAGER
+#define INCLUDE_FS_EVENT_UTIL
+#define INCLUDE_FS_MONITOR
+#define INCLUDE_XBD
+#define INCLUDE_XBD_BLK_DEV
+#define INCLUDE_XBD_TRANS
+#define INCLUDE_DOSFS_DIR_FIXED
+#define INCLUDE_DOSFS_DIR_VFAT
+#define INCLUDE_DOSFS_FAT
+#define INCLUDE_DOSFS_FMT
+#define INCLUDE_DOSFS_CHKDSK
+#define INCLUDE_DOSFS_MAIN
+#endif /* INCLUDE_DOSFS*/
+
+/* I2C not supported */
+#undef INCLUDE_I2C
+
+/* touch screen not supported */
+#undef INCLUDE_TOUCHSCREEN
+
+/*
+ * Interrupt mode. Preemptive interrupts are not supported by the interrupt
+ * driver so INT_MODE must be set to INT_NON_PREEMPT_MODEL.
+ */
+
+#define INT_MODE INT_NON_PREEMPT_MODEL
+
+/*
+ * miscellaneous definitions
+ * Note: ISR_STACK_SIZE is defined here rather than in ../all/configAll.h
+ * (as is more usual) because the stack size depends on the interrupt
+ * structure of the BSP.
+ */
+
+#define ISR_STACK_SIZE 0x2000 /* size of ISR stack, in bytes */
+
+/* Optional timestamp support */
+
+#undef INCLUDE_TIMESTAMP /* define to include timestamp driver */
+#define INCLUDE_TIMESTAMP
+
+#ifndef INCLUDE_LOADER
+#define INCLUDE_LOADER
+#endif
+#ifndef INCLUDE_LOADER_HOOKS
+#define INCLUDE_LOADER_HOOKS
+#endif
+#ifndef INCLUDE_PTYDRV
+#define INCLUDE_PTYDRV /* pseudo terminal driver */
+#endif
+/*script*/
+#ifndef INCLUDE_STARTUP_SCRIPT
+#define INCLUDE_STARTUP_SCRIPT
+#endif
+
+
+#define INCLUDE_SHELL_INTERP_C /* C interpreter */
+#define INCLUDE_SHELL_INTERP_CMD /* shell command interpreter */
+
+#undef SHELL_COMPATIBLE
+#define SHELL_COMPATIBLE TRUE
+
+#ifndef BSP_BUILD_BASIC_BTRM
+#define INCLUDE_RAWFS
+#define INCLUDE_XBD_RAMDRV
+#endif
+#ifndef _CONTROL_SLAVE_CORE_IMG
+#ifdef _BSP_BUILD_VXWORKS
+#define INCLUDE_SECURITY
+#endif
+#endif
+#ifdef INCLUDE_SECURITY
+#define LOGIN_USER_NAME "target"
+#endif
+
+#include "BrdCommon.h"
+//#include "configExtend.h"
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __INCconfigh */
+
+
diff --git a/HisiPkg/README b/HisiPkg/README
index 49b2e026b..05f5e851a 100644
--- a/HisiPkg/README
+++ b/HisiPkg/README
@@ -1,49 +1,49 @@
-
-=== D01Board OVERVIEW ===
-
-The project aims to support UEFI for D01 Board using the edk2
-code base.
-
-=== STATUS ===
-
-Current capabilities:
-* Uefi Boot from NORFLASH
-
-=== FUTURE PLANS ===
-
-* Support for PXE, SATA, ACPI, USB
- - KeyBoard, Mouse and MassStorage
-
-=== BUILDING D01 Board ===
-
-Pre-requisites:
-* Build environment capable of build the edk2 MdeModulePkg.
-* A properly configured ASL compiler:
- - Intel ASL compiler: Available from http://www.acpica.org
- - Microsoft ASL compiler: Available from http://www.acpi.info
-
-Build the D01BoardPkg by running from the Workspace
-If you are using armcc as your compiler, you can build the project:
-build -D BIOS_L1 -p HisiPkg/D01BoardPkg/D01BoardPkg.dsc -b DEBUG
-If you are using gcc as your compiler, you can build the project:
- ./uefi-build.sh -b DEBUG d01
-
-Following the edk2 build process, you will find the D01 binaries
-under the $WORKSPACE/Build/*/*/FV directory. You can find the below
-mentioned binary image.
-D01.fd
-
-=== RUNNING D01BoardPkg on the D01 board ===
-* If you can enter into the shell, connet the network cable from the D01 device to the PC terminal
-* Write BIOS to NORFLASH by using comands as follows:
-D01 >ifconfig -s eth0 192.168.10.50 255.255.255.0 192.168.10.1
-D01 >provision 192.168.10.100 -u admin -p admin -f norflash_header
-D01 >writefiletonor 0 norflash_header
-D01 >provision 192.168.10.100 -u admin -p admin -f D01.fd
-D01 >updateL1 D01.fd
-* If the NORFLASH in your board have nothing, you should adopt other method such as JTAG
-* Now the booting device is ready to be used.
-* Connect the Uart cable from the D01 device to the PC terminal.
-* Power ON the Device.
-* The boot message should be visible on the termial.
-* Finally, it should give boot options.
+
+=== D01Board OVERVIEW ===
+
+The project aims to support UEFI for D01 Board using the edk2
+code base.
+
+=== STATUS ===
+
+Current capabilities:
+* Uefi Boot from NORFLASH
+
+=== FUTURE PLANS ===
+
+* Support for PXE, SATA, ACPI, USB
+ - KeyBoard, Mouse and MassStorage
+
+=== BUILDING D01 Board ===
+
+Pre-requisites:
+* Build environment capable of build the edk2 MdeModulePkg.
+* A properly configured ASL compiler:
+ - Intel ASL compiler: Available from http://www.acpica.org
+ - Microsoft ASL compiler: Available from http://www.acpi.info
+
+Build the D01BoardPkg by running from the Workspace
+If you are using armcc as your compiler, you can build the project:
+build -D BIOS_L1 -p HisiPkg/D01BoardPkg/D01BoardPkg.dsc -b DEBUG
+If you are using gcc as your compiler, you can build the project:
+ ./uefi-build.sh -b DEBUG d01
+
+Following the edk2 build process, you will find the D01 binaries
+under the $WORKSPACE/Build/*/*/FV directory. You can find the below
+mentioned binary image.
+D01.fd
+
+=== RUNNING D01BoardPkg on the D01 board ===
+* If you can enter into the shell, connet the network cable from the D01 device to the PC terminal
+* Write BIOS to NORFLASH by using comands as follows:
+D01 >ifconfig -s eth0 192.168.10.50 255.255.255.0 192.168.10.1
+D01 >provision 192.168.10.100 -u admin -p admin -f norflash_header
+D01 >writefiletonor 0 norflash_header
+D01 >provision 192.168.10.100 -u admin -p admin -f D01.fd
+D01 >updateL1 D01.fd
+* If the NORFLASH in your board have nothing, you should adopt other method such as JTAG
+* Now the booting device is ready to be used.
+* Connect the Uart cable from the D01 device to the PC terminal.
+* Power ON the Device.
+* The boot message should be visible on the termial.
+* Finally, it should give boot options.
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-24 17:56:18 +0000