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/*
 * Copyright (c) 2012, ARM Limited. All rights reserved.
 *       
 * Redistribution and use in source and binary forms, with
 * or without modification, are permitted provided that the
 * following conditions are met:
 *     
 * Redistributions of source code must retain the above
 * copyright notice, this list of conditions and the 
 * following disclaimer.
 *
 * Redistributions in binary form must reproduce the
 * above copyright notice, this list of conditions and 
 * the following disclaimer in the documentation 
 * and/or other materials provided with the distribution.
 *      
 * Neither the name of ARM nor the names of its
 * contributors may be used to endorse or promote products
 * derived from this software without specific prior written
 * permission.                        
 */

#include "bl.h"
#include "virtualisor.h"
#include "cache_geom.h"
#include "a7.h"

/* Forward declaration */
static virt_descriptor a7_virt_desc;

extern cache_geometry host_cache_geometry[];
extern cache_geometry target_cache_geometry[];

/*
 * Functions to handle, save, restore and setup any CPU specific traps.
 */
unsigned a7_trap_handle(gp_regs * regs, unsigned hsr, unsigned sibling_cpu)
{
	/*
	 * Correct the L1 instruction cache CCSIDR value which was incorrectly
	 * set in the default CP15 trap handle function.
	 */
	if (hsr >> 26 == TRAP_CP15_32) {
		unsigned Op1, Op2, CRn, CRm, Rt, csselr, level, ind;

		Op2 = (hsr >> 17) & 0x7;
		Op1 = (hsr >> 14) & 0x7;
		CRn = (hsr >> 10) & 0xf;
		Rt = (hsr >> 5) & 0xf;
		CRm = (hsr >> 1) & 0xf;

		csselr = read_csselr();
		level = get_cache_level(csselr);
		ind = get_cache_ind(csselr);

		if (CRn == CRN_C0 && Op1 == 1 && CRm == 0 && Op2 == CCSIDR &&
		    level == 0 && ind == CIND_INST)
			regs->r[Rt] = read_ccsidr();
	}

	return 0;
}

unsigned a7_trap_save(unsigned first_cpu, unsigned sibling_cpu)
{
	return 0;
}

unsigned a7_trap_restore(unsigned first_cpu, unsigned sibling_cpu)
{
	return 0;
}

unsigned a7_trap_setup(unsigned first_cpu, unsigned sibling_cpu)
{
	if (switcher) {

	} else {
		/* Always on */
	}

	/*
	 * Indicate that cpu specific virtualisor setup
	 * has been done. Restore context instead on next
	 * invocation
	 */
	a7_virt_desc.init[read_cpuid()] = 1;
	return 0;
}

static virt_descriptor a7_virt_desc
    __attribute__ ((section("virt_desc_section"))) = {
	A7, {
0}, a7_trap_setup, a7_trap_handle, a7_trap_save, a7_trap_restore,};