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/*
* Copyright (c) 2011, ARM Limited. All rights reserved.
*
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above
* copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
* above copyright notice, this list of conditions and
* the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
*/
#ifndef __TRAPS_H__
#define __TRAPS_H__
#include "misc.h"
/*
* Ignoring the condition field [24:20] for now.
*/
#define HSR_ISS_OP2 (0x7 << 17)
#define HSR_ISS_OP1 (0x7 << 14)
#define HSR_ISS_CRN (0xf << 10)
#define HSR_ISS_CRM (0xf << 1)
#define HSR_ISS_RW (0x1 << 0)
/*
* Macro to convert the cp15 instruction info in the HSR
* into a unique integer. The integer is used to identify
* the handler for that instruction. Format of the integer
* is [Op2:Op1:CRn:CRm:RW]
*/
#define GET_CP15_OP(x) ((x & HSR_ISS_OP2) >> 5) | ((x & HSR_ISS_OP1) >> 5) | ((x & HSR_ISS_CRN) >> 5) |\
(x & HSR_ISS_CRM) | (x & HSR_ISS_RW)
#define MAKE_CP15_OP(op2, op1, crn, crm, rw) ((op2 << 12) | (op1 << 9) | (crn << 5) | (crm << 1) | rw)
#define READ_MIDR MAKE_CP15_OP(0x0, 0x0, 0x0, 0x0, 0x1)
#define READ_MPIDR MAKE_CP15_OP(0x5, 0x0, 0x0, 0x0, 0x1)
#define READ_AUXCTRL MAKE_CP15_OP(0x1, 0x0, 0x1, 0x0, 0x1)
#define WRITE_MIDR MAKE_CP15_OP(0x0, 0x0, 0x0, 0x0, 0x0)
#define WRITE_MPIDR MAKE_CP15_OP(0x5, 0x0, 0x0, 0x0, 0x0)
#define WRITE_AUXCTRL MAKE_CP15_OP(0x1, 0x0, 0x1, 0x0, 0x0)
/*
* Indices into arrays of registers to whom acceses will be
* trapped.
*/
#define AUXCTRL 0x0
#define MIDR 0x1
#define MPIDR 0x2
#define MAX_REGS 0x10
/*
* Indices into array of handlers of the registered traps.
* Numbers correspond to the Exception Class field of HSR.
*/
#define UNKNOWN 0x0
#define MRC_MCR_CP15 0x3
#define MAX_TRAPS 0x25
/*
* Structure to hold the registered traps
*/
typedef struct tlist {
unsigned int hcr;
unsigned int hstr;
} trap_list;
/*
* Structure to hold registers to whom accesses will be trapped
*/
typedef struct rlist {
unsigned int reg[MAX_REGS];
} reg_list;
/*
* Structure to hold platform defined trap handlers
*/
typedef struct hlist {
int (*handle[MAX_TRAPS]) (unsigned int hsr, unsigned int *operand);
} handler_list;
extern trap_list cp15_trap_list[NUM_CPUS];
extern reg_list cp15_reg_list[NUM_CPUS];
extern handler_list plat_handler_list[NUM_CPUS];
#if !DEBUG
#define printf(...)
#endif
#endif /* __TRAPS_H__ */
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