/* * Copyright (c) 2012, ARM Limited. All rights reserved. * * Redistribution and use in source and binary forms, with * or without modification, are permitted provided that the * following conditions are met: * * Redistributions of source code must retain the above * copyright notice, this list of conditions and the * following disclaimer. * * Redistributions in binary form must reproduce the * above copyright notice, this list of conditions and * the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its * contributors may be used to endorse or promote products * derived from this software without specific prior written * permission. */ #ifndef __VGIC_H__ #define __VGIC_H__ #define GIC_ID_PHY_BASE 0x2C001000 /* Physical Distributor */ #define GIC_IC_PHY_BASE 0x2C002000 /* Physical CPU interface */ /* Distributor interface registers */ #define GICD_CTL 0x0 #define GICD_CTR 0x4 #define GICD_SEC 0x80 #define GICD_ENABLESET 0x100 #define GICD_ENABLECLEAR 0x180 #define GICD_PENDINGSET 0x200 #define GICD_PENDINGCLEAR 0x280 #define GICD_ACTIVESET 0x300 #define GICD_ACTIVECLEAR 0x380 #define GICD_PRI 0x400 #define GICD_CPUS 0x800 #define GICD_CONFIG 0xC00 #define GICD_SW 0xF00 #define GICD_CPENDSGIR 0xF10 #define GICD_SPENDSGIR 0xF20 /* Physical CPU Interface registers */ #define GICC_CTL 0x0 #define GICC_PRIMASK 0x4 #define GICC_BP 0x8 #define GICC_INTACK 0xC #define GICC_EOI 0x10 #define GICC_RUNNINGPRI 0x14 #define GICC_HIGHESTPEND 0x18 #define GICC_DEACTIVATE 0x1000 #define GICC_PRIODROP GICC_EOI #endif /* __VGIC_H__ */