;
	; Copyright (c) 2012, ARM Limited. All rights reserved.
	;       
	; Redistribution and use in source and binary forms, with
	; or without modification, are permitted provided that the
	; following conditions are met:
	;     
	; Redistributions of source code must retain the above
	; copyright notice, this list of conditions and the 
	; following disclaimer.
	;
	; Redistributions in binary form must reproduce the
	; above copyright notice, this list of conditions and 
	; the following disclaimer in the documentation 
	; and/or other materials provided with the distribution.
	;      
	; Neither the name of ARM nor the names of its
	; contributors may be used to endorse or promote products
	; derived from this software without specific prior written
	; permission.                        
	; 

;; CPSR Mode bits definitions
USR_MODE         EQU    16
FIQ_MODE         EQU    17
IRQ_MODE         EQU    18
SVC_MODE         EQU    19
MON_MODE         EQU    22
ABT_MODE         EQU    23
UND_MODE         EQU    27
SYS_MODE         EQU    31

;; CPSR mask bit definitions
CPSR_A           EQU  (1<<8)
CPSR_I           EQU  (1<<7)
CPSR_F           EQU  (1<<6)

;; Control Register bits definition
CR_U             EQU  (1<<22)
CR_I             EQU  (1<<12)
CR_C             EQU  (1<<2)
CR_M	         EQU  (1<<0)
CR_W             EQU  (1<<3)
CR_Z             EQU  (1<<11)
CR_XP            EQU  (1<<23)
	
PAGE_MASK	EQU     ~0xfff
	
CLIENT_ACCESS	EQU     0x55555555
MANAGER_ACCESS	EQU     0xffffffff

	END