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Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
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Basically:
$ for f in $(find . -name "*.[ch]"); do indent -linux $f; done
Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
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Completed PMU states handling.
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PMU related functions moved to pmu_trap_handler.c
Changed assembly for save/restore of the PMU context across a cluster switch
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hvc now uses:
r0 : hvc number
r1 : first argument
r2 : second argument
[..]
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The virtualization of the L1 instruction cache is introduced by this patch.
The A7 CPU has a VIPT L1 instruction cache with a cache line length of 32 bytes
whereas the A15 CPU has a PIPT L1 instruction cache with a cache line length of
64 bytes.
Virtualization of the L1 instruction cache does not follow the approach of the
already existing virtualization of the data/unified caches where cache
operations are virtualized on the host cluster to use the values of the target
cluster.
Instead, this patch guarantees that for L1 instruction cache operations on the
A15 CPU, the CCSIDR value of the A7 is used.
The ccsidr member of the structure cache_geometry is now a two dimensional
array being able to hold the appropriate values for the instruction and the
data/unified caches.
In order to be able to trap cache identification registers on the A15 CPU,
regardless if it is on the host or target cluster, the TID2 bit in the HCR
register is set in the A15 CPU specific trap setup function a15_trap_handle()
as well as restored in the A15 CPU specific trap restore function
a15_trap_restore(). This is of course only done if the sibling CPU is an A7.
The default CP15 trap function trap_cp15_mrc_mcr_handle(), which runs before
the CPU specific trap functions, sets the L1 instruction cache CCSIDR value
incorrectly on A7 and A15 for Virtualizer configuration [BC=x, TC=A15, HC=A7].
This error is corrected in the A7 or A15 CPU specific trap handle function.
Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
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CSSELR as a cache id register is trapped on the host cluster and the
corresponding target value is exported. This works fine for read accesses.
However for write accesses, i.e. the selection of the cache level and type,
the information is captured on the host but not migrated to the target.
This can cause problems if a cluster switch takes place between selecting a
cache level and performing the corresponding cache operation.
This patch makes sure that the CSSELR value selected on the host updates the
target cache geometry data structure as well as the physical CSSELR cp15
register.
The CSSELR cp15 register will be saved and restored as part of the architectural
state during the next switch.
Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
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Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
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Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
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When Linux writes to the RST_HOLD0 register to hotplug a cpu, the
virtualizer saves the context and then ask the secure world to
shutdown this particular cpu. All other accesses to the KFSCB are
simply passed to the KFSCB.
Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
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The function handle_kfscb_abort is called when the virtualizer traps
accesses to the KFSCB from Linux. Right now, it only forwards read and
write accesses to the memory.
Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
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Basically:
$ for f in $(find . -name "*.[ch]"; do indent -linux $f; done
Signed-off-by: Robin Randhawa <robin.randhawa@arm.com>
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CSSELR register.
Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
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Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
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Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
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Intended to be the basis for the VSM development.
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This will be the basis for the VSM.
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