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2012-05-23Added more informative comments to the mxscript files.HEADv2.4masterDietmar Eggemann
Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
2012-05-23Update release notes and docs subdirectory to v2.4.Dietmar Eggemann
Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
2012-05-23Change the start address of the root filesystem in the Virtualizer memory map.Dietmar Eggemann
The Virtualizer allows to incorporate a root filesytem up to a size of 32M (0x2000000) by default. The upper limit of the FILESYSTEM section is $(HIBASE)00000. The start address of the FILESYSTEM section FSADDR has to be set to 0x8df00000 ($(HIBASE)00000 - 0x2000000). Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
2012-05-23Cleanup whitespace errors.Dietmar Eggemann
Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
2012-05-23GNU indent pass over C and header files.Dietmar Eggemann
Basically: $ for f in $(find . -name "*.[ch]"); do indent -linux $f; done Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
2012-05-23Add additional cluster startup related RTSM model parameter to the mxscript ↵Dietmar Eggemann
files. Introduce the parameter string dualcluster which for now only contains the model parameter coretile.dualclustersystemconfigurationblock.CFG_ACTIVECLUSTER. It is set to the model's default value 0x1 meaning the model will boot on the primary cluster (A15). Set it to 0x2 to be able to boot from secondary cluster (A7). Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
2012-05-23Enforce supported cluster setup during build process.Dietmar Eggemann
The current Virtualizer only supports configurations where the BOOT_CLUSTER is different than the HOST_CLUSTER. Enforce this in the build process. Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
2012-05-23Add additional RTSM model parameter to the mxscript files.Dietmar Eggemann
Enable Ethernet and user-mode networking and expose the default gatord listening port in user-mode networking. Configure the uarts to ignore the clock rate and transmit/receive serial data immediately. Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
2012-05-23Added new kernel bare-metal application.Dietmar Eggemann
Changed the default payload application, i.e. the binary 'kernel' in the bootwrapper/payload subdirectory. Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
2012-05-23Re-arrange hvc furnction numbers.Dietmar Eggemann
Allign all hvc function numbers into the ARM owned HVC function number range (0x9000 0000 - 0x9FFF FFFF). Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
2012-05-23switcher: Fix incorrect modifiers in the GIC save/restore codeDave Martin
const and volatile were in the wrong places, causing some compiler warnings. This patch corrects the modifiers to match the corresponding function arguments.
2012-05-23switcher: Fix invalid use of memcpy() on I/O memoryDave Martin
The size and order etc. of memory accesses performed by memcpy() is undefined, so we can't make valid use of it to save and restore peripheral registers which don't implement full memory-like semantics, except as may be permitted by luck. In praticular, the GIC rejects byte accesses to its registers, whereas it is entirely valid for memcpy() to perform byte accesses. This patch replaces the invalid use of memcpy() for GIC save/restore with trivial dedicated functions which preform volatile word accesses only.
2012-05-23Change KFSCB base address.Dietmar Eggemann
This patch updates the KFSCB address according to the RS1 memory map. Signed-off-by: Achin Gupta <achin.gupta@arm.com> Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
2012-05-23Debug S&R cp14: BUGFIX: Set DBGOSDLR.DLK=0 manually. FastModel does notAchin Gupta
do this. UPDATE: Cater for hotplug case as well. The OS double lock register needs to be unset to be able to S&R debug context. The FastModels do not do this after a KFSCB reset. So this is checked before restoring the debug context on the inbound cluster. UPDATE: Unsetting the DBGOSDLR.DLK before a restore operation is not enough. A cpu might get migrated to the inbound cluster after being hotplugged and switched. When it is brought back online, its not on the cluster it was originally hotplugged on. The double lock register would not be unset in this case as the restore operation never took place. Accessing any debug register now as a part of a cluster switch would cause an undef instruction abort. Hence the lock needs to be unset even before a save operation
2012-05-23Debug S&R cp14: BUGFIX: Use correct data structure for context s&rAchin Gupta
While saving and restoring the debug context the 'debug_registers_t' data structure was being used instead of 'debug_context_t'. This caused context to be saved at incorrect locations. It got manifested by the corruption of the LR value for the IRQ mode while running the baremetal stress test.
2012-05-23Debug S&R cp14: BUGFIX: Set DBGOSDLR.DLK=0 manually. FastModel does notAchin Gupta
do this. The OS double lock register needs to be unset to be able to S&R debug context. The FastModels do not do this after a KFSCB reset. So this is checked before restoring the debug context on the inbound cluster.
2012-05-23Debug S&R cp14: Added support for cp14 based save/restoreAchin Gupta
1. If the processor implements Debug v7.1 then S&R takes place through the cp14 interface else through the memory mapped interface. 2. Helper functions to save and restore breakpoint and watchpoint context have been used to populate an array so that its possible use them through indices in a 'for' loop. 3. Debug context data structure is reused for S&R through both the memory mapped and the cp14 interface.
2012-05-23Debug S&R cp14: Added helper functions and their prototypesAchin Gupta
Updated Makefile to include debug_helpers.s source file
2012-05-23Debug S&R cp14: Added helper functions and their prototypesAchin Gupta
Moved cp14 helper functions & prototypes to debug_helpers.s & debug_helpers.h respectively.
2012-05-23Debug S&R cp14: Added helper functions and their prototypesAchin Gupta
Seperated the cp14 helper functions used for Debug S&R from the generic cp15 ones. Needed primarily for 16 sets for registers for breakpoints & watchpoints.
2012-05-23Added support for Save & Restore of v7 Debug contextAchin Gupta
Removed dependency of debug S&R code on the APPF repository, moved the data structure to save context to context.h and added calls to save and restore the debug context
2012-05-23HCDR.HPMN was not initialized with the right value. Fixed.Giuseppe Calderaro
2012-05-23Fixed PMCR event counters number on first cluster switch.Giuseppe Calderaro
2012-05-23Fixed Overflow flag (PMOVS Register) save and restore.Giuseppe Calderaro
2012-05-23PMU_CONF_RESET_COUNTER was not enabling PMCR.E bit. Now fixed.Giuseppe Calderaro
2012-05-23Cosmetic changes following code reviewGiuseppe Calderaro
2012-05-23Completed hvc interface implementation.Giuseppe Calderaro
Completed PMU states handling.
2012-05-23vsm: PMU handling.Giuseppe Calderaro
PMU related functions moved to pmu_trap_handler.c Changed assembly for save/restore of the PMU context across a cluster switch
2012-05-23vsm: preparation for PMU handling.Giuseppe Calderaro
Added PMU regs macros. Added PMU function wrappers.
2012-05-23vsm: changed HVC calling convention.Giuseppe Calderaro
hvc now uses: r0 : hvc number r1 : first argument r2 : second argument [..]
2012-05-23Hide differences in I-cache Topology.Dietmar Eggemann
The virtualization of the L1 instruction cache is introduced by this patch. The A7 CPU has a VIPT L1 instruction cache with a cache line length of 32 bytes whereas the A15 CPU has a PIPT L1 instruction cache with a cache line length of 64 bytes. Virtualization of the L1 instruction cache does not follow the approach of the already existing virtualization of the data/unified caches where cache operations are virtualized on the host cluster to use the values of the target cluster. Instead, this patch guarantees that for L1 instruction cache operations on the A15 CPU, the CCSIDR value of the A7 is used. The ccsidr member of the structure cache_geometry is now a two dimensional array being able to hold the appropriate values for the instruction and the data/unified caches. In order to be able to trap cache identification registers on the A15 CPU, regardless if it is on the host or target cluster, the TID2 bit in the HCR register is set in the A15 CPU specific trap setup function a15_trap_handle() as well as restored in the A15 CPU specific trap restore function a15_trap_restore(). This is of course only done if the sibling CPU is an A7. The default CP15 trap function trap_cp15_mrc_mcr_handle(), which runs before the CPU specific trap functions, sets the L1 instruction cache CCSIDR value incorrectly on A7 and A15 for Virtualizer configuration [BC=x, TC=A15, HC=A7]. This error is corrected in the A7 or A15 CPU specific trap handle function. Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
2012-05-23Introduce BOOT_CLUSTER to the switcher.Dietmar Eggemann
Although BOOT_CLUSTER is already known to bootwrapper, it was not accessible from the switcher so far. Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
2012-05-23Migrate CSSELR from host to target.Dietmar Eggemann
CSSELR as a cache id register is trapped on the host cluster and the corresponding target value is exported. This works fine for read accesses. However for write accesses, i.e. the selection of the cache level and type, the information is captured on the host but not migrated to the target. This can cause problems if a cluster switch takes place between selecting a cache level and performing the corresponding cache operation. This patch makes sure that the CSSELR value selected on the host updates the target cache geometry data structure as well as the physical CSSELR cp15 register. The CSSELR cp15 register will be saved and restored as part of the architectural state during the next switch. Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
2012-05-23Change default ASYNC to FALSE.Dietmar Eggemann
This patch changes the default switching mode to synchronous switching. Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
2012-05-23Get booting from A7 cluster working on A15x4-A7x4 model.Dietmar Eggemann
The for loop in wait_for_secondaries() was only considering the array elements cpus_ready[0][j]. In case the A7 cluster is the boot cluster, the secondaries write to the array elements cpus_ready[1][j]. That's why the end condition of the for loop has to be increased by one in the 'switching' case. Please note, that active_clusters is always one in the 'switching' case, whereas it is two in the 'always on' case. To be able to distinguish between these cases, the SWITCHER variable is introduced into the bootwrapper Makefile. Although it is already defined in the big-little Makefile, we do not want to create a shared Makefile between bootwrapper and big-little for now. Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
2012-05-23Introduce BOOT_CLUSTER to allow to boot from A7 cluster.Dietmar Eggemann
Setting BOOT_CLUSTER to 1 and HOST_CLUSTER to 0 allows to boot from cluster 1. It's working for the A15x1-A7x1 model. When using the A15x4-A7x4 model, the primary CPU waits forever for the Secondaries. By default BOOT_CLUSTER is set to 0 and HOST_CLUSTER is set to 1. Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
2012-05-22Virq mig: Clean desc field after enqueuing of virtual interrupt.Dietmar Eggemann
After the receiver of the IPI_MIGRATE_VIRQS finished the virq migration of a particular virtual irq, the appropriate desc field in the migrated_irqs array has to be cleaned, i.e. has to be set to zero. Otherwise, this irq will be considered the next time again when another irq is migrated which shares the same Interrupt Processor Targets Register GICD_ITARGETSRn with the original irq. Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
2012-05-22Virq mig: Set own cpu_id for VIRQ_MIG_DONE event.Dietmar Eggemann
The sender of the IPI_MIGRATE_VIRQS IPI waits for the VIRQ_MIG_DONE event for the cpu_id of the receiver of the IPI. So the receiver should use its own cpu_id instead of the cpu_id of the sender when sending the event. Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
2012-05-22Merge commit 'arm_v2.3' into HEADDietmar Eggemann
2012-05-22Set FM_BETA to false.v2.3Dietmar Eggemann
Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
2012-05-22Change file mode for 100755 to 100644 for various source files.Dietmar Eggemann
Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
2012-05-22Rearrange mxscript files.Dietmar Eggemann
Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
2012-05-22Add a .gitattributes file to setup export-ignore rules.Dietmar Eggemann
Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
2012-05-22Update release notes and docs subdirectory to v2.3 (3).Dietmar Eggemann
Incorporate changes after release notes and docs subdirectory review. Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
2012-05-22Update release notes and docs subdirectory to v2.3 (2).Dietmar Eggemann
Add an additional file to describe the use of Linux cpu hotplug with the Virtualizer into the docs subdirectory and adapt the release notes accordingly. Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
2012-05-22Update release notes and docs subdirectory to v2.3.Dietmar Eggemann
Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
2012-05-22Debug: Added support for Save & Restore of v7 Debug contextDietmar Eggemann
Removed dependency of debug S&R code on the APPF repository, moved the data structure to save context to context.h and added calls to save and restore the debug context. Signed-off-by: Achin Gupta <achin.gupta@arm.com> Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
2012-05-22Virqmig: Fixed code to find out whether an irq has been migratedAchin Gupta
Shifts applied to the cpu interface mask to determine whether an irq in the mask has been re-targetted was incorrect. Also the original and new cpu interface ids were being calculated wrongly due to the same problem Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
2012-05-22Virqmig: Added support for migrating sw maintained virqsDietmar Eggemann
Prior to this patch, while migrating virtual interrupts only the hw list registers were being checked for a !inactive virtual interrupt. It could be present in the sw maintained list of virqs in case of an overflow of the list registers. Hence, the added check. Signed-off-by: Achin Gupta <achin.gupta@arm.com> Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
2012-05-22Virqmig: Complete interoperability with hotplug.Dietmar Eggemann
Signed-off-by: Achin Gupta <achin.gupta@arm.com> Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>