Diffstat (limited to 'Release_Notes.txt')
1 files changed, 98 insertions, 54 deletions
diff --git a/Release_Notes.txt b/Release_Notes.txt
index 8a82c46..3340bde 100644
@@ -53,7 +53,7 @@ Release notes
d. Product status
- ARM Virtualizer for Cortex-A15/Cortex-A7 Task Migration v2.3
+ ARM Virtualizer for Cortex-A15/Cortex-A7 Task Migration v2.4
e. Web address
@@ -71,11 +71,11 @@ Release notes
a. Product release status
- b. ARM Virtualizer software release v2.3
+ b. ARM Virtualizer software release v2.4
- This software release is a v2.3 snapshot of the ARM
+ This software release is a v2.4 snapshot of the ARM
The ARM Virtualizer software is example code that demonstrates
@@ -97,7 +97,7 @@ Release notes
This release contains the following file:
- 1. arm-virtualizer-v2_3-130312.tar.bz2
+ 1. arm-virtualizer-v2_4-170512.tar.bz2
- Contains source code for a basic boot wrapper.
@@ -124,65 +124,99 @@ Release notes
operating system kernel) built for the Cortex-A15 processor
cluster to run un-modified on a Cortex-A7 processor cluster.
- This release does not support execution of software built for the
- Cortex-A7 cluster on the Cortex-A15 cluster.
e. New features
- 1. It is possible to hotplug a cpu using the mechanisms provided
- by the Linux 3.x cpu hotplug implementation. Please refer to
- "docs/07-Linux-cpu-hotplug-howto.txt" for details regarding
- how the Virtualizer software and Linux should be configured
- to support cpu hotplug.
+ 1. Context of the registers specified by the v7.1 Debug architecture
+ is saved and restored during a cluster context switch operation
+ using the mandatory CP14 interface instead of the optional memory
+ mapped interface.
- 2. Context of the registers specified by the v7.1 Debug architecture
- is saved and restored during a cluster context switch operation.
+ Please note that it is not possible to set hardware breakpoints on
+ v7.0 of the big.LITTLE FastModels. This functionality is expected
+ to be available in v7.1 of the FastModels.
- 3. Use of inter-processor interrupts for HYP mode communication has
- been made generic. It is possible to use an IPI for a particular
- type of HYP mode operation. Requesting a cluster switch and
- completing a virtual irq migration operation are the two types of
- HYP mode operations that are currently supported.
+ 2. It is possible to use the Cortex-A7 MP4 processor cluster as the
+ boot cluster provided it is also configured as the target cluster.
+ Refer to "docs/01-Usage.txt" for details.
- f. Known issues
+ 3. A new API is used to request services from the Virtualizer using
+ the ARM "HVC #0" instruction. Details of this API are documented
+ in "docs/09-HVC-calling-conventions.pdf".
- 1. This release does not support execution of software
- built for the Cortex-A7 cluster on the Cortex-A15
+ Existing services which have been changed to adhere to the new
+ standard are:
- 2. This release is intended to be built in a Linux development
- environment. Environments other than Linux are not supported.
+ 1. HVC to invoke a cluster switch
+ 2. HVC to read the physical MPIDR coprocessor register
- 3. The cache level chosen through a write to the CSSELR on the
- Cortex-A7 cluster is not migrated to the Cortex-A15 cluster during
- a subsequent migration.
+ New services which have been implemented using the new standard
- 4. Differences in the characteristics of the I-Cache between the
- Cortex-A7 and Cortex-A15 are not hidden through the use of
- Virtualization extensions by the Virtualizer.
+ 1. Services to enable use of the PMU with the Virtualizer. Details
+ can be found in:
- 5. Save & Restore of Debug context is done only when the memory mapped
- interface is supported. Doing the same using the cp14 interface is
- currently not supported.
- 6. Save & Restore of Debug context is still being tested.
+ f. Known issues
+ 1. This release is intended to be built in a Linux development
+ environment. Environments other than Linux are not supported.
- 7. Bug fix to support migration of virtual interrupts is still being
- tested. [Please see 'v2.2 to v2.3' in Section g.]
+ 2. The v7.0 release of the FastModels does not reset DBGOSDLR.DLK to
+ 0 when a processor is brought out of warm reset. A software
+ workaround has been implemented which clears the DLK field as a part
+ of saving and restoring the context.
- 8. Support for cpu hotplug is still being subject to
- stress tests.
+ 3. Cortex-A15 implements 6 event counters while Cortex-A7 implements 4.
+ The Virtualizer hides this difference by restricting the number of
+ counters visible on Cortex-A15 to 4. Implementing this requires the
+ PMCR.N field to mirror the HDCR.HPMN field. v7.0 of the FastModels
+ are unable to virtualize the PMCR.N field using this method. Hence
+ Counter #5 & #6 should not be used by the payload software. This
+ issue is expected to be fixed in a subsequent release of the
g. Issues resolved since last release
1. Bug fixes
+ v2.3 to v2.4:
- 1. vGIC HYP view interface handling code in (common/vgiclib.c) now
- detects the number of implemented list registers from the vgic
- type register instead of assuming that the maximum (64) will be
+ 1. It is possible to boot the payload software on the Cortex-A7
+ cluster. This means that software built for Cortex-A7 can be
+ run unmodified on the Cortex-A15 cluster.
+ 2. Cortex-A15 has a PIPT I-cache with 64 byte cache lines. Cortex-A7
+ has a VIPT I-cache with 32 byte cache lines. To provide a uniform
+ view of the I-cache topology to the payload software, the
+ Virtualizer exports the Cortex-A7 I-cache topology to Cortex-A15,
+ thus hiding the differences between them.
+ 3. The cache level chosen through a write to the CSSELR on the
+ Cortex-A7 cluster is now migrated to the Cortex-A15 cluster during
+ a subsequent migration.
+ 4. Support added in v2.3 for migrating virtual interrupts as a part
+ of physical interrupt migration required the following fixes:
+ 1. Event for acknowledging transfer of virtual interrupts is
+ now propagated correctly.
+ 2. Data structure used for enqueuing a virtual interrupt is
+ reset correctly.
+ 5. The pre-built stub image used for synchronous cluster switching
+ now prints out the outbound cluster ID and CPU ID. [See
+ docs/01-Usage.txt for details].
+ v2.2 to v2.3:
+ 1. When a physical interrupt is migrated from one cpu interface to
+ another on any cluster, it is possible that its virtual interrupt
+ is in a pending state in the HYP view interface list registers.
+ It is now ensured that the virtual interrupt is also migrated by
+ requesting it to be added to the queue of virtual interrupts on
+ the destination cpu interface.
v2.1 to v2.2:
@@ -220,18 +254,16 @@ Release notes
without taking part in CCI based coherency for a
brief period of time.
- v2.2 to v2.3:
- 1. When a physical interrupt is migrated from one cpu interface to
- another on any cluster, it is possible that its virtual interrupt
- is in a pending state in the HYP view interface list registers.
- It is now ensured that the virtual interrupt is also migrated by
- requesting it to be added to the queue of virtual interrupts on
- the destination cpu interface.
+ 1. vGIC HYP view interface handling code in (common/vgiclib.c) now
+ detects the number of implemented list registers from the vgic
+ type register instead of assuming that the maximum (64) will be
h. Test cases and results
- In accordance with the delivery’s status as example code, testing is
+ In accordance with the delivery's status as example code, testing is
sufficient to prove robustness of the basic implementation but does
not provide full coverage for all use cases.
@@ -274,11 +306,23 @@ Release notes
07-Linux-cpu-hotplug-howto.txt: Instructions & guidelines to
use Linux CPU hotplug.
+ 08-Streamline-and-cluster-switching-howto.txt: Instructions
+ & guidelines to use ARM Streamline tools with the Virtualizer
+ "09-HVC-calling-conventions.pdf": Describes a set of software
+ conventions for Hyper-calls to be used with the ARM
+ virtualization extensions.
+ "10-ARM-Virtualizer-support-for-debug-and-the-PMU.pdf": Describes the
+ Performance Monitor Units on a big.LITTLE system and the interface to
+ these units as provided by the Virtualizer software.
- 1. ARM Development Studio 5 - Version 5.8.
+ 1. ARM Development Studio 5 - Version 5.9.
2. Real-Time System Model v7.0.1 (RTSM_VE_Cortex_A15x1_A7x1