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authorDietmar Eggemann <dietmar.eggemann@arm.com>2012-03-30 14:47:00 +0100
committerDietmar Eggemann <dietmar.eggemann@arm.com>2012-05-23 12:44:34 +0100
commitf977857d403d56af55436ba331cf6314223d2b47 (patch)
tree5121fabf933dd53a1cdf790bb526e2fc6c1624ac
parent70cf0059ecead93195de2644c75df3c2bfa442ba (diff)
Introduce BOOT_CLUSTER to allow to boot from A7 cluster.
Setting BOOT_CLUSTER to 1 and HOST_CLUSTER to 0 allows to boot from cluster 1. It's working for the A15x1-A7x1 model. When using the A15x4-A7x4 model, the primary CPU waits forever for the Secondaries. By default BOOT_CLUSTER is set to 0 and HOST_CLUSTER is set to 1. Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
-rw-r--r--bootwrapper/Makefile2
-rw-r--r--bootwrapper/c_start.c20
2 files changed, 12 insertions, 10 deletions
diff --git a/bootwrapper/Makefile b/bootwrapper/Makefile
index 44434ea..15a6419 100644
--- a/bootwrapper/Makefile
+++ b/bootwrapper/Makefile
@@ -45,6 +45,7 @@ VECTBASE?=$(LOBASE)
HIBASE?=0x8FF
FSADDR?=0x8e400000
DEBUG=TRUE
+BOOT_CLUSTER?=0
ifeq "$(BA)" ""
BOOTARGS=mem=255M console=ttyAMA0,115200 migration_cost=500 cachepolicy=writealloc
@@ -64,6 +65,7 @@ CFLAGS:=--cpu=Eagle -O2 \
-DSETUPMMU=$(SETUPMMU) \
-DHIBASE=$(HIBASE) \
-DVE=$(VE) \
+ -DBOOT_CLUSTER=$(BOOT_CLUSTER) \
-DVECTBASE=$(VECTBASE)
ifdef DEBUG
diff --git a/bootwrapper/c_start.c b/bootwrapper/c_start.c
index 977f59c..d50e214 100644
--- a/bootwrapper/c_start.c
+++ b/bootwrapper/c_start.c
@@ -57,7 +57,7 @@ void setup_gic_nonsecure(unsigned cluster_id, unsigned cpu_id)
/* Ensure all GIC interrupts are Non-Secure */
write32(GIC_ID_PHY_BASE + GICD_SEC + (ctr << 2), 0xffffffff); /* IRQs 0-31 are Non-Secure */
- if (cpu_id == 0 && cluster_id == 0) {
+ if (cpu_id == 0 && cluster_id == BOOT_CLUSTER) {
for (ctr = 1; ctr <= (num_ints >> 5); ctr++)
write32(GIC_ID_PHY_BASE + GICD_SEC + (ctr << 2), 0xffffffff); /* Set all SPIs as non-secure */
}
@@ -69,9 +69,9 @@ void setup_gic_nonsecure(unsigned cluster_id, unsigned cpu_id)
/*
* Function to send wakeup IPI to the secondary CPUs
*/
-void kick(unsigned cpu_id, int secondary_cpus)
+void kick(unsigned cpu_id, unsigned cluster_id, int secondary_cpus)
{
- int cpu_mask = ((1 << (secondary_cpus + 1)) - 1) & ~(1 << cpu_id);
+ int cpu_mask = (((1 << (secondary_cpus + 1)) - 1) & ~(1 << cpu_id)) << (cluster_id << 2);
write32(VE_SYS_BASE + FLAGS_CLR, 0xffffffff); // clear the flags register
write32(VE_SYS_BASE + FLAGS_SET, (unsigned)start); // set the start address in the flags register
@@ -195,7 +195,7 @@ void c_start(void)
write_vbar((unsigned)&vector_table);
write_mvbar((unsigned)&bl_sec_image);
- if (cpu_id == 0 && cluster_id == 0)
+ if (cpu_id == 0 && cluster_id == BOOT_CLUSTER)
config_uart();
enable_user_perfmon_access();
@@ -206,13 +206,13 @@ void c_start(void)
enable_coherency();
/* Also grant NS access to CCI registers */
- if (cpu_id == 0 && cluster_id == 0)
+ if (cpu_id == 0 && cluster_id == BOOT_CLUSTER)
write32(CCI_BASE + SECURE_ACCESS_REG, 0x1);
/*
* Secondaries wait here while initialisation of global peripherals is done
*/
- if (model_pen == 0 && (cpu_id || cluster_id)) {
+ if (model_pen == 0 && (cpu_id || (cluster_id != BOOT_CLUSTER))) {
do {
wfe();
} while (model_pen == 0);
@@ -220,7 +220,7 @@ void c_start(void)
setup_gic_nonsecure(cluster_id, cpu_id);
- if (cpu_id == 0 && cluster_id == 0) {
+ if (cpu_id == 0 && cluster_id == BOOT_CLUSTER) {
model_pen = 1;
dsb();
sev();
@@ -233,16 +233,16 @@ void c_start(void)
write_cntfrq(CP15_TIMER_FREQ);
/* Start secondary CPUs, if any */
- if (cpu_id == 0 && cluster_id == 0 && secondary_cpus > 0) {
+ if (cpu_id == 0 && cluster_id == BOOT_CLUSTER && secondary_cpus > 0) {
printf("Kicking %d secondary CPU(s)\n", secondary_cpus);
drain_uart_fifo();
- kick(cpu_id, secondary_cpus);
+ kick(cpu_id, cluster_id, secondary_cpus);
}
enter_nonsecure_world((unsigned)bl_image);
/* Secondary CPUs go off to secondary_main() */
- if (cpu_id || cluster_id) {
+ if (cpu_id || (cluster_id != BOOT_CLUSTER)) {
secondary_main(cluster_id, cpu_id); /* no return */
}