|author||Dietmar Eggemann <firstname.lastname@example.org>||2012-02-17 14:11:11 +0000|
|committer||Dave Martin <email@example.com>||2012-03-09 11:09:29 +0000|
Update release notes to v2.2 (3).arm_v2.2
Signed-off-by: Dietmar Eggemann <firstname.lastname@example.org>
1 files changed, 10 insertions, 8 deletions
diff --git a/Release_Notes.txt b/Release_Notes.txt
index 6d8f983..3c48778 100644
@@ -139,17 +139,11 @@ Release notes
2. This release is intended to be built in a Linux development
environment. Environments other than Linux are not supported.
- 3. A race condition exists while enabling CCI coherency after a warm
- reset in the Secure world code. This can lead to a case where
- cpus1-3 start restoring the saved context without taking part in
- CCI based coherency for a brief period of time. This results in
- incorrect code behaviour.
- 4. The cache level chosen through a write to the CSSELR on the
+ 3. The cache level chosen through a write to the CSSELR on the
Cortex-A7 cluster is not migrated to the Cortex-A15 cluster during
a subsequent migration.
- 5. Differences in the characteristics of the I-Cache between the
+ 4. Differences in the characteristics of the I-Cache between the
Cortex-A7 and Cortex-A15 are not hidden through the use of
Virtualization extensions by the Virtualizer.
@@ -188,6 +182,14 @@ Release notes
4K memory map of the physical cpu interface of the vGIC (cpu
interface base + 0x1000).
+ 4. Fix race condition during enabling CCI coherency in warm_reset
+ A race condition existed while enabling CCI coherency after a
+ warm reset in the Secure world code. This could have lead to a
+ case where cpus1-3 start restoring the saved context without
+ taking part in CCI based coherency for a brief period of time.
h. Test cases and results
In accordance with the delivery’s status as example code, testing is