Platforms/AMD/Styx: enable SMMUs in the device treestyx-iort

Due to the fact that AMD Seattle maps all its DRAM starting at
physical address 0x80_0000_0000, we currently only support DMA for
devices that can access 40 bits of physical address space.

This is not a problem for the onboard devices, but it would be useful
if we could support arbitrary PCIe plug-in cards, even if they are only
32-bit DMA capable.

Fortunately, there is a ARM (tm) Corelink(r) MMU-401 between the PCIe
root complex and the CPU bus, and so all we need to do is to inform
the OS about this. So add a description of it to the APCI IORT table.

While we're at it, let's describe all the other SMMUs we may be able to
make use of, i.e., 2x SATA and 2x XGBE, as well.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

4 files changed, 124 insertions, 3 deletions

diff --git a/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c b/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c
index b18caf1..093db65 100644
--- a/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c
+++ b/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c
@@ -22,6 +22,7 @@
 #include <Library/DebugLib.h>

 #include <Library/DxeServicesLib.h>

 #include <Library/MemoryAllocationLib.h>

+#include <Library/PcdLib.h>

 #include <Library/PrintLib.h>

 #include <Library/UefiBootServicesTableLib.h>

 

@@ -189,6 +190,46 @@ SetMacAddress (
 

 #endif

 

+STATIC

+VOID

+DisableSmmu (

+  IN  VOID          *Fdt,

+  IN  CONST CHAR8   *IommuPropName,

+  IN  CONST CHAR8   *SmmuNodeName,

+  IN  CONST CHAR8   *DeviceNodeName

+  )

+{

+  INT32   Node;

+  INT32   Error;

+

+  Node = fdt_path_offset (Fdt, DeviceNodeName);

+  if (Node <= 0) {

+    DEBUG ((DEBUG_WARN, "%a: Failed to find path %s: %a\n",

+      __FUNCTION__, DeviceNodeName, fdt_strerror (Node)));

+    return;

+  }

+

+  Error = fdt_delprop (Fdt, Node, IommuPropName);

+  if (Error != 0) {

+    DEBUG ((DEBUG_WARN, "%a: Failed to delete property %a: %a\n",

+      __FUNCTION__, IommuPropName, fdt_strerror (Error)));

+    return;

+  }

+

+  Node = fdt_path_offset (Fdt, SmmuNodeName);

+  if (Node <= 0) {

+    DEBUG ((DEBUG_WARN, "%a: Failed to find path %s: %a\n",

+      __FUNCTION__, SmmuNodeName, fdt_strerror (Node)));

+    return;

+  }

+

+  Error = fdt_del_node (Fdt, Node);

+  if (Error != 0) {

+    DEBUG ((DEBUG_WARN, "%a: Failed to delete node %a: %a\n",

+      __FUNCTION__, SmmuNodeName, fdt_strerror (Error)));

+  }

+}

+

 #define STYX_SOC_VERSION_MASK    0xFFF

 #define STYX_SOC_VERSION_A0      0x000

 #define STYX_SOC_VERSION_B0      0x010

@@ -216,6 +257,16 @@ SetSocIdStatus (
 #else

   SetDeviceStatus (Fdt, "kcs@e0010000", FALSE);

 #endif

+

+  if (!PcdGetBool (PcdEnableSmmus)) {

+    DisableSmmu (Fdt, "iommu-map", "/smb/smmu@e0a00000", "/smb/pcie@f0000000");

+    DisableSmmu (Fdt, "iommus", "/smb/smmu@e0200000", "/smb/sata@e0300000");

+    DisableSmmu (Fdt, "iommus", "/smb/smmu@e0c00000", "/smb/sata@e0d00000");

+#if DO_XGBE

+    DisableSmmu (Fdt, "iommus", "/smb/smmu@e0600000", "/smb/xgmac@e0700000");

+    DisableSmmu (Fdt, "iommus", "/smb/smmu@e0800000", "/smb/xgmac@e0900000");

+#endif

+  }

 }

 

 STATIC

diff --git a/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf b/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf
index 8bb6e9f..fcf2f05 100644
--- a/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf
+++ b/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf
@@ -37,6 +37,7 @@
   DxeServicesLib

   FdtLib

   MemoryAllocationLib

+  PcdLib

   PrintLib

   UefiBootServicesTableLib

 

@@ -44,6 +45,7 @@
   gAmdStyxTokenSpaceGuid.PcdSocCpuId

   gAmdStyxTokenSpaceGuid.PcdEthMacA

   gAmdStyxTokenSpaceGuid.PcdEthMacB

+  gAmdStyxTokenSpaceGuid.PcdEnableSmmus

   gArmTokenSpaceGuid.PcdSystemMemoryBase

 

 [FixedPcd]

diff --git a/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb b/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb
index d380ea8..0d4d6f9 100644
--- a/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb
+++ b/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb
diff --git a/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts b/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts
index b462910..9128223 100644
--- a/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts
+++ b/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts
@@ -122,12 +122,39 @@
 			phandle = <0x3>;

 		};

 

+		sata0_smmu: smmu@e0200000 {

+			compatible = "arm,mmu-401";

+			reg = <0 0xe0200000 0 0x10000>;

+			#global-interrupts = <1>;

+			interrupts = /* Uses combined intr for both

+				       * global and context

+				       */

+				      <0 332 4>,

+				      <0 332 4>;

+			#iommu-cells = <2>;

+			dma-coherent;

+		};

+

+		sata1_smmu: smmu@e0c00000 {

+			compatible = "arm,mmu-401";

+			reg = <0 0xe0c00000 0 0x10000>;

+			#global-interrupts = <1>;

+			interrupts = /* Uses combined intr for both

+				       * global and context

+				       */

+				      <0 331 4>,

+				      <0 331 4>;

+			#iommu-cells = <2>;

+			dma-coherent;

+		};

+

 		sata@e0300000 {

 			compatible = "snps,dwc-ahci";

 			reg = <0x0 0xe0300000 0x0 0xf0000>;

 			interrupts = <0x0 0x163 0x4>;

 			clocks = <0x2>;

 			dma-coherent;

+			iommus = <&sata0_smmu 0x00 0x1f>; /* 0-31 */

 		};

 

 		sata@e0d00000 {

@@ -137,6 +164,7 @@
 			interrupts = <0x0 0x162 0x4>;

 			clocks = <0x2>;

 			dma-coherent;

+			iommus = <&sata1_smmu 0x00 0x1f>; /* 0-31 */

 		};

 

 		i2c@e1000000 {

@@ -257,10 +285,11 @@
 			#address-cells = <0x3>;

 			#size-cells = <0x2>;

 			#interrupt-cells = <0x1>;

+			iommu-map = <0x0 &pcie_smmu 0x0 0x10000>;

 			device_type = "pci";

 			bus-range = <0x0 0x7f>;

 			msi-parent = <0x4>;

-			reg = <0x0 0xf0000000 0x0 0x10000000>;

+			reg = <0x0 0xf0000000 0x0 0x8000000>;

 			interrupt-map-mask = <0xff00 0x0 0x0 0x7>;

 			interrupt-map = <0x1100 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x120 0x1>,

 					<0x1100 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x121 0x1>,

@@ -283,6 +312,19 @@
 				 <0x3000000 0x1 0x00000000 0x1 0x00000000 0x7f 0x00000000>; /* 64-bit MMIO (size= 124G) */

 		};

 

+		pcie_smmu: smmu@e0a00000 {

+			compatible = "arm,mmu-401";

+			reg = <0 0xe0a00000 0 0x10000>;

+			#global-interrupts = <1>;

+			interrupts = /* Uses combined intr for both

+				       * global and context

+				       */

+				      <0 333 4>,

+				      <0 333 4>;

+			#iommu-cells = <1>;

+			dma-coherent;

+		};

+

 		ccn@0xe8000000 {

 			compatible = "arm,ccn-504";

 			reg = <0x0 0xe8000000 0x0 0x1000000>;

@@ -382,6 +424,32 @@
 			phandle = <0xa>;

 		};

 

+		xgmac0_smmu: smmu@e0600000 {

+			compatible = "arm,mmu-401";

+			reg = <0 0xe0600000 0 0x10000>;

+			#global-interrupts = <1>;

+			interrupts = /* Uses combined intr for both

+				       * global and context

+				       */

+				      <0 336 4>,

+				      <0 336 4>;

+			#iommu-cells = <2>;

+			dma-coherent;

+		};

+

+		xgmac1_smmu: smmu@e0800000 {

+			compatible = "arm,mmu-401";

+			reg = <0 0xe0800000 0 0x10000>;

+			#global-interrupts = <1>;

+			interrupts = /* Uses combined intr for both

+				       * global and context

+				       */

+				      <0 335 4>,

+				      <0 335 4>;

+			#iommu-cells = <2>;

+			dma-coherent;

+		};

+

 		xgmac@e0700000 {

 			status = "disabled";

 			compatible = "amd,xgbe-seattle-v1a";

@@ -397,8 +465,8 @@
 			clock-names = "dma_clk", "ptp_clk";

 			phy-handle = <0x9>;

 			phy-mode = "xgmii";

-			#stream-id-cells = <0x18>;

 			dma-coherent;

+			iommus = <&xgmac0_smmu 0x00 0x1f>; /* 0-31 */

 			linux,phandle = <0xb>;

 			phandle = <0xb>;

 		};

@@ -418,8 +486,8 @@
 			clock-names = "dma_clk", "ptp_clk";

 			phy-handle = <0xa>;

 			phy-mode = "xgmii";

-			#stream-id-cells = <0x18>;

 			dma-coherent;

+			iommus = <&xgmac1_smmu 0x00 0x1f>; /* 0-31 */

 			linux,phandle = <0xc>;

 			phandle = <0xc>;

 		};